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authorAlan Mishchenko <alanmi@berkeley.edu>2021-05-11 15:04:15 -0700
committerAlan Mishchenko <alanmi@berkeley.edu>2021-05-11 15:04:15 -0700
commitaa9fe1f24094d0423cc32cbd6e9682ea2a3935cb (patch)
tree33a773bf2a80f88d071719b2f3232d0cc3a4b885 /src/aig/gia/giaGen.c
parent76bed2055cc171109a86bf56c6da00aa4d251a30 (diff)
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Updating LUT synthesis code.
Diffstat (limited to 'src/aig/gia/giaGen.c')
-rw-r--r--src/aig/gia/giaGen.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/aig/gia/giaGen.c b/src/aig/gia/giaGen.c
index 3c813d5c..cb56ef64 100644
--- a/src/aig/gia/giaGen.c
+++ b/src/aig/gia/giaGen.c
@@ -222,6 +222,8 @@ Vec_Wrd_t * Gia_ManSimulateWordsOut( Gia_Man_t * p, Vec_Wrd_t * vSimsIn )
// set output sim info
Gia_ManForEachCoId( p, Id, i )
memcpy( Vec_WrdEntryP(vSimsOut, i*nWords), Vec_WrdEntryP(p->vSims, Id*nWords), sizeof(word)*nWords );
+ Vec_WrdFreeP( &p->vSims );
+ p->nSimWords = -1;
return vSimsOut;
}