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author | Alan Mishchenko <alanmi@berkeley.edu> | 2018-01-28 18:53:20 -0800 |
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committer | Alan Mishchenko <alanmi@berkeley.edu> | 2018-01-28 18:53:20 -0800 |
commit | 99ddb64095b7fdd0d39b29ee04c962c1d8b63d35 (patch) | |
tree | f3fda265fb923fe3cf3163610a117b071219cdea /src/aig/miniaig | |
parent | c8008383cf3a3180701a8527fa3f83a3873aff58 (diff) | |
download | abc-99ddb64095b7fdd0d39b29ee04c962c1d8b63d35.tar.gz abc-99ddb64095b7fdd0d39b29ee04c962c1d8b63d35.tar.bz2 abc-99ddb64095b7fdd0d39b29ee04c962c1d8b63d35.zip |
Adding support of reading and writing designs using a new internal format.
Diffstat (limited to 'src/aig/miniaig')
-rw-r--r-- | src/aig/miniaig/ndr.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/aig/miniaig/ndr.h b/src/aig/miniaig/ndr.h index 22aa33e3..325cf5d9 100644 --- a/src/aig/miniaig/ndr.h +++ b/src/aig/miniaig/ndr.h @@ -379,7 +379,7 @@ static inline void Ndr_ModuleWriteVerilog( char * pFileName, void * pModule, cha } fprintf( pFile, "\nendmodule\n\n" ); - fclose( pFile ); + if ( pFileName ) fclose( pFile ); } @@ -507,6 +507,7 @@ static inline void Ndr_ModuleTest() // write Verilog for verification Ndr_ModuleWriteVerilog( NULL, pModule, ppNames ); + Ndr_ModuleWrite( "add4.ndr", pModule ); Ndr_ModuleDelete( pModule ); } |