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| author | Alan Mishchenko <alanmi@berkeley.edu> | 2022-08-30 13:28:59 -0700 |
|---|---|---|
| committer | Alan Mishchenko <alanmi@berkeley.edu> | 2022-08-30 13:28:59 -0700 |
| commit | 0ed81b34f1048a10aa1b6785c2fb65b526c77b5a (patch) | |
| tree | 25c3a6fae7b6e28d646d3a1c311c5a24bfdb9d7f /src/aig | |
| parent | 138c381f76bcc1106a2fd3dcd40fcaee89c84e81 (diff) | |
| download | abc-0ed81b34f1048a10aa1b6785c2fb65b526c77b5a.tar.gz abc-0ed81b34f1048a10aa1b6785c2fb65b526c77b5a.tar.bz2 abc-0ed81b34f1048a10aa1b6785c2fb65b526c77b5a.zip | |
Compiler warnings.
Diffstat (limited to 'src/aig')
| -rw-r--r-- | src/aig/gia/giaSimBase.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/aig/gia/giaSimBase.c b/src/aig/gia/giaSimBase.c index c8e25f85..75a6d653 100644 --- a/src/aig/gia/giaSimBase.c +++ b/src/aig/gia/giaSimBase.c @@ -3199,7 +3199,7 @@ Vec_Int_t * Gia_ManRelDeriveSimple( Gia_Man_t * p, Vec_Wrd_t * vSims, Vec_Int_t void Gia_ManRelSolve( Gia_Man_t * p, Vec_Wrd_t * vSims, Vec_Int_t * vIns, Vec_Int_t * vOuts, Vec_Int_t * vRel, Vec_Int_t * vDivs ) { - extern Mini_Aig_t * Exa4_ManGenTest( Vec_Wrd_t * vSimsIn, Vec_Wrd_t * vSimsOut, int nIns, int nDivs, int nOuts, int nNodes, int TimeOut, int fOnlyAnd, int fFancy, int fOrderNodes, int fVerbose ); + extern Mini_Aig_t * Exa4_ManGenTest( Vec_Wrd_t * vSimsIn, Vec_Wrd_t * vSimsOut, int nIns, int nDivs, int nOuts, int nNodes, int TimeOut, int fOnlyAnd, int fFancy, int fOrderNodes, int fUniqFans, int fVerbose ); int i, m, iObj, Entry, iMint = 0, nMints = Vec_IntSize(vRel) - Vec_IntCountEntry(vRel, -1); Vec_Wrd_t * vSimsIn = Vec_WrdStart( nMints ); @@ -3232,7 +3232,7 @@ void Gia_ManRelSolve( Gia_Man_t * p, Vec_Wrd_t * vSims, Vec_Int_t * vIns, Vec_In } assert( iMint == nMints ); printf( "Created %d minterms.\n", iMint ); - Exa4_ManGenTest( vSimsIn, vSimsOut, Vec_IntSize(vIns), Vec_IntSize(vDivs), Vec_IntSize(vOuts), 10, 0, 0, 0, 0, 1 ); + Exa4_ManGenTest( vSimsIn, vSimsOut, Vec_IntSize(vIns), Vec_IntSize(vDivs), Vec_IntSize(vOuts), 10, 0, 0, 0, 0, 0, 1 ); Vec_WrdFree( vSimsIn ); Vec_WrdFree( vSimsOut ); } |