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| author | Alan Mishchenko <alanmi@berkeley.edu> | 2018-04-25 16:58:29 -0700 |
|---|---|---|
| committer | Alan Mishchenko <alanmi@berkeley.edu> | 2018-04-25 16:58:29 -0700 |
| commit | fa00219d4c3c207d542215617f87090e630c8e3c (patch) | |
| tree | 463fe9a37e9a160333d5e4cf635085cecfecc103 /src/base/abci | |
| parent | f093aef867a56f825122e28ac56debf9c97972e5 (diff) | |
| download | abc-fa00219d4c3c207d542215617f87090e630c8e3c.tar.gz abc-fa00219d4c3c207d542215617f87090e630c8e3c.tar.bz2 abc-fa00219d4c3c207d542215617f87090e630c8e3c.zip | |
Adding switch &w -p to dump AIG in a Verilog file.
Diffstat (limited to 'src/base/abci')
| -rw-r--r-- | src/base/abci/abc.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/src/base/abci/abc.c b/src/base/abci/abc.c index 6453bcb0..31f3e270 100644 --- a/src/base/abci/abc.c +++ b/src/base/abci/abc.c @@ -29520,17 +29520,21 @@ int Abc_CommandAbc9Write( Abc_Frame_t * pAbc, int argc, char ** argv ) char ** pArgvNew; int c, nArgcNew; int fUnique = 0; + int fVerilog = 0; int fMiniAig = 0; int fMiniLut = 0; int fVerbose = 0; Extra_UtilGetoptReset(); - while ( ( c = Extra_UtilGetopt( argc, argv, "umlvh" ) ) != EOF ) + while ( ( c = Extra_UtilGetopt( argc, argv, "upmlvh" ) ) != EOF ) { switch ( c ) { case 'u': fUnique ^= 1; break; + case 'p': + fVerilog ^= 1; + break; case 'm': fMiniAig ^= 1; break; @@ -29565,6 +29569,8 @@ int Abc_CommandAbc9Write( Abc_Frame_t * pAbc, int argc, char ** argv ) Gia_AigerWriteSimple( pGia, pFileName ); Gia_ManStop( pGia ); } + else if ( fVerilog ) + Gia_ManDumpVerilog( pAbc->pGia, pFileName ); else if ( fMiniAig ) Gia_ManWriteMiniAig( pAbc->pGia, pFileName ); else if ( fMiniLut ) @@ -29574,9 +29580,10 @@ int Abc_CommandAbc9Write( Abc_Frame_t * pAbc, int argc, char ** argv ) return 0; usage: - Abc_Print( -2, "usage: &w [-umlvh] <file>\n" ); + Abc_Print( -2, "usage: &w [-upmlvh] <file>\n" ); Abc_Print( -2, "\t writes the current AIG into the AIGER file\n" ); Abc_Print( -2, "\t-u : toggle writing canonical AIG structure [default = %s]\n", fUnique? "yes" : "no" ); + Abc_Print( -2, "\t-p : toggle writing Verilog with 'and' and 'not' [default = %s]\n", fVerilog? "yes" : "no" ); Abc_Print( -2, "\t-m : toggle writing MiniAIG rather than AIGER [default = %s]\n", fMiniAig? "yes" : "no" ); Abc_Print( -2, "\t-l : toggle writing MiniLUT rather than AIGER [default = %s]\n", fMiniLut? "yes" : "no" ); Abc_Print( -2, "\t-v : toggle verbose output [default = %s]\n", fVerbose? "yes": "no" ); |