diff options
| author | Alan Mishchenko <alanmi@berkeley.edu> | 2012-09-11 18:44:07 -0700 |
|---|---|---|
| committer | Alan Mishchenko <alanmi@berkeley.edu> | 2012-09-11 18:44:07 -0700 |
| commit | 784a3579e578a0c1b44abf60df74e9de54f8b37b (patch) | |
| tree | e9a4c06131bd97fd7a02638fb7027ba8eeafba75 /src/base/io/ioWriteVerilog.c | |
| parent | 759b7c08554991068f249e51107eb3dd42d84670 (diff) | |
| download | abc-784a3579e578a0c1b44abf60df74e9de54f8b37b.tar.gz abc-784a3579e578a0c1b44abf60df74e9de54f8b37b.tar.bz2 abc-784a3579e578a0c1b44abf60df74e9de54f8b37b.zip | |
Fixing Verilog writer's way of writing module names.
Diffstat (limited to 'src/base/io/ioWriteVerilog.c')
| -rw-r--r-- | src/base/io/ioWriteVerilog.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/base/io/ioWriteVerilog.c b/src/base/io/ioWriteVerilog.c index 0b5ad269..6ffed4a7 100644 --- a/src/base/io/ioWriteVerilog.c +++ b/src/base/io/ioWriteVerilog.c @@ -116,7 +116,7 @@ void Io_WriteVerilogInt( FILE * pFile, Abc_Ntk_t * pNtk ) { // write inputs and outputs // fprintf( pFile, "module %s ( gclk,\n ", Abc_NtkName(pNtk) ); - fprintf( pFile, "module %s ( ", Abc_NtkName(pNtk) ); + fprintf( pFile, "module %s ( ", Io_WriteVerilogGetName(Abc_NtkName(pNtk)) ); // add the clock signal if it does not exist if ( Abc_NtkLatchNum(pNtk) > 0 && Nm_ManFindIdByName(pNtk->pManName, "clock", ABC_OBJ_PI) == -1 ) fprintf( pFile, "clock, " ); |