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| author | Alan Mishchenko <alanmi@berkeley.edu> | 2007-06-08 08:01:00 -0700 |
|---|---|---|
| committer | Alan Mishchenko <alanmi@berkeley.edu> | 2007-06-08 08:01:00 -0700 |
| commit | d47752011d94805850f8713258634d1bde5e639f (patch) | |
| tree | 81236dfb564a1d5c3f4a8e2f6cd56f5b5f88313e /src/base/io/ioWriteVerilog.c | |
| parent | feb8fb692e09a2fc7c1da4f2fcf605d398e940f2 (diff) | |
| download | abc-d47752011d94805850f8713258634d1bde5e639f.tar.gz abc-d47752011d94805850f8713258634d1bde5e639f.tar.bz2 abc-d47752011d94805850f8713258634d1bde5e639f.zip | |
Version abc70608
Diffstat (limited to 'src/base/io/ioWriteVerilog.c')
| -rw-r--r-- | src/base/io/ioWriteVerilog.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/base/io/ioWriteVerilog.c b/src/base/io/ioWriteVerilog.c index a02d53fd..a4eeb78f 100644 --- a/src/base/io/ioWriteVerilog.c +++ b/src/base/io/ioWriteVerilog.c @@ -113,7 +113,12 @@ void Io_WriteVerilogInt( FILE * pFile, Abc_Ntk_t * pNtk ) { // write inputs and outputs // fprintf( pFile, "module %s ( gclk,\n ", Abc_NtkName(pNtk) ); - fprintf( pFile, "module %s ( \n ", Abc_NtkName(pNtk) ); + fprintf( pFile, "module %s ( ", Abc_NtkName(pNtk) ); + // add the clock signal if it does not exist + if ( Abc_NtkLatchNum(pNtk) > 0 && Nm_ManFindIdByName(pNtk->pManName, "clock", ABC_OBJ_PI) == -1 ) + fprintf( pFile, "clock, " ); + // write other primary inputs + fprintf( pFile, "\n " ); if ( Abc_NtkPiNum(pNtk) > 0 ) { Io_WriteVerilogPis( pFile, pNtk, 3 ); @@ -435,7 +440,8 @@ void Io_WriteVerilogLatches( FILE * pFile, Abc_Ntk_t * pNtk ) return; // write the latches // fprintf( pFile, " always @(posedge %s) begin\n", Io_WriteVerilogGetName(Abc_ObjFanout0(Abc_NtkPi(pNtk,0))) ); - fprintf( pFile, " always begin\n" ); +// fprintf( pFile, " always begin\n" ); + fprintf( pFile, " always @ (posedge clock) begin\n" ); Abc_NtkForEachLatch( pNtk, pLatch, i ) { fprintf( pFile, " %s", Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanout0(Abc_ObjFanout0(pLatch)))) ); |