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author | Alan Mishchenko <alanmi@berkeley.edu> | 2006-08-24 08:01:00 -0700 |
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committer | Alan Mishchenko <alanmi@berkeley.edu> | 2006-08-24 08:01:00 -0700 |
commit | 735bca1658f92881e12a616f9bdc6a58d0a4c60b (patch) | |
tree | bf38d65e91be84e4086b585c489411876750f041 /src/base/io | |
parent | 7b09d2d28aa81916f9c06f0993f2569a7ad18596 (diff) | |
download | abc-735bca1658f92881e12a616f9bdc6a58d0a4c60b.tar.gz abc-735bca1658f92881e12a616f9bdc6a58d0a4c60b.tar.bz2 abc-735bca1658f92881e12a616f9bdc6a58d0a4c60b.zip |
Version abc60824
Diffstat (limited to 'src/base/io')
-rw-r--r-- | src/base/io/io.c | 6 | ||||
-rw-r--r-- | src/base/io/ioRead.c | 2 | ||||
-rw-r--r-- | src/base/io/ioReadBaf.c | 21 | ||||
-rw-r--r-- | src/base/io/ioReadBlif.c | 2 | ||||
-rw-r--r-- | src/base/io/ioReadEdif.c | 3 | ||||
-rw-r--r-- | src/base/io/ioUtil.c | 18 | ||||
-rw-r--r-- | src/base/io/ioWriteBaf.c | 8 | ||||
-rw-r--r-- | src/base/io/ioWriteBench.c | 2 | ||||
-rw-r--r-- | src/base/io/ioWriteBlif.c | 4 | ||||
-rw-r--r-- | src/base/io/ioWriteVer.c | 20 |
10 files changed, 57 insertions, 29 deletions
diff --git a/src/base/io/io.c b/src/base/io/io.c index 86e8845b..8b80103b 100644 --- a/src/base/io/io.c +++ b/src/base/io/io.c @@ -595,6 +595,9 @@ int IoCommandReadVerilog( Abc_Frame_t * pAbc, int argc, char ** argv ) int fCheck; int c; + printf( "Stand-alone structural Verilog reader is now available as command \"read_ver\".\n" ); + return 0; + fCheck = 1; Extra_UtilGetoptReset(); while ( ( c = Extra_UtilGetopt( argc, argv, "ch" ) ) != EOF ) @@ -629,7 +632,8 @@ int IoCommandReadVerilog( Abc_Frame_t * pAbc, int argc, char ** argv ) fclose( pFile ); // set the new network - pNtk = Io_ReadVerilog( FileName, fCheck ); +// pNtk = Io_ReadVerilog( FileName, fCheck ); + pNtk = NULL; if ( pNtk == NULL ) { fprintf( pAbc->Err, "Reading network from the verilog file has failed.\n" ); diff --git a/src/base/io/ioRead.c b/src/base/io/ioRead.c index 70e648a7..33f23796 100644 --- a/src/base/io/ioRead.c +++ b/src/base/io/ioRead.c @@ -49,7 +49,7 @@ Abc_Ntk_t * Io_Read( char * pFileName, int fCheck ) if ( Extra_FileNameCheckExtension( pFileName, "blif" ) ) pNtk = Io_ReadBlif( pFileName, fCheck ); else if ( Extra_FileNameCheckExtension( pFileName, "v" ) ) - pNtk = Io_ReadVerilog( pFileName, fCheck ); + pNtk = NULL; //Io_ReadVerilog( pFileName, fCheck ); else if ( Extra_FileNameCheckExtension( pFileName, "bench" ) ) pNtk = Io_ReadBench( pFileName, fCheck ); else if ( Extra_FileNameCheckExtension( pFileName, "edf" ) ) diff --git a/src/base/io/ioReadBaf.c b/src/base/io/ioReadBaf.c index 367d693b..15d75ba8 100644 --- a/src/base/io/ioReadBaf.c +++ b/src/base/io/ioReadBaf.c @@ -85,21 +85,30 @@ Abc_Ntk_t * Io_ReadBaf( char * pFileName, int fCheck ) for ( i = 0; i < nInputs; i++ ) { pObj = Abc_NtkCreatePi(pNtkNew); - Abc_NtkLogicStoreName( pObj, pCur ); while ( *pCur++ ); + Abc_ObjAssignName( pObj, pCur, NULL ); while ( *pCur++ ); Vec_PtrPush( vNodes, pObj ); } // create the POs for ( i = 0; i < nOutputs; i++ ) { pObj = Abc_NtkCreatePo(pNtkNew); - Abc_NtkLogicStoreName( pObj, pCur ); while ( *pCur++ ); + Abc_ObjAssignName( pObj, pCur, NULL ); while ( *pCur++ ); } // create the latches for ( i = 0; i < nLatches; i++ ) { pObj = Abc_NtkCreateLatch(pNtkNew); - Abc_NtkLogicStoreName( pObj, pCur ); while ( *pCur++ ); - Vec_PtrPush( vNodes, pObj ); + Abc_ObjAssignName( pObj, pCur, NULL ); while ( *pCur++ ); + + pNode0 = Abc_NtkCreateBo(pNtkNew); + Abc_ObjAssignName( pNode0, pCur, NULL ); while ( *pCur++ ); + + pNode1 = Abc_NtkCreateBi(pNtkNew); + Abc_ObjAssignName( pNode1, pCur, NULL ); while ( *pCur++ ); + Vec_PtrPush( vNodes, pNode1 ); + + Abc_ObjAddFanin( pObj, pNode0 ); + Abc_ObjAddFanin( pNode1, pObj ); } // get the pointer to the beginning of the node array @@ -129,9 +138,9 @@ Abc_Ntk_t * Io_ReadBaf( char * pFileName, int fCheck ) Abc_NtkForEachCo( pNtkNew, pObj, i ) { Num = pBufferNode[2*nAnds+i]; - if ( Abc_ObjIsLatch(pObj) ) + if ( Abc_ObjFanoutNum(pObj) > 0 && Abc_ObjIsLatch(Abc_ObjFanout0(pObj)) ) { - Abc_ObjSetData( pObj, (void *)(Num & 3) ); + Abc_ObjSetData( Abc_ObjFanout0(pObj), (void *)(Num & 3) ); Num >>= 2; } pNode0 = Abc_ObjNotCond( Vec_PtrEntry(vNodes, Num >> 1), Num & 1 ); diff --git a/src/base/io/ioReadBlif.c b/src/base/io/ioReadBlif.c index 5d6bc2f1..535789d2 100644 --- a/src/base/io/ioReadBlif.c +++ b/src/base/io/ioReadBlif.c @@ -621,7 +621,7 @@ int Io_ReadBlifNetworkSubcircuit( Io_ReadBlif_t * p, Vec_Ptr_t * vTokens ) Vec_PtrPush( vNames, Extra_UtilStrsav(pName) ); // memory leak!!! // create a new box and add it to the network - pBox = Abc_NtkCreateBox( p->pNtkCur ); + pBox = Abc_NtkCreateBlackbox( p->pNtkCur ); // set the pointer to the node names Abc_ObjSetData( pBox, vNames ); // remember the line of the file diff --git a/src/base/io/ioReadEdif.c b/src/base/io/ioReadEdif.c index 7c447523..188e5b8c 100644 --- a/src/base/io/ioReadEdif.c +++ b/src/base/io/ioReadEdif.c @@ -46,6 +46,9 @@ Abc_Ntk_t * Io_ReadEdif( char * pFileName, int fCheck ) Extra_FileReader_t * p; Abc_Ntk_t * pNtk; + printf( "Currently this parser does not work!\n" ); + return NULL; + // start the file p = Extra_FileReaderAlloc( pFileName, "#", "\n\r", " \t()" ); if ( p == NULL ) diff --git a/src/base/io/ioUtil.c b/src/base/io/ioUtil.c index 5482eed4..cc51cc1c 100644 --- a/src/base/io/ioUtil.c +++ b/src/base/io/ioUtil.c @@ -116,15 +116,23 @@ Abc_Obj_t * Io_ReadCreateAssert( Abc_Ntk_t * pNtk, char * pName ) ***********************************************************************/ Abc_Obj_t * Io_ReadCreateLatch( Abc_Ntk_t * pNtk, char * pNetLI, char * pNetLO ) { - Abc_Obj_t * pLatch, * pNet; - // create a new latch and add it to the network - pLatch = Abc_NtkCreateLatch( pNtk ); + Abc_Obj_t * pLatch, * pTerm, * pNet; // get the LI net pNet = Abc_NtkFindOrCreateNet( pNtk, pNetLI ); - Abc_ObjAddFanin( pLatch, pNet ); + // add the BO terminal + pTerm = Abc_NtkCreateBo( pNtk ); + Abc_ObjAddFanin( pTerm, pNet ); + // add the latch box + pLatch = Abc_NtkCreateLatch( pNtk ); + Abc_ObjAddFanin( pLatch, pTerm ); + // add the BI terminal + pTerm = Abc_NtkCreateBi( pNtk ); + Abc_ObjAddFanin( pTerm, pLatch ); // get the LO net pNet = Abc_NtkFindOrCreateNet( pNtk, pNetLO ); - Abc_ObjAddFanin( pNet, pLatch ); + Abc_ObjAddFanin( pNet, pTerm ); + // set latch name + Abc_ObjAssignName( pLatch, pNetLO, "_latch" ); return pLatch; } diff --git a/src/base/io/ioWriteBaf.c b/src/base/io/ioWriteBaf.c index 5bba942b..fc0229a4 100644 --- a/src/base/io/ioWriteBaf.c +++ b/src/base/io/ioWriteBaf.c @@ -116,7 +116,11 @@ void Io_WriteBaf( Abc_Ntk_t * pNtk, char * pFileName ) fprintf( pFile, "%s%c", Abc_ObjName(pObj), 0 ); // write latches Abc_NtkForEachLatch( pNtk, pObj, i ) + { fprintf( pFile, "%s%c", Abc_ObjName(pObj), 0 ); + fprintf( pFile, "%s%c", Abc_ObjName(Abc_ObjFanin0(pObj)), 0 ); + fprintf( pFile, "%s%c", Abc_ObjName(Abc_ObjFanout0(pObj)), 0 ); + } // set the node numbers to be used in the output file Abc_NtkCleanCopy( pNtk ); @@ -143,8 +147,8 @@ void Io_WriteBaf( Abc_Ntk_t * pNtk, char * pFileName ) { Extra_ProgressBarUpdate( pProgress, nAnds, NULL ); pBufferNode[nAnds] = (((int)Abc_ObjFanin0(pObj)->pCopy) << 1) | Abc_ObjFaninC0(pObj); - if ( Abc_ObjIsLatch(pObj) ) - pBufferNode[nAnds] = (pBufferNode[nAnds] << 2) | ((unsigned)Abc_ObjData(pObj) & 3); + if ( Abc_ObjFanoutNum(pObj) > 0 && Abc_ObjIsLatch(Abc_ObjFanout0(pObj)) ) + pBufferNode[nAnds] = (pBufferNode[nAnds] << 2) | ((unsigned)Abc_ObjData(Abc_ObjFanout0(pObj)) & 3); nAnds++; } Extra_ProgressBarStop( pProgress ); diff --git a/src/base/io/ioWriteBench.c b/src/base/io/ioWriteBench.c index 26130d38..4cf320b1 100644 --- a/src/base/io/ioWriteBench.c +++ b/src/base/io/ioWriteBench.c @@ -89,7 +89,7 @@ int Io_WriteBenchOne( FILE * pFile, Abc_Ntk_t * pNtk ) fprintf( pFile, "OUTPUT(%s)\n", Abc_ObjName(Abc_ObjFanin0(pNode)) ); Abc_NtkForEachLatch( pNtk, pNode, i ) fprintf( pFile, "%-11s = DFF(%s)\n", - Abc_ObjName(pNode), Abc_ObjName(Abc_ObjFanin0(pNode)) ); + Abc_ObjName(Abc_ObjFanout0(Abc_ObjFanout0(pNode))), Abc_ObjName(Abc_ObjFanin0(Abc_ObjFanin0(pNode))) ); // write internal nodes pProgress = Extra_ProgressBarStart( stdout, Abc_NtkObjNumMax(pNtk) ); diff --git a/src/base/io/ioWriteBlif.c b/src/base/io/ioWriteBlif.c index 8cbd0cd0..3b8c41fa 100644 --- a/src/base/io/ioWriteBlif.c +++ b/src/base/io/ioWriteBlif.c @@ -379,8 +379,8 @@ void Io_NtkWriteLatch( FILE * pFile, Abc_Obj_t * pLatch ) { Abc_Obj_t * pNetLi, * pNetLo; int Reset; - pNetLi = Abc_ObjFanin0( pLatch ); - pNetLo = Abc_ObjFanout0( pLatch ); + pNetLi = Abc_ObjFanin0( Abc_ObjFanin0(pLatch) ); + pNetLo = Abc_ObjFanout0( Abc_ObjFanout0(pLatch) ); Reset = (int)Abc_ObjData( pLatch ); // write the latch line fprintf( pFile, ".latch" ); diff --git a/src/base/io/ioWriteVer.c b/src/base/io/ioWriteVer.c index 2234b3a3..64438b05 100644 --- a/src/base/io/ioWriteVer.c +++ b/src/base/io/ioWriteVer.c @@ -331,7 +331,7 @@ void Io_WriteVerilogWires( FILE * pFile, Abc_Ntk_t * pNtk, int Start ) } Abc_NtkForEachLatch( pNtk, pTerm, i ) { - pNet = Abc_ObjFanin0(pTerm); + pNet = Abc_ObjFanin0(Abc_ObjFanin0(pTerm)); Counter++; // get the line length after this name is written AddedLength = strlen(Abc_ObjName(pNet)) + 2; @@ -377,7 +377,7 @@ void Io_WriteVerilogRegs( FILE * pFile, Abc_Ntk_t * pNtk, int Start ) NameCounter = 0; Abc_NtkForEachLatch( pNtk, pLatch, i ) { - pNet = Abc_ObjFanout0(pLatch); + pNet = Abc_ObjFanout0(Abc_ObjFanout0(pLatch)); Counter++; // get the line length after this name is written AddedLength = strlen(Abc_ObjName(pNet)) + 2; @@ -412,14 +412,14 @@ void Io_WriteVerilogLatches( FILE * pFile, Abc_Ntk_t * pNtk ) Abc_NtkForEachLatch( pNtk, pLatch, i ) { // fprintf( pFile, " always@(posedge gclk) begin %s", Abc_ObjName(Abc_ObjFanout0(pLatch)) ); - fprintf( pFile, " always begin %s", Abc_ObjName(Abc_ObjFanout0(pLatch)) ); - fprintf( pFile, " = %s; end\n", Abc_ObjName(Abc_ObjFanin0(pLatch)) ); + fprintf( pFile, " always begin %s", Abc_ObjName(Abc_ObjFanout0(Abc_ObjFanout0(pLatch))) ); + fprintf( pFile, " = %s; end\n", Abc_ObjName(Abc_ObjFanin0(Abc_ObjFanin0(pLatch))) ); if ( Abc_LatchInit(pLatch) == ABC_INIT_ZERO ) // fprintf( pFile, " initial begin %s = 1\'b0; end\n", Abc_ObjName(Abc_ObjFanout0(pLatch)) ); - fprintf( pFile, " initial begin %s = 0; end\n", Abc_ObjName(Abc_ObjFanout0(pLatch)) ); + fprintf( pFile, " initial begin %s = 0; end\n", Abc_ObjName(Abc_ObjFanout0(Abc_ObjFanout0(pLatch))) ); else if ( Abc_LatchInit(pLatch) == ABC_INIT_ONE ) // fprintf( pFile, " initial begin %s = 1\'b1; end\n", Abc_ObjName(Abc_ObjFanout0(pLatch)) ); - fprintf( pFile, " initial begin %s = 1; end\n", Abc_ObjName(Abc_ObjFanout0(pLatch)) ); + fprintf( pFile, " initial begin %s = 1; end\n", Abc_ObjName(Abc_ObjFanout0(Abc_ObjFanout0(pLatch))) ); } } @@ -431,11 +431,11 @@ void Io_WriteVerilogLatches( FILE * pFile, Abc_Ntk_t * pNtk ) Abc_NtkForEachLatch( pNtk, pLatch, i ) { if ( Abc_LatchInit(pLatch) == ABC_INIT_ZERO ) - fprintf( pFile, " initial begin %s <= 1\'b0; end\n", Abc_ObjName(Abc_ObjFanout0(pLatch)) ); + fprintf( pFile, " initial begin %s <= 1\'b0; end\n", Abc_ObjName(Abc_ObjFanout0(Abc_ObjFanout0(pLatch))) ); else if ( Abc_LatchInit(pLatch) == ABC_INIT_ONE ) - fprintf( pFile, " initial begin %s <= 1\'b1; end\n", Abc_ObjName(Abc_ObjFanout0(pLatch)) ); - fprintf( pFile, " always@(posedge gclk) begin %s", Abc_ObjName(Abc_ObjFanout0(pLatch)) ); - fprintf( pFile, " <= %s; end\n", Abc_ObjName(Abc_ObjFanin0(pLatch)) ); + fprintf( pFile, " initial begin %s <= 1\'b1; end\n", Abc_ObjName(Abc_ObjFanout0(Abc_ObjFanout0(pLatch))) ); + fprintf( pFile, " always@(posedge gclk) begin %s", Abc_ObjName(Abc_ObjFanout0(Abc_ObjFanout0(pLatch))) ); + fprintf( pFile, " <= %s; end\n", Abc_ObjName(Abc_ObjFanin0(Abc_ObjFanin0(pLatch))) ); } } */ |