Adding barrier buffers.

3 files changed, 33 insertions, 11 deletions

diff --git a/src/base/io/ioReadVerilog.c b/src/base/io/ioReadVerilog.c
index 92083580..4907c784 100644
--- a/src/base/io/ioReadVerilog.c
+++ b/src/base/io/ioReadVerilog.c
@@ -88,7 +88,7 @@ Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck )
     }
 
 //Io_WriteVerilog( pNtk, "_temp.v" );
-    Abc_NtkPrintBoxInfo( pNtk );
+//    Abc_NtkPrintBoxInfo( pNtk );
     return pNtk;
 }
 
diff --git a/src/base/io/ioUtil.c b/src/base/io/ioUtil.c
index 685fcf73..24ed029a 100644
--- a/src/base/io/ioUtil.c
+++ b/src/base/io/ioUtil.c
@@ -465,6 +465,7 @@ void Io_Write( Abc_Ntk_t * pNtk, char * pFileName, Io_FileType_t FileType )
 void Io_WriteHie( Abc_Ntk_t * pNtk, char * pBaseName, char * pFileName )
 {
     Abc_Ntk_t * pNtkTemp, * pNtkResult, * pNtkBase = NULL;
+    int i;
     // check if the current network is available
     if ( pNtk == NULL )
     {
@@ -486,7 +487,7 @@ void Io_WriteHie( Abc_Ntk_t * pNtk, char * pBaseName, char * pFileName )
         return;
 
     // flatten logic hierarchy if present
-    if ( Abc_NtkWhiteboxNum(pNtkBase) > 0 )
+    if ( Abc_NtkWhiteboxNum(pNtkBase) > 0 && pNtk->nBarBufs == 0 )
     {
         pNtkBase = Abc_NtkFlattenLogicHierarchy( pNtkTemp = pNtkBase );
         Abc_NtkDelete( pNtkTemp );
@@ -502,7 +503,7 @@ void Io_WriteHie( Abc_Ntk_t * pNtk, char * pBaseName, char * pFileName )
         pNtkResult = Abc_NtkFromBarBufs( pNtkBase, pNtkTemp = pNtkResult );
         Abc_NtkDelete( pNtkTemp );
         if ( pNtkResult )
-            printf( "Hierarchy writer reintroduced %d barbufs.\n", pNtk->nBarBufs );
+            printf( "Hierarchy writer replaced %d barbufs by hierarchy boundaries.\n", pNtk->nBarBufs );
     }
     else if ( Io_ReadFileType(pBaseName) == IO_FILE_BLIFMV ) 
     {
@@ -545,14 +546,32 @@ void Io_WriteHie( Abc_Ntk_t * pNtk, char * pBaseName, char * pFileName )
     // write the resulting network
     if ( Io_ReadFileType(pFileName) == IO_FILE_BLIF )
     {
-        if ( !Abc_NtkHasSop(pNtkResult) && !Abc_NtkHasMapping(pNtkResult) )
-            Abc_NtkToSop( pNtkResult, 0 );
+        if ( pNtkResult->pDesign )
+        {
+            Vec_PtrForEachEntry( Abc_Ntk_t *, pNtkResult->pDesign->vModules, pNtkTemp, i )
+                if ( !Abc_NtkHasSop(pNtkTemp) && !Abc_NtkHasMapping(pNtkTemp) )
+                    Abc_NtkToSop( pNtkTemp, 0 );
+        }
+        else
+        {
+            if ( !Abc_NtkHasSop(pNtkResult) && !Abc_NtkHasMapping(pNtkResult) )
+                Abc_NtkToSop( pNtkResult, 0 );
+        }
         Io_WriteBlif( pNtkResult, pFileName, 1, 0, 0 );
     }
     else if ( Io_ReadFileType(pFileName) == IO_FILE_VERILOG )
     {
-        if ( !Abc_NtkHasAig(pNtkResult) && !Abc_NtkHasMapping(pNtkResult) )
-            Abc_NtkToAig( pNtkResult );
+        if ( pNtkResult->pDesign )
+        {
+            Vec_PtrForEachEntry( Abc_Ntk_t *, pNtkResult->pDesign->vModules, pNtkTemp, i )
+                if ( !Abc_NtkHasAig(pNtkTemp) && !Abc_NtkHasMapping(pNtkTemp) )
+                    Abc_NtkToAig( pNtkTemp );
+        }
+        else
+        {
+            if ( !Abc_NtkHasAig(pNtkResult) && !Abc_NtkHasMapping(pNtkResult) )
+                Abc_NtkToAig( pNtkResult );
+        }
         Io_WriteVerilog( pNtkResult, pFileName );
     }
     else if ( Io_ReadFileType(pFileName) == IO_FILE_BLIFMV )
diff --git a/src/base/io/ioWriteBlif.c b/src/base/io/ioWriteBlif.c
index b1b4f5d0..65546c01 100644
--- a/src/base/io/ioWriteBlif.c
+++ b/src/base/io/ioWriteBlif.c
@@ -98,9 +98,9 @@ void Io_WriteBlif( Abc_Ntk_t * pNtk, char * FileName, int fWriteLatches, int fBb
     // write the master network
     Io_NtkWrite( pFile, pNtk, fWriteLatches, fBb2Wb, fSeq );
     // make sure there is no logic hierarchy
-    assert( Abc_NtkWhiteboxNum(pNtk) == 0 );
+//    assert( Abc_NtkWhiteboxNum(pNtk) == 0 );
     // write the hierarchy if present
-    if ( Abc_NtkBlackboxNum(pNtk) > 0 )
+    if ( Abc_NtkBlackboxNum(pNtk) > 0 || Abc_NtkWhiteboxNum(pNtk) > 0 )
     {
         Vec_PtrForEachEntry( Abc_Ntk_t *, pNtk->pDesign->vModules, pNtkTemp, i )
         {
@@ -235,13 +235,16 @@ void Io_NtkWriteOne( FILE * pFile, Abc_Ntk_t * pNtk, int fWriteLatches, int fBb2
     }
 
     // write the subcircuits
-    assert( Abc_NtkWhiteboxNum(pNtk) == 0 );
-    if ( Abc_NtkBlackboxNum(pNtk) > 0 )
+//    assert( Abc_NtkWhiteboxNum(pNtk) == 0 );
+    if ( Abc_NtkBlackboxNum(pNtk) > 0 || Abc_NtkWhiteboxNum(pNtk) > 0 )
     {
         fprintf( pFile, "\n" );
         Abc_NtkForEachBlackbox( pNtk, pNode, i )
             Io_NtkWriteSubckt( pFile, pNode );
         fprintf( pFile, "\n" );
+        Abc_NtkForEachWhitebox( pNtk, pNode, i )
+            Io_NtkWriteSubckt( pFile, pNode );
+        fprintf( pFile, "\n" );
     }
 
     // write each internal node