C++ portability changes.

4 files changed, 8 insertions, 8 deletions

diff --git a/src/base/abci/abcMap.c b/src/base/abci/abcMap.c
index 7c1c05be..0476ec92 100644
--- a/src/base/abci/abcMap.c
+++ b/src/base/abci/abcMap.c
@@ -66,7 +66,7 @@ Abc_Ntk_t * Abc_NtkMap( Abc_Ntk_t * pNtk, double DelayTarget, double AreaMulti,
     Vec_Int_t * vSwitching = NULL;
     float * pSwitching = NULL;
     clock_t clk, clkTotal = clock();
-    Mio_Library_t * pLib = Abc_FrameReadLibGen();
+    Mio_Library_t * pLib = (Mio_Library_t *)Abc_FrameReadLibGen();
 
     assert( Abc_NtkIsStrash(pNtk) );
 
@@ -102,9 +102,9 @@ Abc_Ntk_t * Abc_NtkMap( Abc_Ntk_t * pNtk, double DelayTarget, double AreaMulti,
 
     // return the library to normal
     if ( AreaMulti != 0.0 )
-        Mio_LibraryMultiArea( Abc_FrameReadLibGen(), -AreaMulti );
+        Mio_LibraryMultiArea( (Mio_Library_t *)Abc_FrameReadLibGen(), -AreaMulti );
     if ( DelayMulti != 0.0 )
-        Mio_LibraryMultiDelay( Abc_FrameReadLibGen(), -DelayMulti );
+        Mio_LibraryMultiDelay( (Mio_Library_t *)Abc_FrameReadLibGen(), -DelayMulti );
 
     // print a warning about choice nodes
     if ( Abc_NtkGetChoiceNum( pNtk ) )
diff --git a/src/base/abci/abcRec2.c b/src/base/abci/abcRec2.c
index c84ea3ea..460fe71d 100644
--- a/src/base/abci/abcRec2.c
+++ b/src/base/abci/abcRec2.c
@@ -163,7 +163,7 @@ static inline int Rec_AppendObj( Abc_ManRec_t2 * p, Rec_Obj_t2 ** pObj )
     if ( p->nRecObjs == p->nRecObjsAlloc )
     {
         assert( p->nRecObjs > 0 );
-        p->pRecObjs = realloc(p->pRecObjs, 2 * p->nRecObjsAlloc * p->recObjSize );
+        p->pRecObjs = ABC_REALLOC( char, p->pRecObjs, 2 * p->nRecObjsAlloc * p->recObjSize );
         memset( p->pRecObjs + p->nRecObjsAlloc * p->recObjSize, 0, p->recObjSize * p->nRecObjsAlloc );
         p->nRecObjsAlloc *= 2;
         hasRealloced = 1;
@@ -2177,7 +2177,7 @@ void Abc_NtkRecCutTruthFromLib2( Gia_Man_t * pGia2, Vec_Ptr_t * vNodes, int nLea
     Vec_PtrForEachEntry( Gia_Obj_t *, vNodes, pObj, i )
     {
         Gia_ObjSetCopyF(pGia2, 0, pObj, i);
-        pSims = Vec_PtrEntry(vTtTemps, i);
+        pSims = (unsigned *)Vec_PtrEntry(vTtTemps, i);
         if ( i < nLeaves )
         {
             Kit_TruthCopy( pSims, (unsigned *)Vec_PtrEntry(vTtElems, i), nInputs );
diff --git a/src/base/abci/abcTim.c b/src/base/abci/abcTim.c
index a9cc4b96..35f1186d 100644
--- a/src/base/abci/abcTim.c
+++ b/src/base/abci/abcTim.c
@@ -385,11 +385,11 @@ void Abc_NtkTestTim( Abc_Ntk_t * pNtk, int fVerbose )
     // create GIA manager (pGia) with hierarhy/timing manager attached (pGia->pManTime)
     // while assuming that some nodes are white boxes (see Abc_NodeIsWhiteBox)
     pGia = Abc_NtkTestTimDeriveGia( pNtk, fVerbose );
-    printf( "Created GIA manager for network with %d white boxes.\n", Tim_ManBoxNum(pGia->pManTime) );
+    printf( "Created GIA manager for network with %d white boxes.\n", Tim_ManBoxNum((Tim_Man_t *)pGia->pManTime) );
 
     // print the timing manager
     if ( fVerbose )
-        Tim_ManPrint( pGia->pManTime );
+        Tim_ManPrint( (Tim_Man_t *)pGia->pManTime );
 
     // test writing both managers into a file and reading them back
     Abc_NtkTestTimByWritingFile( pGia, "test1.aig" );
diff --git a/src/base/io/ioReadBlif.c b/src/base/io/ioReadBlif.c
index bb031200..72f5c9dc 100644
--- a/src/base/io/ioReadBlif.c
+++ b/src/base/io/ioReadBlif.c
@@ -607,7 +607,7 @@ int Io_ReadBlifReorderFormalNames( Vec_Ptr_t * vTokens, Mio_Gate_t * pGate, Mio_
             pName = (char *)Vec_PtrEntry(vTokens, nSize - 1);
             if ( !strncmp( pNamePin, pName, Length ) && pName[Length] == '=' ) // the last entry is pTwin
             {
-                pName = Vec_PtrPop( vTokens );
+                pName = (char *)Vec_PtrPop( vTokens );
                 Vec_PtrPush( vTokens, NULL );
                 Vec_PtrPush( vTokens, pName );
                 return 1;