Version abc61122

56 files changed, 3594 insertions, 1079 deletions

diff --git a/src/base/abc/abc.h b/src/base/abc/abc.h
index f44a8022..c4c42f99 100644
--- a/src/base/abc/abc.h
+++ b/src/base/abc/abc.h
@@ -36,7 +36,7 @@ extern "C" {
 #include <time.h>
 
 #include "cuddInt.h"
-#include "aig.h"
+#include "hop.h"
 #include "extra.h"
 #include "solver.h"
 #include "vec.h"
@@ -178,7 +178,6 @@ struct Abc_Ntk_t_
     Vec_Ptr_t *       vPios;         // the array of PIOs
     Vec_Ptr_t *       vAsserts;      // the array of assertions
     Vec_Ptr_t *       vBoxes;        // the array of boxes
-    Vec_Ptr_t *       vCutSet;       // the array of cutset nodes (used in the sequential AIG)
     // the number of living objects
     int               nObjs;         // the number of live objs
     int nObjCounts[ABC_OBJ_NUMBER];  // the number of objects by type
@@ -196,8 +195,6 @@ struct Abc_Ntk_t_
     Extra_MmStep_t *  pMmStep;       // memory manager for arrays
     void *            pManFunc;      // functionality manager (AIG manager, BDD manager, or memory manager for SOPs)
 //    Abc_Lib_t *       pVerLib;       // for structural verilog designs
-    void *            pManGlob;      // the global BDD manager
-    Vec_Ptr_t *       vFuncsGlob;    // the global BDDs of CO functions
     Abc_ManTime_t *   pManTime;      // the timing manager (for mapped networks) stores arrival/required times for all nodes
     void *            pManCut;       // the cut manager (for AIGs) stores information about the cuts computed for the nodes
     int               LevelMax;      // maximum number of levels
@@ -206,10 +203,8 @@ struct Abc_Ntk_t_
     int *             pModel;        // counter-example (for miters)
     Abc_Ntk_t *       pExdc;         // the EXDC network (if given)
     void *            pData;         // misc
-    // skew values (for latches)
-    float             maxMeanCycle;  // maximum mean cycle time
-    float             globalSkew;    // global skewing
-    Vec_Flt_t *       vSkews;        // endpoint skewing
+    // node attributes
+    Vec_Ptr_t *       vAttrs;        // managers of various node attributes (node functionality, global BDDs, etc)
 };
 
 struct Abc_Lib_t_ 
@@ -282,7 +277,6 @@ static inline int         Abc_NtkCiNum( Abc_Ntk_t * pNtk )           { return Ve
 static inline int         Abc_NtkCoNum( Abc_Ntk_t * pNtk )           { return Vec_PtrSize(pNtk->vCos);            }
 static inline int         Abc_NtkAssertNum( Abc_Ntk_t * pNtk )       { return Vec_PtrSize(pNtk->vAsserts);        }
 static inline int         Abc_NtkBoxNum( Abc_Ntk_t * pNtk )          { return Vec_PtrSize(pNtk->vBoxes);          }
-static inline int         Abc_NtkCutSetNodeNum( Abc_Ntk_t * pNtk )   { return Vec_PtrSize(pNtk->vCutSet);         }
 static inline int         Abc_NtkBiNum( Abc_Ntk_t * pNtk )           { return pNtk->nObjCounts[ABC_OBJ_BI];       }
 static inline int         Abc_NtkBoNum( Abc_Ntk_t * pNtk )           { return pNtk->nObjCounts[ABC_OBJ_BO];       }
 static inline int         Abc_NtkNetNum( Abc_Ntk_t * pNtk )          { return pNtk->nObjCounts[ABC_OBJ_NET];      }
@@ -315,7 +309,6 @@ static inline Abc_Obj_t * Abc_NtkCi( Abc_Ntk_t * pNtk, int i )       { return (A
 static inline Abc_Obj_t * Abc_NtkCo( Abc_Ntk_t * pNtk, int i )       { return (Abc_Obj_t *)Vec_PtrEntry( pNtk->vCos, i );    }
 static inline Abc_Obj_t * Abc_NtkAssert( Abc_Ntk_t * pNtk, int i )   { return (Abc_Obj_t *)Vec_PtrEntry( pNtk->vAsserts, i );}
 static inline Abc_Obj_t * Abc_NtkBox( Abc_Ntk_t * pNtk, int i )      { return (Abc_Obj_t *)Vec_PtrEntry( pNtk->vBoxes, i );  }
-static inline Abc_Obj_t * Abc_NtkCutSetNode( Abc_Ntk_t * pNtk, int i){ return (Abc_Obj_t *)Vec_PtrEntry( pNtk->vCutSet, i ); }
 
 // reading data members of the object
 static inline unsigned    Abc_ObjType( Abc_Obj_t * pObj )            { return pObj->Type;               }
@@ -409,9 +402,12 @@ static inline bool        Abc_LatchIsInit1( Abc_Obj_t * pLatch )     { assert(Ab
 static inline bool        Abc_LatchIsInitDc( Abc_Obj_t * pLatch )    { assert(Abc_ObjIsLatch(pLatch)); return pLatch->pData == (void *)ABC_INIT_DC;   }
 static inline int         Abc_LatchInit( Abc_Obj_t * pLatch )        { assert(Abc_ObjIsLatch(pLatch)); return (int)pLatch->pData;          }
 
-// skewing latches
-static inline void        Abc_NtkSetLatSkew ( Abc_Ntk_t * pNtk, int lat, float skew )  { Vec_FltWriteEntry( pNtk->vSkews, lat, skew ); }
-static inline float       Abc_NtkGetLatSkew ( Abc_Ntk_t * pNtk, int lat )              { if (lat >= Vec_FltSize( pNtk->vSkews )) return 0; else return Vec_FltEntry( pNtk->vSkews, lat ); }
+// global BDDs of the nodes
+static inline void *      Abc_NtkGlobalBdds( Abc_Ntk_t * pNtk )         { return (void *)Vec_PtrEntry(pNtk->vAttrs, VEC_ATTR_GLOBAL_BDD);          }
+static inline DdManager * Abc_NtkGlobalBddMan( Abc_Ntk_t * pNtk )       { return (DdManager *)Vec_AttMan( Abc_NtkGlobalBdds(pNtk) );                  }
+static inline DdNode **   Abc_NtkGlobalBddArray( Abc_Ntk_t * pNtk )     { return (DdNode **)Vec_AttArray( Abc_NtkGlobalBdds(pNtk) );                  }
+static inline DdNode *    Abc_ObjGlobalBdd( Abc_Obj_t * pObj )          { return (DdNode *)Vec_AttEntry( Abc_NtkGlobalBdds(pObj->pNtk), pObj->Id );   }
+static inline void        Abc_ObjSetGlobalBdd( Abc_Obj_t * pObj, DdNode * bF )   { Vec_AttWriteEntry( Abc_NtkGlobalBdds(pObj->pNtk), pObj->Id, bF );              }
 
 // outputs the runtime in seconds
 #define PRT(a,t)  printf("%s = ", (a)); printf("%6.2f sec\n", (float)(t)/(float)(CLOCKS_PER_SEC))
@@ -436,9 +432,6 @@ static inline float       Abc_NtkGetLatSkew ( Abc_Ntk_t * pNtk, int lat )
 #define Abc_AigForEachAnd( pNtk, pNode, i )                                                        \
     for ( i = 0; (i < Vec_PtrSize((pNtk)->vObjs)) && (((pNode) = Abc_NtkObj(pNtk, i)), 1); i++ )   \
         if ( (pNode) == NULL || !Abc_AigNodeIsAnd(pNode) ) {} else
-#define Abc_SeqForEachCutsetNode( pNtk, pNode, i )                                                 \
-    for ( i = 0; (i < Abc_NtkCutSetNodeNum(pNtk)) && (((pNode) = Abc_NtkCutSetNode(pNtk, i)), 1); i++ )\
-        if ( (pNode) == NULL ) {} else
 // various boxes
 #define Abc_NtkForEachBox( pNtk, pObj, i )                                                         \
     for ( i = 0; (i < Vec_PtrSize((pNtk)->vBoxes)) && (((pObj) = Abc_NtkBox(pNtk, i)), 1); i++ )
@@ -489,7 +482,7 @@ extern Abc_Aig_t *        Abc_AigAlloc( Abc_Ntk_t * pNtk );
 extern void               Abc_AigFree( Abc_Aig_t * pMan );
 extern int                Abc_AigCleanup( Abc_Aig_t * pMan );
 extern bool               Abc_AigCheck( Abc_Aig_t * pMan );
-extern int                Abc_AigGetLevelNum( Abc_Ntk_t * pNtk );
+extern int                Abc_AigLevel( Abc_Ntk_t * pNtk );
 extern Abc_Obj_t *        Abc_AigConst1( Abc_Ntk_t * pNtk );
 extern Abc_Obj_t *        Abc_AigAnd( Abc_Aig_t * pMan, Abc_Obj_t * p0, Abc_Obj_t * p1 );
 extern Abc_Obj_t *        Abc_AigAndLookup( Abc_Aig_t * pMan, Abc_Obj_t * p0, Abc_Obj_t * p1 );
@@ -536,7 +529,8 @@ extern Vec_Ptr_t *        Abc_NtkSupport( Abc_Ntk_t * pNtk );
 extern Vec_Ptr_t *        Abc_NtkNodeSupport( Abc_Ntk_t * pNtk, Abc_Obj_t ** ppNodes, int nNodes );
 extern Vec_Ptr_t *        Abc_AigDfs( Abc_Ntk_t * pNtk, int fCollectAll, int fCollectCos );
 extern Vec_Vec_t *        Abc_DfsLevelized( Abc_Obj_t * pNode, bool fTfi );
-extern int                Abc_NtkGetLevelNum( Abc_Ntk_t * pNtk );
+extern int                Abc_NtkLevel( Abc_Ntk_t * pNtk );
+extern int                Abc_NtkLevelReverse( Abc_Ntk_t * pNtk );
 extern bool               Abc_NtkIsAcyclic( Abc_Ntk_t * pNtk );
 extern Vec_Ptr_t *        Abc_AigGetLevelizedOrder( Abc_Ntk_t * pNtk, int fCollectCis );
 /*=== abcFanio.c ==========================================================*/
@@ -652,8 +646,8 @@ extern Abc_Ntk_t *        Abc_NtkAigToLogicSopBench( Abc_Ntk_t * pNtk );
 /*=== abcNtbdd.c ==========================================================*/
 extern Abc_Ntk_t *        Abc_NtkDeriveFromBdd( DdManager * dd, DdNode * bFunc, char * pNamePo, Vec_Ptr_t * vNamesPi );
 extern Abc_Ntk_t *        Abc_NtkBddToMuxes( Abc_Ntk_t * pNtk );
-extern DdManager *        Abc_NtkGlobalBdds( Abc_Ntk_t * pNtk, int fBddSizeMax, int fLatchOnly, int fReorder, int fVerbose );
-extern void               Abc_NtkFreeGlobalBdds( Abc_Ntk_t * pNtk );
+extern DdManager *        Abc_NtkBuildGlobalBdds( Abc_Ntk_t * pNtk, int fBddSizeMax, int fDropInternal, int fReorder, int fVerbose );
+extern DdManager *        Abc_NtkFreeGlobalBdds( Abc_Ntk_t * pNtk, int fFreeMan );
 /*=== abcNtk.c ==========================================================*/
 extern Abc_Ntk_t *        Abc_NtkAlloc( Abc_NtkType_t Type, Abc_NtkFunc_t Func, int fUseMemMan );
 extern Abc_Ntk_t *        Abc_NtkStartFrom( Abc_Ntk_t * pNtk, Abc_NtkType_t Type, Abc_NtkFunc_t Func );
@@ -759,7 +753,7 @@ extern Abc_Ntk_t *        Abc_NtkTopmost( Abc_Ntk_t * pNtk, int nLevels );
 /*=== abcSweep.c ==========================================================*/
 extern int                Abc_NtkSweep( Abc_Ntk_t * pNtk, int fVerbose );
 extern int                Abc_NtkCleanup( Abc_Ntk_t * pNtk, int fVerbose );
-extern int                Abc_NtkCleanupSeq( Abc_Ntk_t * pNtk, int fVerbose );
+extern int                Abc_NtkCleanupSeq( Abc_Ntk_t * pNtk, int fLatchSweep, int fAutoSweep, int fVerbose );
 /*=== abcTiming.c ==========================================================*/
 extern Abc_Time_t *       Abc_NodeReadArrival( Abc_Obj_t * pNode );
 extern Abc_Time_t *       Abc_NodeReadRequired( Abc_Obj_t * pNode );
@@ -782,6 +776,7 @@ extern void               Abc_NodeSetReverseLevel( Abc_Obj_t * pObj, int LevelR
 extern int                Abc_NodeReadReverseLevel( Abc_Obj_t * pObj );
 extern int                Abc_NodeReadRequiredLevel( Abc_Obj_t * pObj );
 /*=== abcUtil.c ==========================================================*/
+extern void *             Abc_NtkAttrFree( Abc_Ntk_t * pNtk, int Attr, int fFreeMan );
 extern void               Abc_NtkIncrementTravId( Abc_Ntk_t * pNtk );
 extern void               Abc_NtkOrderCisCos( Abc_Ntk_t * pNtk );
 extern int                Abc_NtkGetCubeNum( Abc_Ntk_t * pNtk );
diff --git a/src/base/abc/abcAig.c b/src/base/abc/abcAig.c
index ce430cf4..46070a11 100644
--- a/src/base/abc/abcAig.c
+++ b/src/base/abc/abcAig.c
@@ -269,7 +269,7 @@ bool Abc_AigCheck( Abc_Aig_t * pMan )
   SeeAlso     []
 
 ***********************************************************************/
-int Abc_AigGetLevelNum( Abc_Ntk_t * pNtk )
+int Abc_AigLevel( Abc_Ntk_t * pNtk )
 {
     Abc_Obj_t * pNode;
     int i, LevelsMax;
diff --git a/src/base/abc/abcCheck.c b/src/base/abc/abcCheck.c
index eb5a8400..087d5150 100644
--- a/src/base/abc/abcCheck.c
+++ b/src/base/abc/abcCheck.c
@@ -580,12 +580,33 @@ bool Abc_NtkCheckLatch( Abc_Ntk_t * pNtk, Abc_Obj_t * pLatch )
         fprintf( stdout, "NodeCheck: Latch \"%s\" has wrong number (%d) of fanins.\n", Abc_ObjName(pLatch), Abc_ObjFaninNum(pLatch) );
         Value = 0;
     }
-    // make sure the latch has only one fanin
+    // make sure the latch has only one fanout
     if ( Abc_ObjFanoutNum(pLatch) != 1 )
     {
         fprintf( stdout, "NodeCheck: Latch \"%s\" has wrong number (%d) of fanouts.\n", Abc_ObjName(pLatch), Abc_ObjFanoutNum(pLatch) );
         Value = 0;
     }
+    // make sure the latch input has only one fanin
+    if ( Abc_ObjFaninNum(Abc_ObjFanin0(pLatch)) != 1 )
+    {
+        fprintf( stdout, "NodeCheck: Input of latch \"%s\" has wrong number (%d) of fanins.\n", 
+            Abc_ObjName(Abc_ObjFanin0(pLatch)), Abc_ObjFaninNum(Abc_ObjFanin0(pLatch)) );
+        Value = 0;
+    }
+    // make sure the latch input has only one fanout
+    if ( Abc_ObjFanoutNum(Abc_ObjFanin0(pLatch)) != 1 )
+    {
+        fprintf( stdout, "NodeCheck: Input of latch \"%s\" has wrong number (%d) of fanouts.\n", 
+            Abc_ObjName(Abc_ObjFanin0(pLatch)), Abc_ObjFanoutNum(Abc_ObjFanin0(pLatch)) );
+        Value = 0;
+    }
+    // make sure the latch output has only one fanin
+    if ( Abc_ObjFaninNum(Abc_ObjFanout0(pLatch)) != 1 )
+    {
+        fprintf( stdout, "NodeCheck: Output of latch \"%s\" has wrong number (%d) of fanins.\n", 
+            Abc_ObjName(Abc_ObjFanout0(pLatch)), Abc_ObjFaninNum(Abc_ObjFanout0(pLatch)) );
+        Value = 0;
+    }
     return Value;
 }
 
diff --git a/src/base/abc/abcDfs.c b/src/base/abc/abcDfs.c
index a8edfbeb..5a0bf252 100644
--- a/src/base/abc/abcDfs.c
+++ b/src/base/abc/abcDfs.c
@@ -24,12 +24,12 @@
 ///                        DECLARATIONS                              ///
 ////////////////////////////////////////////////////////////////////////
 
+static void     Abc_NtkDfs_iter( Vec_Ptr_t * vStack, Abc_Obj_t * pRoot, Vec_Ptr_t * vNodes );
 static void     Abc_NtkDfs_rec( Abc_Obj_t * pNode, Vec_Ptr_t * vNodes );
 static void     Abc_AigDfs_rec( Abc_Obj_t * pNode, Vec_Ptr_t * vNodes );
 static void     Abc_NtkDfsReverse_rec( Abc_Obj_t * pNode, Vec_Ptr_t * vNodes );
 static void     Abc_NtkNodeSupport_rec( Abc_Obj_t * pNode, Vec_Ptr_t * vNodes );
 static void     Abc_DfsLevelizedTfo_rec( Abc_Obj_t * pNode, Vec_Vec_t * vLevels );
-static int      Abc_NtkGetLevelNum_rec( Abc_Obj_t * pNode );
 static bool     Abc_NtkIsAcyclic_rec( Abc_Obj_t * pNode );
 
 ////////////////////////////////////////////////////////////////////////
@@ -137,6 +137,101 @@ void Abc_NtkDfs_rec( Abc_Obj_t * pNode, Vec_Ptr_t * vNodes )
     Vec_PtrPush( vNodes, pNode );
 }
 
+/**Function*************************************************************
+
+  Synopsis    [Returns the DFS ordered array of logic nodes.]
+
+  Description [Collects only the internal nodes, leaving CIs and CO.
+  However it marks with the current TravId both CIs and COs.]
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Vec_Ptr_t * Abc_NtkDfsIter( Abc_Ntk_t * pNtk, int fCollectAll )
+{
+    Vec_Ptr_t * vNodes, * vStack;
+    Abc_Obj_t * pObj;
+    int i;
+    // set the traversal ID
+    Abc_NtkIncrementTravId( pNtk );
+    // start the array of nodes
+    vNodes = Vec_PtrAlloc( 1000 );
+    vStack = Vec_PtrAlloc( 1000 );
+    Abc_NtkForEachCo( pNtk, pObj, i )
+    {
+        Abc_NodeSetTravIdCurrent( pObj );
+        Abc_NtkDfs_iter( vStack, Abc_ObjFanin0Ntk(Abc_ObjFanin0(pObj)), vNodes );
+    }
+    // collect dangling nodes if asked to
+    if ( fCollectAll )
+    {
+        Abc_NtkForEachNode( pNtk, pObj, i )
+            if ( !Abc_NodeIsTravIdCurrent(pObj) )
+                Abc_NtkDfs_iter( vStack, pObj, vNodes );
+    }
+    Vec_PtrFree( vStack );
+    return vNodes;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Iterative version of the DFS procedure.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Abc_NtkDfs_iter( Vec_Ptr_t * vStack, Abc_Obj_t * pRoot, Vec_Ptr_t * vNodes )
+{
+    Abc_Obj_t * pNode, * pFanin;
+    int iFanin;
+    // if this node is already visited, skip
+    if ( Abc_NodeIsTravIdCurrent( pRoot ) )
+        return;
+    // mark the node as visited
+    Abc_NodeSetTravIdCurrent( pRoot );
+    // skip the CI
+    if ( Abc_ObjIsCi(pRoot) || (Abc_NtkIsStrash(pRoot->pNtk) && Abc_AigNodeIsConst(pRoot)) )
+        return;
+    // add the CI
+    Vec_PtrClear( vStack );
+    Vec_PtrPush( vStack, pRoot );
+    Vec_PtrPush( vStack, (void *)0 );
+    while ( Vec_PtrSize(vStack) > 0 )
+    {
+        // get the node and its fanin
+        iFanin = (int)Vec_PtrPop(vStack);
+        pNode  = Vec_PtrPop(vStack);
+        assert( !Abc_ObjIsNet(pNode) );
+        // add it to the array of nodes if we finished
+        if ( iFanin == Abc_ObjFaninNum(pNode) )
+        {
+            Vec_PtrPush( vNodes, pNode );
+            continue;
+        }
+        // explore the next fanin
+        Vec_PtrPush( vStack, pNode );
+        Vec_PtrPush( vStack, (void *)(iFanin+1) );
+        // get the fanin
+        pFanin = Abc_ObjFanin0Ntk( Abc_ObjFanin(pNode,iFanin) );
+        // if this node is already visited, skip
+        if ( Abc_NodeIsTravIdCurrent( pFanin ) )
+            continue;
+        // mark the node as visited
+        Abc_NodeSetTravIdCurrent( pFanin );
+        // skip the CI
+        if ( Abc_ObjIsCi(pFanin) || (Abc_NtkIsStrash(pFanin->pNtk) && Abc_AigNodeIsConst(pFanin)) )
+            continue;
+        Vec_PtrPush( vStack, pFanin );
+        Vec_PtrPush( vStack, (void *)0 );   
+    }
+}
+
 
 /**Function*************************************************************
 
@@ -593,7 +688,7 @@ void Abc_DfsLevelizedTfo_rec( Abc_Obj_t * pNode, Vec_Vec_t * vLevels )
 
 /**Function*************************************************************
 
-  Synopsis    [Computes the number of logic levels not counting PIs/POs.]
+  Synopsis    [Recursively counts the number of logic levels of one node.]
 
   Description []
                
@@ -602,24 +697,31 @@ void Abc_DfsLevelizedTfo_rec( Abc_Obj_t * pNode, Vec_Vec_t * vLevels )
   SeeAlso     []
 
 ***********************************************************************/
-int Abc_NtkGetLevelNum( Abc_Ntk_t * pNtk )
+int Abc_NtkLevel_rec( Abc_Obj_t * pNode )
 {
-    Abc_Obj_t * pNode;
-    int i, LevelsMax;
-    // set the traversal ID for this traversal
-    Abc_NtkIncrementTravId( pNtk );
-    // set the CI levels to zero
-    Abc_NtkForEachCi( pNtk, pNode, i )
-        pNode->Level = 0;
-    // perform the traversal
-    LevelsMax = 0;
-    Abc_NtkForEachNode( pNtk, pNode, i )
+    Abc_Obj_t * pNext;
+    int i, Level;
+    assert( !Abc_ObjIsNet(pNode) );
+    // skip the PI
+    if ( Abc_ObjIsCi(pNode) )
+        return pNode->Level;
+    assert( Abc_ObjIsNode( pNode ) );
+    // if this node is already visited, return
+    if ( Abc_NodeIsTravIdCurrent( pNode ) )
+        return pNode->Level;
+    // mark the node as visited
+    Abc_NodeSetTravIdCurrent( pNode );
+    // visit the transitive fanin
+    pNode->Level = 0;
+    Abc_ObjForEachFanin( pNode, pNext, i )
     {
-        Abc_NtkGetLevelNum_rec( pNode );
-        if ( LevelsMax < (int)pNode->Level )
-            LevelsMax = (int)pNode->Level;
+        Level = Abc_NtkLevel_rec( Abc_ObjFanin0Ntk(pNext) );
+        if ( pNode->Level < (unsigned)Level )
+            pNode->Level = Level;
     }
-    return LevelsMax;
+    if ( Abc_ObjFaninNum(pNode) > 0 )
+        pNode->Level++;
+    return pNode->Level;
 }
 
 /**Function*************************************************************
@@ -633,18 +735,14 @@ int Abc_NtkGetLevelNum( Abc_Ntk_t * pNtk )
   SeeAlso     []
 
 ***********************************************************************/
-int Abc_NtkGetLevelNum_rec( Abc_Obj_t * pNode )
+int Abc_NtkLevelReverse_rec( Abc_Obj_t * pNode )
 {
-    Abc_Obj_t * pFanin;
+    Abc_Obj_t * pNext;
     int i, Level;
     assert( !Abc_ObjIsNet(pNode) );
-    if ( pNode->Id == 27278 )
-    {
-        int x = 0;        
-    }
     // skip the PI
-    if ( Abc_ObjIsCi(pNode) )
-        return 0;
+    if ( Abc_ObjIsCo(pNode) )
+        return pNode->Level;
     assert( Abc_ObjIsNode( pNode ) );
     // if this node is already visited, return
     if ( Abc_NodeIsTravIdCurrent( pNode ) )
@@ -653,17 +751,76 @@ int Abc_NtkGetLevelNum_rec( Abc_Obj_t * pNode )
     Abc_NodeSetTravIdCurrent( pNode );
     // visit the transitive fanin
     pNode->Level = 0;
-    Abc_ObjForEachFanin( pNode, pFanin, i )
+    Abc_ObjForEachFanout( pNode, pNext, i )
     {
-        Level = Abc_NtkGetLevelNum_rec( Abc_ObjFanin0Ntk(pFanin) );
+        Level = Abc_NtkLevelReverse_rec( Abc_ObjFanout0Ntk(pNext) );
         if ( pNode->Level < (unsigned)Level )
             pNode->Level = Level;
     }
-    if ( Abc_ObjFaninNum(pNode) > 0 )
-        pNode->Level++;
+    pNode->Level++;
     return pNode->Level;
 }
 
+/**Function*************************************************************
+
+  Synopsis    [Computes the number of logic levels not counting PIs/POs.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+int Abc_NtkLevel( Abc_Ntk_t * pNtk )
+{
+    Abc_Obj_t * pNode;
+    int i, LevelsMax;
+    // set the CI levels to zero
+    Abc_NtkForEachCi( pNtk, pNode, i )
+        pNode->Level = 0;
+    // perform the traversal
+    LevelsMax = 0;
+    Abc_NtkIncrementTravId( pNtk );
+    Abc_NtkForEachNode( pNtk, pNode, i )
+    {
+        Abc_NtkLevel_rec( pNode );
+        if ( LevelsMax < (int)pNode->Level )
+            LevelsMax = (int)pNode->Level;
+    }
+    return LevelsMax;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Computes the number of logic levels not counting PIs/POs.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+int Abc_NtkLevelReverse( Abc_Ntk_t * pNtk )
+{
+    Abc_Obj_t * pNode;
+    int i, LevelsMax;
+    // set the CO levels to zero
+    Abc_NtkForEachCo( pNtk, pNode, i )
+        pNode->Level = 0;
+    // perform the traversal
+    LevelsMax = 0;
+    Abc_NtkIncrementTravId( pNtk );
+    Abc_NtkForEachNode( pNtk, pNode, i )
+    {
+        Abc_NtkLevelReverse_rec( pNode );
+        if ( LevelsMax < (int)pNode->Level )
+            LevelsMax = (int)pNode->Level;
+    }
+    return LevelsMax;
+}
+
 
 /**Function*************************************************************
 
diff --git a/src/base/abc/abcFanio.c b/src/base/abc/abcFanio.c
index a988062f..e7ee3405 100644
--- a/src/base/abc/abcFanio.c
+++ b/src/base/abc/abcFanio.c
@@ -50,6 +50,10 @@ void Abc_ObjAddFanin( Abc_Obj_t * pObj, Abc_Obj_t * pFanin )
     Vec_IntPushMem( pObj->pNtk->pMmStep, &pFaninR->vFanouts, pObj->Id    );
     if ( Abc_ObjIsComplement(pFanin) )
         Abc_ObjSetFaninC( pObj, Abc_ObjFaninNum(pObj)-1 );
+    if ( Abc_ObjIsNet(pObj) && Abc_ObjFaninNum(pObj) > 1 )
+    {
+        int x = 0; 
+    }
 }
 
 
diff --git a/src/base/abc/abcFunc.c b/src/base/abc/abcFunc.c
index 23afcd25..e2389fc6 100644
--- a/src/base/abc/abcFunc.c
+++ b/src/base/abc/abcFunc.c
@@ -29,8 +29,8 @@
 #define ABC_MUX_CUBES   100000
 
 static int Abc_ConvertZddToSop( DdManager * dd, DdNode * zCover, char * pSop, int nFanins, Vec_Str_t * vCube, int fPhase );
-static DdNode * Abc_ConvertAigToBdd( DdManager * dd, Aig_Obj_t * pRoot);
-static Aig_Obj_t * Abc_ConvertSopToAig( Aig_Man_t * pMan, char * pSop );
+static DdNode * Abc_ConvertAigToBdd( DdManager * dd, Hop_Obj_t * pRoot);
+static Hop_Obj_t * Abc_ConvertSopToAig( Hop_Man_t * pMan, char * pSop );
 
 ////////////////////////////////////////////////////////////////////////
 ///                     FUNCTION DEFINITIONS                         ///
@@ -533,13 +533,13 @@ int Abc_CountZddCubes( DdManager * dd, DdNode * zCover )
 int Abc_NtkSopToAig( Abc_Ntk_t * pNtk )
 {
     Abc_Obj_t * pNode;
-    Aig_Man_t * pMan;
+    Hop_Man_t * pMan;
     int i;
 
     assert( Abc_NtkIsSopLogic(pNtk) || Abc_NtkIsSopNetlist(pNtk) ); 
 
     // start the functionality manager
-    pMan = Aig_ManStart();
+    pMan = Hop_ManStart();
 
     // convert each node from SOP to BDD
     Abc_NtkForEachNode( pNtk, pNode, i )
@@ -572,32 +572,32 @@ int Abc_NtkSopToAig( Abc_Ntk_t * pNtk )
   SeeAlso     []
 
 ***********************************************************************/
-Aig_Obj_t * Abc_ConvertSopToAigInternal( Aig_Man_t * pMan, char * pSop )
+Hop_Obj_t * Abc_ConvertSopToAigInternal( Hop_Man_t * pMan, char * pSop )
 {
-    Aig_Obj_t * pAnd, * pSum;
+    Hop_Obj_t * pAnd, * pSum;
     int i, Value, nFanins;
     char * pCube;
     // get the number of variables
     nFanins = Abc_SopGetVarNum(pSop);
     // go through the cubes of the node's SOP
-    pSum = Aig_ManConst0(pMan);
+    pSum = Hop_ManConst0(pMan);
     Abc_SopForEachCube( pSop, nFanins, pCube )
     {
         // create the AND of literals
-        pAnd = Aig_ManConst1(pMan);
+        pAnd = Hop_ManConst1(pMan);
         Abc_CubeForEachVar( pCube, Value, i )
         {
             if ( Value == '1' )
-                pAnd = Aig_And( pMan, pAnd, Aig_IthVar(pMan,i) );
+                pAnd = Hop_And( pMan, pAnd, Hop_IthVar(pMan,i) );
             else if ( Value == '0' )
-                pAnd = Aig_And( pMan, pAnd, Aig_Not(Aig_IthVar(pMan,i)) );
+                pAnd = Hop_And( pMan, pAnd, Hop_Not(Hop_IthVar(pMan,i)) );
         }
         // add to the sum of cubes
-        pSum = Aig_Or( pMan, pSum, pAnd );
+        pSum = Hop_Or( pMan, pSum, pAnd );
     }
     // decide whether to complement the result
     if ( Abc_SopIsComplement(pSop) )
-        pSum = Aig_Not(pSum);
+        pSum = Hop_Not(pSum);
     return pSum;
 }
 
@@ -612,16 +612,16 @@ Aig_Obj_t * Abc_ConvertSopToAigInternal( Aig_Man_t * pMan, char * pSop )
   SeeAlso     []
 
 ***********************************************************************/
-Aig_Obj_t * Abc_ConvertSopToAig( Aig_Man_t * pMan, char * pSop )
+Hop_Obj_t * Abc_ConvertSopToAig( Hop_Man_t * pMan, char * pSop )
 {
-    extern Aig_Obj_t * Dec_GraphFactorSop( Aig_Man_t * pMan, char * pSop );
+    extern Hop_Obj_t * Dec_GraphFactorSop( Hop_Man_t * pMan, char * pSop );
     int fUseFactor = 1;
     // consider the constant node
     if ( Abc_SopGetVarNum(pSop) == 0 )
-        return Aig_NotCond( Aig_ManConst1(pMan), Abc_SopIsConst0(pSop) );
+        return Hop_NotCond( Hop_ManConst1(pMan), Abc_SopIsConst0(pSop) );
     // consider the special case of EXOR function
     if ( Abc_SopIsExorType(pSop) )
-        return Aig_NotCond( Aig_CreateExor(pMan, Abc_SopGetVarNum(pSop)), Abc_SopIsComplement(pSop) );
+        return Hop_NotCond( Hop_CreateExor(pMan, Abc_SopGetVarNum(pSop)), Abc_SopIsComplement(pSop) );
     // decide when to use factoring
     if ( fUseFactor && Abc_SopGetVarNum(pSop) > 2 && Abc_SopGetCubeNum(pSop) > 1 )
         return Dec_GraphFactorSop( pMan, pSop );
@@ -642,7 +642,7 @@ Aig_Obj_t * Abc_ConvertSopToAig( Aig_Man_t * pMan, char * pSop )
 int Abc_NtkAigToBdd( Abc_Ntk_t * pNtk )
 {
     Abc_Obj_t * pNode;
-    Aig_Man_t * pMan;
+    Hop_Man_t * pMan;
     DdManager * dd;
     int nFaninsMax, i;
 
@@ -657,9 +657,9 @@ int Abc_NtkAigToBdd( Abc_Ntk_t * pNtk )
 
     // set the mapping of AIG nodes into the BDD nodes
     pMan = pNtk->pManFunc;
-    assert( Aig_ManPiNum(pMan) >= nFaninsMax ); 
+    assert( Hop_ManPiNum(pMan) >= nFaninsMax ); 
     for ( i = 0; i < nFaninsMax; i++ )
-        Aig_ManPi(pMan, i)->pData = Cudd_bddIthVar(dd, i);
+        Hop_ManPi(pMan, i)->pData = Cudd_bddIthVar(dd, i);
 
     // convert each node from SOP to BDD
     Abc_NtkForEachNode( pNtk, pNode, i )
@@ -674,7 +674,7 @@ int Abc_NtkAigToBdd( Abc_Ntk_t * pNtk )
         Cudd_Ref( pNode->pData );
     }
 
-    Aig_ManStop( pNtk->pManFunc );
+    Hop_ManStop( pNtk->pManFunc );
     pNtk->pManFunc = dd;
 
     // update the network type
@@ -693,17 +693,17 @@ int Abc_NtkAigToBdd( Abc_Ntk_t * pNtk )
   SeeAlso     []
 
 ***********************************************************************/
-void Abc_ConvertAigToBdd_rec1( DdManager * dd, Aig_Obj_t * pObj )
+void Abc_ConvertAigToBdd_rec1( DdManager * dd, Hop_Obj_t * pObj )
 {
-    assert( !Aig_IsComplement(pObj) );
-    if ( !Aig_ObjIsNode(pObj) || Aig_ObjIsMarkA(pObj) )
+    assert( !Hop_IsComplement(pObj) );
+    if ( !Hop_ObjIsNode(pObj) || Hop_ObjIsMarkA(pObj) )
         return;
-    Abc_ConvertAigToBdd_rec1( dd, Aig_ObjFanin0(pObj) ); 
-    Abc_ConvertAigToBdd_rec1( dd, Aig_ObjFanin1(pObj) );
-    pObj->pData = Cudd_bddAnd( dd, (DdNode *)Aig_ObjChild0Copy(pObj), (DdNode *)Aig_ObjChild1Copy(pObj) ); 
+    Abc_ConvertAigToBdd_rec1( dd, Hop_ObjFanin0(pObj) ); 
+    Abc_ConvertAigToBdd_rec1( dd, Hop_ObjFanin1(pObj) );
+    pObj->pData = Cudd_bddAnd( dd, (DdNode *)Hop_ObjChild0Copy(pObj), (DdNode *)Hop_ObjChild1Copy(pObj) ); 
     Cudd_Ref( pObj->pData );
-    assert( !Aig_ObjIsMarkA(pObj) ); // loop detection
-    Aig_ObjSetMarkA( pObj );
+    assert( !Hop_ObjIsMarkA(pObj) ); // loop detection
+    Hop_ObjSetMarkA( pObj );
 }
 
 /**Function*************************************************************
@@ -717,17 +717,17 @@ void Abc_ConvertAigToBdd_rec1( DdManager * dd, Aig_Obj_t * pObj )
   SeeAlso     []
 
 ***********************************************************************/
-void Abc_ConvertAigToBdd_rec2( DdManager * dd, Aig_Obj_t * pObj )
+void Abc_ConvertAigToBdd_rec2( DdManager * dd, Hop_Obj_t * pObj )
 {
-    assert( !Aig_IsComplement(pObj) );
-    if ( !Aig_ObjIsNode(pObj) || !Aig_ObjIsMarkA(pObj) )
+    assert( !Hop_IsComplement(pObj) );
+    if ( !Hop_ObjIsNode(pObj) || !Hop_ObjIsMarkA(pObj) )
         return;
-    Abc_ConvertAigToBdd_rec2( dd, Aig_ObjFanin0(pObj) ); 
-    Abc_ConvertAigToBdd_rec2( dd, Aig_ObjFanin1(pObj) );
+    Abc_ConvertAigToBdd_rec2( dd, Hop_ObjFanin0(pObj) ); 
+    Abc_ConvertAigToBdd_rec2( dd, Hop_ObjFanin1(pObj) );
     Cudd_RecursiveDeref( dd, pObj->pData );
     pObj->pData = NULL;
-    assert( Aig_ObjIsMarkA(pObj) ); // loop detection
-    Aig_ObjClearMarkA( pObj );
+    assert( Hop_ObjIsMarkA(pObj) ); // loop detection
+    Hop_ObjClearMarkA( pObj );
 }
 
 /**Function*************************************************************
@@ -741,18 +741,18 @@ void Abc_ConvertAigToBdd_rec2( DdManager * dd, Aig_Obj_t * pObj )
   SeeAlso     []
 
 ***********************************************************************/
-DdNode * Abc_ConvertAigToBdd( DdManager * dd, Aig_Obj_t * pRoot )
+DdNode * Abc_ConvertAigToBdd( DdManager * dd, Hop_Obj_t * pRoot )
 {
     DdNode * bFunc;
     // check the case of a constant
-    if ( Aig_ObjIsConst1( Aig_Regular(pRoot) ) )
-        return Cudd_NotCond( Cudd_ReadOne(dd), Aig_IsComplement(pRoot) );
+    if ( Hop_ObjIsConst1( Hop_Regular(pRoot) ) )
+        return Cudd_NotCond( Cudd_ReadOne(dd), Hop_IsComplement(pRoot) );
     // construct BDD
-    Abc_ConvertAigToBdd_rec1( dd, Aig_Regular(pRoot) );
+    Abc_ConvertAigToBdd_rec1( dd, Hop_Regular(pRoot) );
     // hold on to the result
-    bFunc = Cudd_NotCond( Aig_Regular(pRoot)->pData, Aig_IsComplement(pRoot) );  Cudd_Ref( bFunc );
+    bFunc = Cudd_NotCond( Hop_Regular(pRoot)->pData, Hop_IsComplement(pRoot) );  Cudd_Ref( bFunc );
     // dereference BDD
-    Abc_ConvertAigToBdd_rec2( dd, Aig_Regular(pRoot) );
+    Abc_ConvertAigToBdd_rec2( dd, Hop_Regular(pRoot) );
     // return the result
     Cudd_Deref( bFunc );
     return bFunc;
diff --git a/src/base/abc/abcLatch.c b/src/base/abc/abcLatch.c
index e475fd2a..cf3ddaba 100644
--- a/src/base/abc/abcLatch.c
+++ b/src/base/abc/abcLatch.c
@@ -117,11 +117,11 @@ int Abc_NtkRemoveSelfFeedLatches( Abc_Ntk_t * pNtk )
     {
         if ( Abc_NtkLatchIsSelfFeed( pLatch ) )
         {
-            if ( Abc_NtkIsStrash(pNtk) || Abc_NtkIsSeq(pNtk) )
+            if ( Abc_NtkIsStrash(pNtk) )
                 pConst1 = Abc_AigConst1(pNtk);
             else
                 pConst1 = Abc_NtkCreateNodeConst1(pNtk);
-            Abc_ObjPatchFanin( pLatch, Abc_ObjFanin0(Abc_ObjFanin0(pLatch)), pConst1 );
+            Abc_ObjPatchFanin( Abc_ObjFanin0(pLatch), Abc_ObjFanin0(Abc_ObjFanin0(pLatch)), pConst1 );
             Counter++;
         }
     }
diff --git a/src/base/abc/abcLib.c b/src/base/abc/abcLib.c
index 218df6ef..0036e687 100644
--- a/src/base/abc/abcLib.c
+++ b/src/base/abc/abcLib.c
@@ -47,7 +47,7 @@ Abc_Lib_t * Abc_LibCreate( char * pName )
     p->pName    = Extra_UtilStrsav( pName );
     p->tModules = st_init_table( strcmp, st_strhash );
     p->vModules = Vec_PtrAlloc( 100 );
-    p->pManFunc = Aig_ManStart();
+    p->pManFunc = Hop_ManStart();
     p->pLibrary = NULL;
     return p;
 }
@@ -70,7 +70,7 @@ void Abc_LibFree( Abc_Lib_t * pLib )
     if ( pLib->pName )
         free( pLib->pName );
     if ( pLib->pManFunc )
-        Aig_ManStop( pLib->pManFunc );
+        Hop_ManStop( pLib->pManFunc );
     if ( pLib->tModules )
         st_free_table( pLib->tModules );
     if ( pLib->vModules )
diff --git a/src/base/abc/abcNetlist.c b/src/base/abc/abcNetlist.c
index 5ea9b369..1ce10209 100644
--- a/src/base/abc/abcNetlist.c
+++ b/src/base/abc/abcNetlist.c
@@ -251,15 +251,6 @@ Abc_Ntk_t * Abc_NtkLogicToNetlist( Abc_Ntk_t * pNtk, int fDirect )
         pNtkNew = Abc_NtkLogicSopToNetlist( pNtkTemp );
         Abc_NtkDelete( pNtkTemp );
     }
-    else if ( Abc_NtkIsSeq(pNtk) )
-    {
-        assert( 0 );
-/*
-        pNtkTemp = Abc_NtkSeqToLogicSop(pNtk);
-        pNtkNew = Abc_NtkLogicSopToNetlist( pNtkTemp );
-        Abc_NtkDelete( pNtkTemp );
-*/
-    }
     else if ( Abc_NtkIsBddLogic(pNtk) )
     {
         if ( !Abc_NtkBddToSop(pNtk, fDirect) )
@@ -328,13 +319,22 @@ Abc_Ntk_t * Abc_NtkLogicSopToNetlist( Abc_Ntk_t * pNtk )
     Abc_NtkCleanup( pNtk, 0 );
 
     assert( Abc_NtkIsLogic(pNtk) );
-    assert( Abc_NtkLogicHasSimpleCos(pNtk) );
+//    assert( Abc_NtkLogicHasSimpleCos(pNtk) );
+    if ( !Abc_NtkLogicHasSimpleCos(pNtk) )
+    {
+        printf( "Abc_NtkLogicSopToNetlist() warning: The network is converted to have simple COs.\n" );
+        Abc_NtkLogicMakeSimpleCos( pNtk, 0 );
+    }
+
     if ( Abc_NtkIsBddLogic(pNtk) )
     {
         if ( !Abc_NtkBddToSop(pNtk,0) )
             return NULL;
     }
 
+//    Abc_NtkForEachCo(pNtk, pObj, i)
+//        Abc_ObjPrint( stdout, Abc_ObjFanin0(pObj) );
+
     // start the netlist by creating PI/PO/Latch objects
     pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_NETLIST, pNtk->ntkFunc );
     // create the CI nets and remember them in the new CI nodes
@@ -358,7 +358,7 @@ Abc_Ntk_t * Abc_NtkLogicSopToNetlist( Abc_Ntk_t * pNtk )
             continue;
         }
         assert( Abc_ObjIsNode(pDriver) );
-        // if the CO drive has no net, create it
+        // if the CO driver has no net, create it
         if ( pDriver->pCopy->pCopy == NULL )
         {
             // create the CO net and connect it to CO
diff --git a/src/base/abc/abcNtk.c b/src/base/abc/abcNtk.c
index a3ce5145..f0642ffa 100644
--- a/src/base/abc/abcNtk.c
+++ b/src/base/abc/abcNtk.c
@@ -58,9 +58,7 @@ Abc_Ntk_t * Abc_NtkAlloc( Abc_NtkType_t Type, Abc_NtkFunc_t Func, int fUseMemMan
     pNtk->vPos        = Vec_PtrAlloc( 100 );
     pNtk->vCis        = Vec_PtrAlloc( 100 );
     pNtk->vCos        = Vec_PtrAlloc( 100 );
-    pNtk->vCutSet     = Vec_PtrAlloc( 100 );
     pNtk->vBoxes      = Vec_PtrAlloc( 100 );
-    pNtk->vSkews      = Vec_FltAlloc( 100 );
     // start the memory managers
     pNtk->pMmObj      = fUseMemMan? Extra_MmFixedStart( sizeof(Abc_Obj_t) ) : NULL;
     pNtk->pMmStep     = fUseMemMan? Extra_MmStepStart( ABC_NUM_STEPS ) : NULL;
@@ -76,13 +74,15 @@ Abc_Ntk_t * Abc_NtkAlloc( Abc_NtkType_t Type, Abc_NtkFunc_t Func, int fUseMemMan
     else if ( Abc_NtkHasBdd(pNtk) )
         pNtk->pManFunc = Cudd_Init( 20, 0, CUDD_UNIQUE_SLOTS, CUDD_CACHE_SLOTS, 0 );
     else if ( Abc_NtkHasAig(pNtk) )
-        pNtk->pManFunc = Aig_ManStart();
+        pNtk->pManFunc = Hop_ManStart();
     else if ( Abc_NtkHasMapping(pNtk) )
         pNtk->pManFunc = Abc_FrameReadLibGen();
     else if ( !Abc_NtkHasBlackbox(pNtk) )
         assert( 0 );
     // name manager
     pNtk->pManName = Nm_ManCreate( 200 );
+    // attribute manager
+    pNtk->vAttrs = Vec_PtrStart( VEC_ATTR_TOTAL_NUM );
     return pNtk;
 }
 
@@ -301,40 +301,6 @@ Abc_Ntk_t * Abc_NtkDup( Abc_Ntk_t * pNtk )
             printf( "Warning: Structural hashing during duplication reduced %d nodes (this is a minor bug).\n",
                 Abc_NtkNodeNum(pNtk) - Abc_NtkNodeNum(pNtkNew) );
     }
-/*
-    else if ( Abc_NtkIsSeq(pNtk) )
-    {
-        // start the storage for initial states
-        Seq_Resize( pNtkNew->pManFunc, Abc_NtkObjNumMax(pNtk) );
-        // copy the nodes
-        Abc_NtkForEachObj( pNtk, pObj, i )
-            if ( pObj->pCopy == NULL )
-            {
-                Abc_NtkDupObj(pNtkNew, pObj, 0);
-                pObj->pCopy->Level = pObj->Level;
-                pObj->pCopy->fPhase = pObj->fPhase;
-            }
-        // connect the nodes
-        Abc_NtkForEachObj( pNtk, pObj, i )
-        {
-            Abc_ObjForEachFanin( pObj, pFanin, k )
-            {
-                Abc_ObjAddFanin( pObj->pCopy, pFanin->pCopy );
-                if ( Abc_ObjFaninC(pObj, k) )
-                    Abc_ObjSetFaninC( pObj->pCopy, k );
-                if ( Seq_ObjFaninL(pObj, k) )
-                    Seq_NodeDupLats( pObj->pCopy, pObj, k );
-            }
-        }
-        // relink the choice nodes
-        Abc_AigForEachAnd( pNtk, pObj, i )
-            if ( pObj->pData )
-                pObj->pCopy->pData = ((Abc_Obj_t *)pObj->pData)->pCopy;
-        // copy the cutset
-        Abc_SeqForEachCutsetNode( pNtk, pObj, i )
-            Vec_PtrPush( pNtkNew->vCutSet, pObj->pCopy );
-    }
-*/
     else
     {
         // duplicate the nets and nodes (CIs/COs/latches already dupped)
@@ -795,6 +761,7 @@ Abc_Ntk_t * Abc_NtkCreateWithNode( char * pSop )
 void Abc_NtkDelete( Abc_Ntk_t * pNtk )
 {
     Abc_Obj_t * pObj;
+    void * pAttrMan;
     int TotalMemory, i;
     int LargePiece = (4 << ABC_NUM_STEPS);
     if ( pNtk == NULL )
@@ -845,9 +812,7 @@ void Abc_NtkDelete( Abc_Ntk_t * pNtk )
     Vec_PtrFree( pNtk->vCos );
     Vec_PtrFree( pNtk->vAsserts );
     Vec_PtrFree( pNtk->vObjs );
-    Vec_PtrFree( pNtk->vCutSet );
     Vec_PtrFree( pNtk->vBoxes );
-    Vec_FltFree( pNtk->vSkews );
     if ( pNtk->vLevelsR ) Vec_IntFree( pNtk->vLevelsR );
     if ( pNtk->pModel ) free( pNtk->pModel );
     TotalMemory  = 0;
@@ -874,7 +839,7 @@ void Abc_NtkDelete( Abc_Ntk_t * pNtk )
     else if ( Abc_NtkHasBdd(pNtk) )
         Extra_StopManager( pNtk->pManFunc );
     else if ( Abc_NtkHasAig(pNtk) )
-        { if ( pNtk->pManFunc ) Aig_ManStop( pNtk->pManFunc ); }
+        { if ( pNtk->pManFunc ) Hop_ManStop( pNtk->pManFunc ); }
     else if ( Abc_NtkHasMapping(pNtk) )
         pNtk->pManFunc = NULL;
     else if ( !Abc_NtkHasBlackbox(pNtk) )
@@ -891,6 +856,11 @@ void Abc_NtkDelete( Abc_Ntk_t * pNtk )
     }
     if ( pNtk->pBlackBoxes ) 
         Vec_IntFree( pNtk->pBlackBoxes );
+    // free node attributes
+    Vec_PtrForEachEntry( pNtk->vAttrs, pAttrMan, i )
+        if ( pAttrMan )
+            Vec_AttFree( pAttrMan, 1 );
+    Vec_PtrFree( pNtk->vAttrs );
     free( pNtk );
 }
 
diff --git a/src/base/abc/abcObj.c b/src/base/abc/abcObj.c
index dc3ff73c..d0e1dc37 100644
--- a/src/base/abc/abcObj.c
+++ b/src/base/abc/abcObj.c
@@ -299,7 +299,7 @@ void Abc_NtkDeleteAll_rec( Abc_Obj_t * pObj )
     Abc_NodeCollectFanins( pObj, vNodes );
     Abc_NtkDeleteObj( pObj );
     Vec_PtrForEachEntry( vNodes, pObj, i )
-        if ( Abc_ObjFanoutNum(pObj) == 0 )
+        if ( !Abc_ObjIsNode(pObj) && Abc_ObjFanoutNum(pObj) == 0 )
             Abc_NtkDeleteAll_rec( pObj );
     Vec_PtrFree( vNodes );
 }
@@ -342,7 +342,7 @@ Abc_Obj_t * Abc_NtkDupObj( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pObj, int fCopyName
             else if ( Abc_NtkHasBdd(pNtkNew) )
                 pObjNew->pData = Cudd_bddTransfer(pObj->pNtk->pManFunc, pNtkNew->pManFunc, pObj->pData), Cudd_Ref(pObjNew->pData);
             else if ( Abc_NtkHasAig(pNtkNew) )
-                pObjNew->pData = Aig_Transfer(pObj->pNtk->pManFunc, pNtkNew->pManFunc, pObj->pData, Abc_ObjFaninNum(pObj));
+                pObjNew->pData = Hop_Transfer(pObj->pNtk->pManFunc, pNtkNew->pManFunc, pObj->pData, Abc_ObjFaninNum(pObj));
             else if ( Abc_NtkHasMapping(pNtkNew) )
                 pObjNew->pData = pObj->pData;
             else assert( 0 );
@@ -576,7 +576,7 @@ Abc_Obj_t * Abc_NtkCreateNodeConst0( Abc_Ntk_t * pNtk )
     else if ( Abc_NtkHasBdd(pNtk) )
         pNode->pData = Cudd_ReadLogicZero(pNtk->pManFunc), Cudd_Ref( pNode->pData );
     else if ( Abc_NtkHasAig(pNtk) )
-        pNode->pData = Aig_ManConst0(pNtk->pManFunc);
+        pNode->pData = Hop_ManConst0(pNtk->pManFunc);
     else if ( Abc_NtkHasMapping(pNtk) )
         pNode->pData = Mio_LibraryReadConst0(Abc_FrameReadLibGen());
     else if ( !Abc_NtkHasBlackbox(pNtk) )
@@ -605,7 +605,7 @@ Abc_Obj_t * Abc_NtkCreateNodeConst1( Abc_Ntk_t * pNtk )
     else if ( Abc_NtkHasBdd(pNtk) )
         pNode->pData = Cudd_ReadOne(pNtk->pManFunc), Cudd_Ref( pNode->pData );
     else if ( Abc_NtkHasAig(pNtk) )
-        pNode->pData = Aig_ManConst1(pNtk->pManFunc);
+        pNode->pData = Hop_ManConst1(pNtk->pManFunc);
     else if ( Abc_NtkHasMapping(pNtk) )
         pNode->pData = Mio_LibraryReadConst1(Abc_FrameReadLibGen());
     else if ( !Abc_NtkHasBlackbox(pNtk) )
@@ -635,7 +635,7 @@ Abc_Obj_t * Abc_NtkCreateNodeInv( Abc_Ntk_t * pNtk, Abc_Obj_t * pFanin )
     else if ( Abc_NtkHasBdd(pNtk) )
         pNode->pData = Cudd_Not(Cudd_bddIthVar(pNtk->pManFunc,0)), Cudd_Ref( pNode->pData );
     else if ( Abc_NtkHasAig(pNtk) )
-        pNode->pData = Aig_Not(Aig_IthVar(pNtk->pManFunc,0));
+        pNode->pData = Hop_Not(Hop_IthVar(pNtk->pManFunc,0));
     else if ( Abc_NtkHasMapping(pNtk) )
         pNode->pData = Mio_LibraryReadInv(Abc_FrameReadLibGen());
     else
@@ -665,7 +665,7 @@ Abc_Obj_t * Abc_NtkCreateNodeBuf( Abc_Ntk_t * pNtk, Abc_Obj_t * pFanin )
     else if ( Abc_NtkHasBdd(pNtk) )
         pNode->pData = Cudd_bddIthVar(pNtk->pManFunc,0), Cudd_Ref( pNode->pData );
     else if ( Abc_NtkHasAig(pNtk) )
-        pNode->pData = Aig_IthVar(pNtk->pManFunc,0);
+        pNode->pData = Hop_IthVar(pNtk->pManFunc,0);
     else if ( Abc_NtkHasMapping(pNtk) )
         pNode->pData = Mio_LibraryReadBuf(Abc_FrameReadLibGen());
     else
@@ -697,7 +697,7 @@ Abc_Obj_t * Abc_NtkCreateNodeAnd( Abc_Ntk_t * pNtk, Vec_Ptr_t * vFanins )
     else if ( Abc_NtkHasBdd(pNtk) )
         pNode->pData = Extra_bddCreateAnd( pNtk->pManFunc, Vec_PtrSize(vFanins) ), Cudd_Ref(pNode->pData); 
     else if ( Abc_NtkHasAig(pNtk) )
-        pNode->pData = Aig_CreateAnd( pNtk->pManFunc, Vec_PtrSize(vFanins) ); 
+        pNode->pData = Hop_CreateAnd( pNtk->pManFunc, Vec_PtrSize(vFanins) ); 
     else
         assert( 0 );
     return pNode;
@@ -727,7 +727,7 @@ Abc_Obj_t * Abc_NtkCreateNodeOr( Abc_Ntk_t * pNtk, Vec_Ptr_t * vFanins )
     else if ( Abc_NtkHasBdd(pNtk) )
         pNode->pData = Extra_bddCreateOr( pNtk->pManFunc, Vec_PtrSize(vFanins) ), Cudd_Ref(pNode->pData); 
     else if ( Abc_NtkHasAig(pNtk) )
-        pNode->pData = Aig_CreateOr( pNtk->pManFunc, Vec_PtrSize(vFanins) ); 
+        pNode->pData = Hop_CreateOr( pNtk->pManFunc, Vec_PtrSize(vFanins) ); 
     else
         assert( 0 );
     return pNode;
@@ -757,7 +757,7 @@ Abc_Obj_t * Abc_NtkCreateNodeExor( Abc_Ntk_t * pNtk, Vec_Ptr_t * vFanins )
     else if ( Abc_NtkHasBdd(pNtk) )
         pNode->pData = Extra_bddCreateExor( pNtk->pManFunc, Vec_PtrSize(vFanins) ), Cudd_Ref(pNode->pData); 
     else if ( Abc_NtkHasAig(pNtk) )
-        pNode->pData = Aig_CreateExor( pNtk->pManFunc, Vec_PtrSize(vFanins) ); 
+        pNode->pData = Hop_CreateExor( pNtk->pManFunc, Vec_PtrSize(vFanins) ); 
     else
         assert( 0 );
     return pNode;
@@ -787,7 +787,7 @@ Abc_Obj_t * Abc_NtkCreateNodeMux( Abc_Ntk_t * pNtk, Abc_Obj_t * pNodeC, Abc_Obj_
     else if ( Abc_NtkHasBdd(pNtk) )
         pNode->pData = Cudd_bddIte(pNtk->pManFunc,Cudd_bddIthVar(pNtk->pManFunc,0),Cudd_bddIthVar(pNtk->pManFunc,1),Cudd_bddIthVar(pNtk->pManFunc,2)), Cudd_Ref( pNode->pData );
     else if ( Abc_NtkHasAig(pNtk) )
-        pNode->pData = Aig_Mux(pNtk->pManFunc,Aig_IthVar(pNtk->pManFunc,0),Aig_IthVar(pNtk->pManFunc,1),Aig_IthVar(pNtk->pManFunc,2));
+        pNode->pData = Hop_Mux(pNtk->pManFunc,Hop_IthVar(pNtk->pManFunc,0),Hop_IthVar(pNtk->pManFunc,1),Hop_IthVar(pNtk->pManFunc,2));
     else
         assert( 0 );
     return pNode;
@@ -834,7 +834,7 @@ bool Abc_NodeIsConst0( Abc_Obj_t * pNode )
     if ( Abc_NtkHasBdd(pNtk) )
         return Cudd_IsComplement(pNode->pData);
     if ( Abc_NtkHasAig(pNtk) )
-        return Aig_IsComplement(pNode->pData);
+        return Hop_IsComplement(pNode->pData);
     if ( Abc_NtkHasMapping(pNtk) )
         return pNode->pData == Mio_LibraryReadConst0(Abc_FrameReadLibGen());
     assert( 0 );
@@ -864,7 +864,7 @@ bool Abc_NodeIsConst1( Abc_Obj_t * pNode )
     if ( Abc_NtkHasBdd(pNtk) )
         return !Cudd_IsComplement(pNode->pData);
     if ( Abc_NtkHasAig(pNtk) )
-        return !Aig_IsComplement(pNode->pData);
+        return !Hop_IsComplement(pNode->pData);
     if ( Abc_NtkHasMapping(pNtk) )
         return pNode->pData == Mio_LibraryReadConst1(Abc_FrameReadLibGen());
     assert( 0 );
@@ -894,7 +894,7 @@ bool Abc_NodeIsBuf( Abc_Obj_t * pNode )
     if ( Abc_NtkHasBdd(pNtk) )
         return !Cudd_IsComplement(pNode->pData);
     if ( Abc_NtkHasAig(pNtk) )
-        return !Aig_IsComplement(pNode->pData);
+        return !Hop_IsComplement(pNode->pData);
     if ( Abc_NtkHasMapping(pNtk) )
         return pNode->pData == Mio_LibraryReadBuf(Abc_FrameReadLibGen());
     assert( 0 );
@@ -924,7 +924,7 @@ bool Abc_NodeIsInv( Abc_Obj_t * pNode )
     if ( Abc_NtkHasBdd(pNtk) )
         return Cudd_IsComplement(pNode->pData);
     if ( Abc_NtkHasAig(pNtk) )
-        return Aig_IsComplement(pNode->pData);
+        return Hop_IsComplement(pNode->pData);
     if ( Abc_NtkHasMapping(pNtk) )
         return pNode->pData == Mio_LibraryReadInv(Abc_FrameReadLibGen());
     assert( 0 );
@@ -951,7 +951,7 @@ void Abc_NodeComplement( Abc_Obj_t * pNode )
     else if ( Abc_NtkHasBdd(pNode->pNtk) )
         pNode->pData = Cudd_Not( pNode->pData );
     else if ( Abc_NtkHasAig(pNode->pNtk) )
-        pNode->pData = Aig_Not( pNode->pData );
+        pNode->pData = Hop_Not( pNode->pData );
     else
         assert( 0 );
 }
diff --git a/src/base/abc/abcShow.c b/src/base/abc/abcShow.c
index fa921391..ee86e8aa 100644
--- a/src/base/abc/abcShow.c
+++ b/src/base/abc/abcShow.c
@@ -79,109 +79,6 @@ void Abc_NodeShowBdd( Abc_Obj_t * pNode )
 
 /**Function*************************************************************
 
-  Synopsis    [Visualizes AIG with choices.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Abc_NtkShowAig( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodesShow )
-{
-    FILE * pFile;
-    Abc_Obj_t * pNode;
-    Vec_Ptr_t * vNodes;
-    char FileNameDot[200];
-    int i;
-
-    assert( Abc_NtkIsStrash(pNtk) );
-    // create the file name
-    Abc_ShowGetFileName( pNtk->pName, FileNameDot );
-    // check that the file can be opened
-    if ( (pFile = fopen( FileNameDot, "w" )) == NULL )
-    {
-        fprintf( stdout, "Cannot open the intermediate file \"%s\".\n", FileNameDot );
-        return;
-    }
-    fclose( pFile );
-
-    // collect all nodes in the network
-    vNodes = Vec_PtrAlloc( 100 );
-    Abc_NtkForEachObj( pNtk, pNode, i )
-        Vec_PtrPush( vNodes, pNode );
-    // write the DOT file
-    Io_WriteDotAig( pNtk, vNodes, vNodesShow, FileNameDot, 0 );
-    Vec_PtrFree( vNodes );
-
-    // visualize the file 
-    Abc_ShowFile( FileNameDot );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Visualizes AIG with choices.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Abc_NtkShowMulti( Abc_Ntk_t * pNtk )
-{
-    FILE * pFile;
-    Abc_Obj_t * pNode;
-    Vec_Ptr_t * vNodes;
-    char FileNameDot[200];
-    int i;
-    extern void Abc_NtkBalanceAttach( Abc_Ntk_t * pNtk );
-    extern void Abc_NtkBalanceDetach( Abc_Ntk_t * pNtk );
-    extern void Abc_NtkBalanceLevel( Abc_Ntk_t * pNtk );
-
-    assert( Abc_NtkIsStrash(pNtk) );
-    // create the file name
-    Abc_ShowGetFileName( pNtk->pName, FileNameDot );
-    // check that the file can be opened
-    if ( (pFile = fopen( FileNameDot, "w" )) == NULL )
-    {
-        fprintf( stdout, "Cannot open the intermediate file \"%s\".\n", FileNameDot );
-        return;
-    }
-    fclose( pFile );
-
-    // get the implication supergates
-    Abc_NtkBalanceAttach( pNtk );
-    // set the levels based on the implication supergates
-    Abc_NtkBalanceLevel( pNtk );
-
-    // collect all nodes that are roots
-    vNodes = Vec_PtrAlloc( 100 );
-    Abc_NtkForEachCi( pNtk, pNode, i )
-        Vec_PtrPush( vNodes, pNode );
-    Abc_NtkForEachNode( pNtk, pNode, i )
-        if ( pNode->pCopy || Abc_ObjFaninNum(pNode) == 0 )
-            Vec_PtrPush( vNodes, pNode );
-    Abc_NtkForEachPo( pNtk, pNode, i )
-        Vec_PtrPush( vNodes, pNode );
-
-    // write the DOT file
-    Io_WriteDotAig( pNtk, vNodes, NULL, FileNameDot, 1 );
-    Vec_PtrFree( vNodes );
-
-    // undo the supergates
-    Abc_NtkBalanceDetach( pNtk );
-    // set the normal levels
-    Abc_NtkGetLevelNum( pNtk );
-
-    // visualize the file 
-    Abc_ShowFile( FileNameDot );
-}
-
-/**Function*************************************************************
-
   Synopsis    [Visualizes a reconvergence driven cut at the node.]
 
   Description []
@@ -232,7 +129,7 @@ void Abc_NodeShowCut( Abc_Obj_t * pNode, int nNodeSizeMax, int nConeSizeMax )
     // add the root node to the cone (for visualization)
     Vec_PtrPush( vCutSmall, pNode );
     // write the DOT file
-    Io_WriteDotAig( pNode->pNtk, vInside, vCutSmall, FileNameDot, 0 );
+    Io_WriteDotNtk( pNode->pNtk, vInside, vCutSmall, FileNameDot, 0, 0 );
     // stop the cut computation manager
     Abc_NtkManCutStop( p );
 
@@ -251,7 +148,7 @@ void Abc_NodeShowCut( Abc_Obj_t * pNode, int nNodeSizeMax, int nConeSizeMax )
   SeeAlso     []
 
 ***********************************************************************/
-void Abc_NtkShow( Abc_Ntk_t * pNtk, int fGateNames )
+void Abc_NtkShow( Abc_Ntk_t * pNtk, int fGateNames, int fSeq, int fUseReverse )
 {
     FILE * pFile;
     Abc_Obj_t * pNode;
@@ -259,8 +156,15 @@ void Abc_NtkShow( Abc_Ntk_t * pNtk, int fGateNames )
     char FileNameDot[200];
     int i;
 
-    assert( !Abc_NtkIsStrash(pNtk) );
-    Abc_NtkLogicToSop( pNtk, 0 );
+    assert( Abc_NtkIsStrash(pNtk) || Abc_NtkIsLogic(pNtk) );
+    if ( Abc_NtkIsStrash(pNtk) && Abc_NtkGetChoiceNum(pNtk) )
+    {
+        printf( "Temporarily visualization of AIGs with choice nodes is disabled.\n" );
+        return;
+    }
+    // convert to logic SOP
+    if ( Abc_NtkIsLogic(pNtk) )
+        Abc_NtkLogicToSop( pNtk, 0 );
     // create the file name
     Abc_ShowGetFileName( pNtk->pName, FileNameDot );
     // check that the file can be opened
@@ -274,10 +178,12 @@ void Abc_NtkShow( Abc_Ntk_t * pNtk, int fGateNames )
     // collect all nodes in the network
     vNodes = Vec_PtrAlloc( 100 );
     Abc_NtkForEachObj( pNtk, pNode, i )
-//        if ( !Abc_ObjIsBi(pNode) && !Abc_ObjIsBo(pNode) )
-            Vec_PtrPush( vNodes, pNode );
+        Vec_PtrPush( vNodes, pNode );
     // write the DOT file
-    Io_WriteDotNtk( pNtk, vNodes, NULL, FileNameDot, fGateNames );
+    if ( fSeq )
+        Io_WriteDotSeq( pNtk, vNodes, NULL, FileNameDot, fGateNames, fUseReverse );
+    else
+        Io_WriteDotNtk( pNtk, vNodes, NULL, FileNameDot, fGateNames, fUseReverse );
     Vec_PtrFree( vNodes );
 
     // visualize the file 
diff --git a/src/base/abc/abcSop.c b/src/base/abc/abcSop.c
index db0803c1..81d91499 100644
--- a/src/base/abc/abcSop.c
+++ b/src/base/abc/abcSop.c
@@ -768,7 +768,8 @@ bool Abc_SopCheck( char * pSop, int nFanins )
         // compare the distance
         if ( pCubes - pCubesOld != nFanins )
         {
-            fprintf( stdout, "Abc_SopCheck: SOP has a mismatch between its cover and its fanins.\n" );
+            fprintf( stdout, "Abc_SopCheck: SOP has a mismatch between its cover size (%d) and its fanin number (%d).\n",
+                pCubes - pCubesOld, nFanins );
             return 0;
         }
         // check the output values for this cube
@@ -779,7 +780,7 @@ bool Abc_SopCheck( char * pSop, int nFanins )
             fFound1 = 1;
         else if ( *pCubes != 'x' && *pCubes != 'n' )
         {
-            fprintf( stdout, "Abc_SopCheck: SOP has a strange character in the output part of its cube.\n" );
+            fprintf( stdout, "Abc_SopCheck: SOP has a strange character (%c) in the output part of its cube.\n", *pCubes );
             return 0;
         }
         // check the last symbol (new line)
diff --git a/src/base/abc/abcUtil.c b/src/base/abc/abcUtil.c
index fa1cd69a..12bb8341 100644
--- a/src/base/abc/abcUtil.c
+++ b/src/base/abc/abcUtil.c
@@ -34,6 +34,27 @@
 
 /**Function*************************************************************
 
+  Synopsis    [Frees one attribute manager.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void * Abc_NtkAttrFree( Abc_Ntk_t * pNtk, int Attr, int fFreeMan ) 
+{  
+    void * pUserMan;
+    Vec_Att_t * pAttrMan;
+    pAttrMan = Vec_PtrEntry( pNtk->vAttrs, Attr );
+    Vec_PtrWriteEntry( pNtk->vAttrs, Attr, NULL );
+    pUserMan = Vec_AttFree( pAttrMan, fFreeMan );
+    return pUserMan;
+}
+
+/**Function*************************************************************
+
   Synopsis    [Increments the current traversal ID of the network.]
 
   Description []
@@ -225,7 +246,7 @@ int Abc_NtkGetAigNodeNum( Abc_Ntk_t * pNtk )
         assert( pNode->pData );
         if ( Abc_NodeIsConst(pNode) )
             continue;
-        nNodes += pNode->pData? Aig_DagSize( pNode->pData ) : 0;
+        nNodes += pNode->pData? Hop_DagSize( pNode->pData ) : 0;
     }
     return nNodes;
 }
@@ -356,7 +377,7 @@ int Abc_NtkGetChoiceNum( Abc_Ntk_t * pNtk )
 {
     Abc_Obj_t * pNode;
     int i, Counter;
-    if ( !Abc_NtkHasAig(pNtk) )
+    if ( !Abc_NtkIsStrash(pNtk) )
         return 0;
     Counter = 0;
     Abc_NtkForEachNode( pNtk, pNode, i )
@@ -578,7 +599,7 @@ void Abc_NtkFixCoDriverProblem( Abc_Obj_t * pDriver, Abc_Obj_t * pNodeCo, int fD
   Description [The COs of a logic network are simple under three conditions:
   (1) The edge from CO to its driver is not complemented.
   (2) If CI is a driver of a CO, they have the same name.]
-  (2) If two COs share the same driver, they have the same name.]
+  (3) If two COs share the same driver, they have the same name.]
                
   SideEffects []
 
@@ -621,7 +642,7 @@ bool Abc_NtkLogicHasSimpleCos( Abc_Ntk_t * pNtk )
   Description [The COs of a logic network are simple under three conditions:
   (1) The edge from CO to its driver is not complemented.
   (2) If CI is a driver of a CO, they have the same name.]
-  (2) If two COs share the same driver, they have the same name.
+  (3) If two COs share the same driver, they have the same name.
   In some cases, such as FPGA mapping, we prevent the increase in delay
   by duplicating the driver nodes, rather than adding invs/bufs.]
                
diff --git a/src/base/abci/abc.c b/src/base/abci/abc.c
index dffe4b99..9613ab40 100644
--- a/src/base/abci/abc.c
+++ b/src/base/abci/abc.c
@@ -22,10 +22,9 @@
 #include "mainInt.h"
 #include "fraig.h"
 #include "fxu.h"
-#include "fpga.h"
-#include "pga.h"
 #include "cut.h"
-//#include "seq.h"
+#include "fpga.h"
+#include "if.h"
 
 ////////////////////////////////////////////////////////////////////////
 ///                        DECLARATIONS                              ///
@@ -46,12 +45,10 @@ static int Abc_CommandPrintAuto      ( Abc_Frame_t * pAbc, int argc, char ** arg
 static int Abc_CommandPrintKMap      ( Abc_Frame_t * pAbc, int argc, char ** argv );
 static int Abc_CommandPrintGates     ( Abc_Frame_t * pAbc, int argc, char ** argv );
 static int Abc_CommandPrintSharing   ( Abc_Frame_t * pAbc, int argc, char ** argv );
-static int Abc_CommandPrintSkews     ( Abc_Frame_t * pAbc, int argc, char ** argv );
 
+static int Abc_CommandShow           ( Abc_Frame_t * pAbc, int argc, char ** argv );
 static int Abc_CommandShowBdd        ( Abc_Frame_t * pAbc, int argc, char ** argv );
 static int Abc_CommandShowCut        ( Abc_Frame_t * pAbc, int argc, char ** argv );
-static int Abc_CommandShowAig        ( Abc_Frame_t * pAbc, int argc, char ** argv );
-static int Abc_CommandShowNtk        ( Abc_Frame_t * pAbc, int argc, char ** argv );
 
 static int Abc_CommandCollapse       ( Abc_Frame_t * pAbc, int argc, char ** argv );
 static int Abc_CommandStrash         ( Abc_Frame_t * pAbc, int argc, char ** argv );
@@ -123,7 +120,7 @@ static int Abc_CommandSuperChoiceLut ( Abc_Frame_t * pAbc, int argc, char ** arg
 
 static int Abc_CommandFpga           ( Abc_Frame_t * pAbc, int argc, char ** argv );
 static int Abc_CommandFpgaFast       ( Abc_Frame_t * pAbc, int argc, char ** argv );
-static int Abc_CommandPga            ( Abc_Frame_t * pAbc, int argc, char ** argv );
+static int Abc_CommandIf             ( Abc_Frame_t * pAbc, int argc, char ** argv );
 
 static int Abc_CommandScut           ( Abc_Frame_t * pAbc, int argc, char ** argv );
 static int Abc_CommandInit           ( Abc_Frame_t * pAbc, int argc, char ** argv );
@@ -145,9 +142,6 @@ static int Abc_CommandDebug          ( Abc_Frame_t * pAbc, int argc, char ** arg
 static int Abc_CommandTraceStart     ( Abc_Frame_t * pAbc, int argc, char ** argv );
 static int Abc_CommandTraceCheck     ( Abc_Frame_t * pAbc, int argc, char ** argv );
 
-static int Abc_CommandHoward       ( Abc_Frame_t * pAbc, int argc, char ** argv );
-static int Abc_CommandSkewForward  ( Abc_Frame_t * pAbc, int argc, char ** argv );
-
 ////////////////////////////////////////////////////////////////////////
 ///                     FUNCTION DEFINITIONS                         ///
 ////////////////////////////////////////////////////////////////////////
@@ -182,12 +176,10 @@ void Abc_Init( Abc_Frame_t * pAbc )
     Cmd_CommandAdd( pAbc, "Printing",     "print_kmap",    Abc_CommandPrintKMap,        0 );
     Cmd_CommandAdd( pAbc, "Printing",     "print_gates",   Abc_CommandPrintGates,       0 );
     Cmd_CommandAdd( pAbc, "Printing",     "print_sharing", Abc_CommandPrintSharing,     0 );
-    Cmd_CommandAdd( pAbc, "Printing",     "print_skews",   Abc_CommandPrintSkews,       0 );
 
+    Cmd_CommandAdd( pAbc, "Printing",     "show",          Abc_CommandShow,             0 );
     Cmd_CommandAdd( pAbc, "Printing",     "show_bdd",      Abc_CommandShowBdd,          0 );
     Cmd_CommandAdd( pAbc, "Printing",     "show_cut",      Abc_CommandShowCut,          0 );
-    Cmd_CommandAdd( pAbc, "Printing",     "show_aig",      Abc_CommandShowAig,          0 );
-    Cmd_CommandAdd( pAbc, "Printing",     "show_ntk",      Abc_CommandShowNtk,          0 );
 
     Cmd_CommandAdd( pAbc, "Synthesis",    "collapse",      Abc_CommandCollapse,         1 );
     Cmd_CommandAdd( pAbc, "Synthesis",    "strash",        Abc_CommandStrash,           1 );
@@ -259,7 +251,7 @@ void Abc_Init( Abc_Frame_t * pAbc )
 
     Cmd_CommandAdd( pAbc, "FPGA mapping", "fpga",          Abc_CommandFpga,             1 );
     Cmd_CommandAdd( pAbc, "FPGA mapping", "ffpga",         Abc_CommandFpgaFast,         1 );
-    Cmd_CommandAdd( pAbc, "FPGA mapping", "pga",           Abc_CommandPga,              1 );
+    Cmd_CommandAdd( pAbc, "FPGA mapping", "if",            Abc_CommandIf,               1 );
 
 //    Cmd_CommandAdd( pAbc, "Sequential",   "scut",          Abc_CommandScut,             0 );
     Cmd_CommandAdd( pAbc, "Sequential",   "init",          Abc_CommandInit,             1 );
@@ -281,9 +273,6 @@ void Abc_Init( Abc_Frame_t * pAbc )
 //    Cmd_CommandAdd( pAbc, "Verification", "trace_start",   Abc_CommandTraceStart,       0 );
 //    Cmd_CommandAdd( pAbc, "Verification", "trace_check",   Abc_CommandTraceCheck,       0 );
 
-//    Cmd_CommandAdd( pAbc, "Sequential",   "howard",        Abc_CommandHoward,           0 );
-//    Cmd_CommandAdd( pAbc, "Sequential",   "skew_fwd",      Abc_CommandSkewForward,      0 );
-
 //    Rwt_Man4ExploreStart();
 //    Map_Var3Print();
 //    Map_Var4Test();
@@ -1383,29 +1372,38 @@ usage:
   SeeAlso     []
 
 ***********************************************************************/
-int Abc_CommandPrintSkews( Abc_Frame_t * pAbc, int argc, char ** argv )
+int Abc_CommandShow( Abc_Frame_t * pAbc, int argc, char ** argv )
 {
     FILE * pOut, * pErr;
     Abc_Ntk_t * pNtk;
     int c;
-    int fPrintAll;
+    int fSeq;
+    int fGateNames;
+    int fUseReverse;
+    extern void Abc_NtkShow( Abc_Ntk_t * pNtk, int fGateNames, int fSeq, int fUseReverse );
 
     pNtk = Abc_FrameReadNtk(pAbc);
     pOut = Abc_FrameReadOut(pAbc);
     pErr = Abc_FrameReadErr(pAbc);
 
     // set defaults
-    fPrintAll = 0;
+    fSeq        = 0;
+    fGateNames  = 0;
+    fUseReverse = 1;
     Extra_UtilGetoptReset();
-    while ( ( c = Extra_UtilGetopt( argc, argv, "ah" ) ) != EOF )
+    while ( ( c = Extra_UtilGetopt( argc, argv, "rsgh" ) ) != EOF )
     {
         switch ( c )
         {
-        case 'a':
-            fPrintAll = 1;
+        case 'r':
+            fUseReverse ^= 1;
+            break;
+        case 's':
+            fSeq ^= 1;
+            break;
+        case 'g':
+            fGateNames ^= 1;
             break;
-        case 'h':
-            goto usage;
         default:
             goto usage;
         }
@@ -1417,25 +1415,19 @@ int Abc_CommandPrintSkews( Abc_Frame_t * pAbc, int argc, char ** argv )
         return 1;
     }
 
-    if ( !Abc_NtkIsSeq(pNtk) && Abc_NtkLatchNum(pNtk) == 0 )
-    {
-        fprintf( pErr, "The network has no latches.\n" );
-        return 0;
-    }
-
-    if ( pNtk->vSkews == NULL || pNtk->vSkews->nSize == 0 )
-    {
-        fprintf( pErr, "The network has no clock skew schedule.\n" );
-        return 0;
-    }
-
-    Abc_NtkPrintSkews( pOut, pNtk, fPrintAll );
+    Abc_NtkShow( pNtk, fGateNames, fSeq, fUseReverse );
     return 0;
 
 usage:
-    fprintf( pErr, "usage: print_skews [-h] [-a]\n" );
-    fprintf( pErr, "\t        prints information about a clock skew schedule\n" );
-    fprintf( pErr, "\t-a    : dumps the skew of every latch [default = no]\n");
+    fprintf( pErr, "usage: show [-srgh]\n" );
+    fprintf( pErr, "       visualizes the network structure using DOT and GSVIEW\n" );
+#ifdef WIN32
+    fprintf( pErr, "       \"dot.exe\" and \"gsview32.exe\" should be set in the paths\n" );
+    fprintf( pErr, "       (\"gsview32.exe\" may be in \"C:\\Program Files\\Ghostgum\\gsview\\\")\n" );
+#endif
+    fprintf( pErr, "\t-s    : toggles visualization of sequential networks [default = %s].\n", fSeq? "yes": "no" );  
+    fprintf( pErr, "\t-r    : toggles ordering nodes in reverse order [default = %s].\n", fUseReverse? "yes": "no" );  
+    fprintf( pErr, "\t-g    : toggles printing gate names for mapped network [default = %s].\n", fGateNames? "yes": "no" );  
     fprintf( pErr, "\t-h    : print the command usage\n");
     return 1;
 }
@@ -1628,145 +1620,6 @@ usage:
     return 1;
 }
 
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Abc_CommandShowAig( Abc_Frame_t * pAbc, int argc, char ** argv )
-{
-    FILE * pOut, * pErr;
-    Abc_Ntk_t * pNtk;
-    int c;
-    int fMulti;
-    extern void Abc_NtkShowAig( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodesShow );
-    extern void Abc_NtkShowMulti( Abc_Ntk_t * pNtk );
-
-    pNtk = Abc_FrameReadNtk(pAbc);
-    pOut = Abc_FrameReadOut(pAbc);
-    pErr = Abc_FrameReadErr(pAbc);
-
-    // set defaults
-    fMulti = 0;
-    Extra_UtilGetoptReset();
-    while ( ( c = Extra_UtilGetopt( argc, argv, "mh" ) ) != EOF )
-    {
-        switch ( c )
-        {
-        case 'm':
-            fMulti ^= 1;
-            break;
-        default:
-            goto usage;
-        }
-    }
-
-    if ( pNtk == NULL )
-    {
-        fprintf( pErr, "Empty network.\n" );
-        return 1;
-    }
-
-    if ( !Abc_NtkIsStrash(pNtk) )
-    {
-        fprintf( pErr, "Visualizing networks other than AIGs can be done using command \"show_ntk\".\n" );
-        return 1;
-    }
-
-    if ( fMulti && !Abc_NtkIsStrash(pNtk) )
-    {
-        fprintf( pErr, "Visualizing multi-input ANDs cannot be done for sequential network (run \"unseq\").\n" );
-        return 1;
-    }
-
-    if ( !fMulti )
-        Abc_NtkShowAig( pNtk, NULL );
-    else
-        Abc_NtkShowMulti( pNtk );
-    return 0;
-
-usage:
-    fprintf( pErr, "usage: show_aig [-h]\n" );
-    fprintf( pErr, "       visualizes the AIG with choices using DOT and GSVIEW\n" );
-#ifdef WIN32
-    fprintf( pErr, "       \"dot.exe\" and \"gsview32.exe\" should be set in the paths\n" );
-    fprintf( pErr, "       (\"gsview32.exe\" may be in \"C:\\Program Files\\Ghostgum\\gsview\\\")\n" );
-#endif
-    fprintf( pErr, "\t-m    : toggles visualization of multi-input ANDs [default = %s].\n", fMulti? "yes": "no" );  
-    fprintf( pErr, "\t-h    : print the command usage\n");
-    return 1;
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Abc_CommandShowNtk( Abc_Frame_t * pAbc, int argc, char ** argv )
-{
-    FILE * pOut, * pErr;
-    Abc_Ntk_t * pNtk;
-    int c;
-    int fGateNames;
-    extern void Abc_NtkShow( Abc_Ntk_t * pNtk, int fGateNames );
-
-    pNtk = Abc_FrameReadNtk(pAbc);
-    pOut = Abc_FrameReadOut(pAbc);
-    pErr = Abc_FrameReadErr(pAbc);
-
-    // set defaults
-    fGateNames = 0;
-    Extra_UtilGetoptReset();
-    while ( ( c = Extra_UtilGetopt( argc, argv, "gh" ) ) != EOF )
-    {
-        switch ( c )
-        {
-        case 'g':
-            fGateNames ^= 1;
-            break;
-        default:
-            goto usage;
-        }
-    }
-
-    if ( pNtk == NULL )
-    {
-        fprintf( pErr, "Empty network.\n" );
-        return 1;
-    }
-
-    if ( Abc_NtkIsStrash(pNtk) )
-    {
-        fprintf( pErr, "Visualizing AIG can only be done using command \"show_aig\".\n" );
-        return 1;
-    }
-    Abc_NtkShow( pNtk, fGateNames );
-    return 0;
-
-usage:
-    fprintf( pErr, "usage: show_ntk [-gh]\n" );
-    fprintf( pErr, "       visualizes the network structure using DOT and GSVIEW\n" );
-#ifdef WIN32
-    fprintf( pErr, "       \"dot.exe\" and \"gsview32.exe\" should be set in the paths\n" );
-    fprintf( pErr, "       (\"gsview32.exe\" may be in \"C:\\Program Files\\Ghostgum\\gsview\\\")\n" );
-#endif
-    fprintf( pErr, "\t-g    : toggles printing gate names for mapped network [default = %s].\n", fGateNames? "yes": "no" );  
-    fprintf( pErr, "\t-h    : print the command usage\n");
-    return 1;
-}
-
 
 /**Function*************************************************************
 
@@ -5136,8 +4989,8 @@ int Abc_CommandCycle( Abc_Frame_t * pAbc, int argc, char ** argv )
     pErr = Abc_FrameReadErr(pAbc);
 
     // set defaults
-    nFrames    = 50;
-    fVerbose   =  0;
+    nFrames    = 100;
+    fVerbose   =   0;
     Extra_UtilGetoptReset();
     while ( ( c = Extra_UtilGetopt( argc, argv, "Fvh" ) ) != EOF )
     {
@@ -5633,7 +5486,7 @@ int Abc_CommandIRewriteSeq( Abc_Frame_t * pAbc, int argc, char ** argv )
     pErr = Abc_FrameReadErr(pAbc);
 
     // set defaults
-    fUpdateLevel = 1;
+    fUpdateLevel = 0;
     fUseZeroCost = 0;
     fVerbose     = 0;
     Extra_UtilGetoptReset();
@@ -7343,7 +7196,7 @@ int Abc_CommandFpga( Abc_Frame_t * pAbc, int argc, char ** argv )
 
 usage:
     if ( DelayTarget == -1 ) 
-        sprintf( Buffer, "not used" );
+        sprintf( Buffer, "best possible" );
     else
         sprintf( Buffer, "%.2f", DelayTarget );
     if ( nLutSize == -1 ) 
@@ -7394,7 +7247,7 @@ int Abc_CommandFpgaFast( Abc_Frame_t * pAbc, int argc, char ** argv )
     fRecovery   = 1;
     fVerbose    = 0;
     DelayTarget =-1;
-    nLutSize    = 8;
+    nLutSize    = 5;
     Extra_UtilGetoptReset();
     while ( ( c = Extra_UtilGetopt( argc, argv, "avhDK" ) ) != EOF )
     {
@@ -7514,46 +7367,90 @@ usage:
   SeeAlso     []
 
 ***********************************************************************/
-int Abc_CommandPga( Abc_Frame_t * pAbc, int argc, char ** argv )
+int Abc_CommandIf( Abc_Frame_t * pAbc, int argc, char ** argv )
 {
+    char Buffer[100];
+    char LutSize[100];
     FILE * pOut, * pErr;
     Abc_Ntk_t * pNtk, * pNtkRes;
-    Pga_Params_t Params, * pParams = &Params;
+    If_Par_t Pars, * pPars = &Pars;
     int c;
-    extern Abc_Ntk_t * Abc_NtkPga( Pga_Params_t * pParams );
+    extern Abc_Ntk_t * Abc_NtkIf( Abc_Ntk_t * pNtk, If_Par_t * pPars );
 
     pNtk = Abc_FrameReadNtk(pAbc);
     pOut = Abc_FrameReadOut(pAbc);
     pErr = Abc_FrameReadErr(pAbc);
 
     // set defaults
-    memset( pParams, 0, sizeof(Pga_Params_t) );
-    pParams->pNtk       = pNtk;
-    pParams->pLutLib    = Abc_FrameReadLibLut();
-    pParams->fAreaFlow  = 1;
-    pParams->fArea      = 1;
-    pParams->fSwitching = 0;
-    pParams->fDropCuts  = 0;
-    pParams->fVerbose   = 0;
+    memset( pPars, 0, sizeof(If_Par_t) );
+    pPars->Mode        = 1;
+    pPars->nLutSize    = 4;
+//    pPars->pLutLib    = Abc_FrameReadLibLut();
+    pPars->nCutsMax    = 2;
+    pPars->fSeq        = 0;
+    pPars->fLatchPaths = 0;
+    pPars->nLatches    = 0;
+    pPars->pTimesArr   = Abc_NtkGetCiArrivalFloats(pNtk);
+    pPars->pTimesReq   = NULL;
+    pPars->DelayTarget = -1;
+    pPars->fVerbose    = 0;
     Extra_UtilGetoptReset();
-    while ( ( c = Extra_UtilGetopt( argc, argv, "fapdvh" ) ) != EOF )
+    while ( ( c = Extra_UtilGetopt( argc, argv, "MKCDlsvh" ) ) != EOF )
     {
         switch ( c )
         {
-        case 'f':
-            pParams->fAreaFlow ^= 1;
+        case 'M':
+            if ( globalUtilOptind >= argc )
+            {
+                fprintf( pErr, "Command line switch \"-M\" should be followed by a positive integer.\n" );
+                goto usage;
+            }
+            pPars->Mode = atoi(argv[globalUtilOptind]);
+            globalUtilOptind++;
+            if ( pPars->Mode < 0 ) 
+                goto usage;
             break;
-        case 'a':
-            pParams->fArea ^= 1;
+        case 'K':
+            if ( globalUtilOptind >= argc )
+            {
+                fprintf( pErr, "Command line switch \"-K\" should be followed by a positive integer.\n" );
+                goto usage;
+            }
+            pPars->nLutSize = atoi(argv[globalUtilOptind]);
+            globalUtilOptind++;
+            if ( pPars->nLutSize < 0 ) 
+                goto usage;
             break;
-        case 'p':
-            pParams->fSwitching ^= 1;
+        case 'C':
+            if ( globalUtilOptind >= argc )
+            {
+                fprintf( pErr, "Command line switch \"-C\" should be followed by a positive integer.\n" );
+                goto usage;
+            }
+            pPars->nCutsMax = atoi(argv[globalUtilOptind]);
+            globalUtilOptind++;
+            if ( pPars->nCutsMax < 0 ) 
+                goto usage;
             break;
-        case 'd':
-            pParams->fDropCuts ^= 1;
+        case 'D':
+            if ( globalUtilOptind >= argc )
+            {
+                fprintf( pErr, "Command line switch \"-D\" should be followed by a floating point number.\n" );
+                goto usage;
+            }
+            pPars->DelayTarget = (float)atof(argv[globalUtilOptind]);
+            globalUtilOptind++;
+            if ( pPars->DelayTarget <= 0.0 ) 
+                goto usage;
+            break;
+        case 'l':
+            pPars->fLatchPaths ^= 1;
+            break;
+        case 's':
+            pPars->fSeq ^= 1;
             break;
         case 'v':
-            pParams->fVerbose ^= 1;
+            pPars->fVerbose ^= 1;
             break;
         case 'h':
         default:
@@ -7567,8 +7464,18 @@ int Abc_CommandPga( Abc_Frame_t * pAbc, int argc, char ** argv )
         return 1;
     }
 
-    printf( "This command is not yet implemented.\n" );
-    return 0;
+    if ( pPars->Mode < 0 || pPars->Mode > 4 )
+    {
+        fprintf( pErr, "Incorrect mapping mode.\n" );
+        return 1;
+    }
+
+    // set the latch paths
+    if ( pPars->fLatchPaths )
+    {
+        for ( c = 0; c < Abc_NtkPiNum(pNtk); c++ )
+            pPars->pTimesArr[c] = -ABC_INFINITY;
+    }
 
     if ( !Abc_NtkIsStrash(pNtk) )
     {
@@ -7588,7 +7495,7 @@ int Abc_CommandPga( Abc_Frame_t * pAbc, int argc, char ** argv )
         }
         fprintf( pOut, "The network was strashed and balanced before FPGA mapping.\n" );
         // get the new network
-        pNtkRes = Abc_NtkPga( pParams );
+        pNtkRes = Abc_NtkIf( pNtk, pPars );
         if ( pNtkRes == NULL )
         {
             Abc_NtkDelete( pNtk );
@@ -7600,7 +7507,7 @@ int Abc_CommandPga( Abc_Frame_t * pAbc, int argc, char ** argv )
     else
     {
         // get the new network
-        pNtkRes = Abc_NtkPga( pParams );
+        pNtkRes = Abc_NtkIf( pNtk, pPars );
         if ( pNtkRes == NULL )
         {
             fprintf( pErr, "FPGA mapping has failed.\n" );
@@ -7612,14 +7519,28 @@ int Abc_CommandPga( Abc_Frame_t * pAbc, int argc, char ** argv )
     return 0;
 
 usage:
-    fprintf( pErr, "usage: pga [-fapdvh]\n" );
-    fprintf( pErr, "\t        performs FPGA mapping of the current network\n" );
-    fprintf( pErr, "\t-f    : toggles area flow recovery [default = %s]\n", pParams->fAreaFlow? "yes": "no" );
-    fprintf( pErr, "\t-a    : toggles area recovery [default = %s]\n", pParams->fArea? "yes": "no" );
-    fprintf( pErr, "\t-p    : optimizes power by minimizing switching activity [default = %s]\n", pParams->fSwitching? "yes": "no" );
-    fprintf( pErr, "\t-d    : toggles dropping cuts to save memory [default = %s]\n", pParams->fDropCuts? "yes": "no" );
-    fprintf( pErr, "\t-v    : toggles verbose output [default = %s]\n", pParams->fVerbose? "yes": "no" );
-    fprintf( pErr, "\t-h    : prints the command usage\n");
+    if ( pPars->DelayTarget == -1 ) 
+        sprintf( Buffer, "best possible" );
+    else
+        sprintf( Buffer, "%.2f", pPars->DelayTarget );
+    if ( pPars->nLutSize == -1 ) 
+        sprintf( LutSize, "library" );
+    else
+        sprintf( LutSize, "%d", pPars->nLutSize );
+    fprintf( pErr, "usage: if [-M num] [-K num] [-C num] [-D float] [-lsvh]\n" );
+    fprintf( pErr, "\t           performs FPGA mapping of the network as follows:\n" );
+    fprintf( pErr, "\t               1 - delay only\n" );
+    fprintf( pErr, "\t               2 - area only\n" );
+    fprintf( pErr, "\t               3 - area under delay constraints\n" );
+    fprintf( pErr, "\t               4 - area under delay constraints with area recovery\n" );
+    fprintf( pErr, "\t-M num   : the mapping mode [default = %d]\n", pPars->Mode );
+    fprintf( pErr, "\t-K num   : the number of LUT inputs (2 < num < 32) [default = %s]\n", LutSize );
+    fprintf( pErr, "\t-C num   : the max number of cuts to use (1 < num < 2^12) [default = %d]\n", pPars->nCutsMax );
+    fprintf( pErr, "\t-D float : sets the delay constraint for the mapping [default = %s]\n", Buffer );  
+    fprintf( pErr, "\t-l       : optimizes latch paths for delay, other paths for area [default = %s]\n", pPars->fLatchPaths? "yes": "no" );
+    fprintf( pErr, "\t-s       : toggles sequential mapping [default = %s]\n", pPars->fSeq? "yes": "no" );
+    fprintf( pErr, "\t-v       : toggles verbose output [default = %s]\n", pPars->fVerbose? "yes": "no" );
+    fprintf( pErr, "\t-h       : prints the command usage\n");
     return 1;
 }
 
@@ -7996,7 +7917,7 @@ int Abc_CommandRetime( Abc_Frame_t * pAbc, int argc, char ** argv )
     Mode      =  5;
     fForward  =  0;
     fBackward =  0;
-    fVerbose  =  1;
+    fVerbose  =  0;
     nMaxIters = 15;
     Extra_UtilGetoptReset();
     while ( ( c = Extra_UtilGetopt( argc, argv, "Mfbvh" ) ) != EOF )
@@ -8048,6 +7969,12 @@ int Abc_CommandRetime( Abc_Frame_t * pAbc, int argc, char ** argv )
         return 0;
     }
 
+    if ( Mode < 0 || Mode > 6 )
+    {
+        fprintf( pErr, "The mode (%d) is incorrect. Retiming is not performed.\n", Mode );
+        return 0;
+    }
+
     if ( Abc_NtkIsStrash(pNtk) )
     {
         if ( Abc_NtkGetChoiceNum(pNtk) )
@@ -8089,6 +8016,7 @@ usage:
     fprintf( pErr, "\t             3: forward and backward min-area retiming\n" );
     fprintf( pErr, "\t             4: forward and backward min-delay retiming\n" );
     fprintf( pErr, "\t             5: mode 3 followed by mode 4\n" );
+    fprintf( pErr, "\t             6: Pan's optimum-delay retiming using binary search\n" );
     fprintf( pErr, "\t-M num : the retiming algorithm to use [default = %d]\n", Mode );
     fprintf( pErr, "\t-f     : enables forward-only retiming in modes 3,4,5 [default = %s]\n", fForward? "yes": "no" );
     fprintf( pErr, "\t-b     : enables backward-only retiming in modes 3,4,5 [default = %s]\n", fBackward? "yes": "no" );
@@ -8488,6 +8416,8 @@ int Abc_CommandSeqCleanup( Abc_Frame_t * pAbc, int argc, char ** argv )
     FILE * pOut, * pErr;
     Abc_Ntk_t * pNtk;
     int c;
+    int fLatchSweep;
+    int fAutoSweep;
     int fVerbose;
 
     pNtk = Abc_FrameReadNtk(pAbc);
@@ -8495,12 +8425,20 @@ int Abc_CommandSeqCleanup( Abc_Frame_t * pAbc, int argc, char ** argv )
     pErr = Abc_FrameReadErr(pAbc);
 
     // set defaults
-    fVerbose = 1;
+    fLatchSweep = 0;
+    fAutoSweep  = 0;
+    fVerbose    = 0;
     Extra_UtilGetoptReset();
-    while ( ( c = Extra_UtilGetopt( argc, argv, "vh" ) ) != EOF )
+    while ( ( c = Extra_UtilGetopt( argc, argv, "lavh" ) ) != EOF )
     {
         switch ( c )
         {
+        case 'l':
+            fLatchSweep ^= 1;
+            break;
+        case 'a':
+            fAutoSweep ^= 1;
+            break;
         case 'v':
             fVerbose ^= 1;
             break;
@@ -8521,16 +8459,18 @@ int Abc_CommandSeqCleanup( Abc_Frame_t * pAbc, int argc, char ** argv )
         return 1;
     }
     // modify the current network
-    Abc_NtkCleanupSeq( pNtk, fVerbose );
+    Abc_NtkCleanupSeq( pNtk, fLatchSweep, fAutoSweep, fVerbose );
     return 0;
 
 usage:
-    fprintf( pErr, "usage: scleanup [-vh]\n" );
+    fprintf( pErr, "usage: scleanup [-lavh]\n" );
     fprintf( pErr, "\t         performs sequential cleanup\n" );
     fprintf( pErr, "\t         - removes nodes/latches that do not feed into POs\n" );
     fprintf( pErr, "\t         - removes and shared latches driven by constants\n" );
     fprintf( pErr, "\t         - replaces autonomous logic by free PI variables\n" );
     fprintf( pErr, "\t           (the latter may change sequential behaviour)\n" );
+    fprintf( pErr, "\t-l     : toggle sweeping latches [default = %s]\n", fLatchSweep? "yes": "no" );
+    fprintf( pErr, "\t-a     : toggle removing autonomous logic [default = %s]\n", fAutoSweep? "yes": "no" );
     fprintf( pErr, "\t-v     : toggle verbose output [default = %s]\n", fVerbose? "yes": "no" );
     fprintf( pErr, "\t-h     : print the command usage\n");
     return 1;
@@ -8694,7 +8634,7 @@ int Abc_CommandSec( Abc_Frame_t * pAbc, int argc, char ** argv )
     // set defaults
     fSat     =  0;
     fVerbose =  0;
-    nFrames  =  3;
+    nFrames  =  5;
     nSeconds = 20;
     nConfLimit = 10000;   
     nInsLimit  = 0;
@@ -8758,6 +8698,12 @@ int Abc_CommandSec( Abc_Frame_t * pAbc, int argc, char ** argv )
         }
     }
 
+    if ( Abc_NtkLatchNum(pNtk) == 0 )
+    {
+        printf( "The network has no latches. Used combinational command \"cec\".\n" );
+        return 0;
+    }
+
     pArgvNew = argv + globalUtilOptind;
     nArgcNew = argc - globalUtilOptind;
     if ( !Abc_NtkPrepareTwoNtks( pErr, pNtk, pArgvNew, nArgcNew, &pNtk1, &pNtk2, &fDelete1, &fDelete2 ) )
@@ -9290,168 +9236,6 @@ usage:
     return 1;
 }
 
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Abc_CommandHoward( Abc_Frame_t * pAbc, int argc, char ** argv )
-{
-    FILE * pOut, * pErr;
-    Abc_Ntk_t * pNtk;
-    int c;
-    int fVerbose;
-    double result;
-
-    pNtk = Abc_FrameReadNtk(pAbc);
-    pOut = Abc_FrameReadOut(pAbc);
-    pErr = Abc_FrameReadErr(pAbc);
-
-    // set defaults
-    fVerbose =  0;
-    Extra_UtilGetoptReset();
-    while ( ( c = Extra_UtilGetopt( argc, argv, "vh" ) ) != EOF )
-    {
-        switch ( c )
-        {
-        case 'v':
-            fVerbose ^= 1;
-            break;
-        default:
-            goto usage;
-        }
-    }
-
-    if ( pNtk == NULL )
-    {
-        fprintf( pErr, "Empty network.\n" );
-        return 1;
-    }
-
-    if ( !Abc_NtkIsSeq(pNtk) && Abc_NtkLatchNum(pNtk) == 0 )
-    {
-        fprintf( pErr, "The network has no latches. Analysis is not performed.\n" );
-        return 0;
-    }
-
-    if ( Abc_NtkHasAig(pNtk) )
-    {
-        // quit if there are choice nodes
-        if ( Abc_NtkGetChoiceNum(pNtk) )
-        {
-            fprintf( pErr, "Currently cannot analyze networks with choice nodes.\n" );
-            return 0;
-        }
-
-        /*
-        if ( Abc_NtkIsStrash(pNtk) )
-            pNtkRes = Abc_NtkAigToSeq(pNtk);
-        else
-            pNtkRes = Abc_NtkDup(pNtk);
-
-        */
-
-        fprintf( pErr, "Currently cannot analyze unmapped networks.\n" );
-        return 0;
-    }
-
-//    result = Seq_NtkHoward( pNtk, fVerbose );
-    result = 0;
-
-    if (result < 0) {
-      fprintf( pErr, "Analysis failed.\n" );
-      return 0;
-    }
-
-    printf("Maximum mean cycle time = %.2f\n", result);
-
-    return 1;
-
-usage:
-    fprintf( pErr, "usage: howard [-h]\n" );
-    fprintf( pErr, "\t         computes the maximum mean cycle time using Howard's algorithm\n" );
-    fprintf( pErr, "\t-v     : toggles verbose output [default = %s]\n", fVerbose? "yes": "no" );
-    fprintf( pErr, "\t-h     : print the command usage\n");
-    return 1;
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Abc_CommandSkewForward( Abc_Frame_t * pAbc, int argc, char ** argv )
-{
-    FILE * pOut, * pErr;
-    Abc_Ntk_t * pNtk;
-    int c;
-    int fMinimize;
-    float target;
-
-    pNtk = Abc_FrameReadNtk(pAbc);
-    pOut = Abc_FrameReadOut(pAbc);
-    pErr = Abc_FrameReadErr(pAbc);
-
-    // set defaults
-    target = pNtk->maxMeanCycle;
-    fMinimize =  0;
-    Extra_UtilGetoptReset();
-    while ( ( c = Extra_UtilGetopt( argc, argv, "mh" ) ) != EOF )
-    {
-        switch ( c )
-        {
-        case 'm':
-            fMinimize ^= 1;
-            break;
-        default:
-            goto usage;
-        }
-    }
-
-
-    if ( pNtk == NULL )
-    {
-        fprintf( pErr, "Empty network.\n" );
-        return 1;
-    }
-
-    if ( !Abc_NtkIsSeq(pNtk) && Abc_NtkLatchNum(pNtk) == 0 )
-    {
-        fprintf( pErr, "The network has no latches.\n" );
-        return 0;
-    }
-
-    if ( pNtk->vSkews == NULL || pNtk->vSkews->nSize == 0 )
-    {
-        fprintf( pErr, "The network has no clock skew schedule.\n" );
-        return 0;
-    }
-
-//    Seq_NtkSkewForward( pNtk, target, fMinimize );
-
-    return 1;
-
-usage:
-    fprintf( pErr, "usage: skew_fwd [-h] [-m] [-t float]\n" );
-    fprintf( pErr, "\t         converts a skew schedule into a set of forward skews 0<skew<T\n" );
-    fprintf( pErr, "\t-m     : minimizes sum of skews [default = %s]\n", fMinimize? "yes": "no" );
-    fprintf( pErr, "\t-t     : clock period, T [default = maxMeanCycle] (unimplemented)\n");
-    fprintf( pErr, "\t-h     : print the command usage\n");
-    return 1;
-}
-
 ////////////////////////////////////////////////////////////////////////
 ///                       END OF FILE                                ///
 ////////////////////////////////////////////////////////////////////////
diff --git a/src/base/abci/abcAuto.c b/src/base/abci/abcAuto.c
index cc6e8913..3b307ac2 100644
--- a/src/base/abci/abcAuto.c
+++ b/src/base/abci/abcAuto.c
@@ -49,16 +49,24 @@ void Abc_NtkAutoPrint( Abc_Ntk_t * pNtk, int Output, int fNaive, int fVerbose )
     char ** pInputNames;    // pointers to the CI names
     char ** pOutputNames;   // pointers to the CO names
     int nOutputs, nInputs, i;
+    Vec_Ptr_t * vFuncsGlob;
+    Abc_Obj_t * pObj;
 
     // compute the global BDDs
-    if ( Abc_NtkGlobalBdds(pNtk, 10000000, 0, 1, fVerbose) == NULL )
+    if ( Abc_NtkBuildGlobalBdds(pNtk, 10000000, 1, 1, fVerbose) == NULL )
         return;
 
     // get information about the network
     nInputs  = Abc_NtkCiNum(pNtk);
     nOutputs = Abc_NtkCoNum(pNtk);
-    dd       = pNtk->pManGlob;
-    pbGlobal = (DdNode **)Vec_PtrArray( pNtk->vFuncsGlob );
+//    dd       = pNtk->pManGlob;
+    dd = Abc_NtkGlobalBddMan( pNtk );
+
+    // complement the global functions
+    vFuncsGlob = Vec_PtrAlloc( Abc_NtkCoNum(pNtk) );
+    Abc_NtkForEachCo( pNtk, pObj, i )
+        Vec_PtrPush( vFuncsGlob, Abc_ObjGlobalBdd(pObj) );
+    pbGlobal = (DdNode **)Vec_PtrArray( vFuncsGlob );
 
     // get the network names
     pInputNames = Abc_NtkCollectCioNames( pNtk, 0 );
@@ -83,12 +91,14 @@ void Abc_NtkAutoPrint( Abc_Ntk_t * pNtk, int Output, int fNaive, int fVerbose )
         Abc_NtkAutoPrintOne( dd, nInputs, pbGlobal, Output, pInputNames, pOutputNames, fNaive );
 
     // deref the PO functions
-    Abc_NtkFreeGlobalBdds( pNtk );
+//    Abc_NtkFreeGlobalBdds( pNtk );
     // stop the global BDD manager
-    Extra_StopManager( pNtk->pManGlob );
-    pNtk->pManGlob = NULL;
+//    Extra_StopManager( pNtk->pManGlob );
+//    pNtk->pManGlob = NULL;
+    Abc_NtkFreeGlobalBdds( pNtk, 1 );
     free( pInputNames );
     free( pOutputNames );
+    Vec_PtrFree( vFuncsGlob );
 }
 
 /**Function*************************************************************
diff --git a/src/base/abci/abcClpBdd.c b/src/base/abci/abcClpBdd.c
index 650f379f..ce67aff7 100644
--- a/src/base/abci/abcClpBdd.c
+++ b/src/base/abci/abcClpBdd.c
@@ -49,25 +49,27 @@ Abc_Ntk_t * Abc_NtkCollapse( Abc_Ntk_t * pNtk, int fBddSizeMax, int fDualRail, i
 
     assert( Abc_NtkIsStrash(pNtk) );
     // compute the global BDDs
-    if ( Abc_NtkGlobalBdds(pNtk, fBddSizeMax, 0, fReorder, fVerbose) == NULL )
+    if ( Abc_NtkBuildGlobalBdds(pNtk, fBddSizeMax, 1, fReorder, fVerbose) == NULL )
         return NULL;
     if ( fVerbose )
     {
-        printf( "The shared BDD size is %d nodes.  ", Cudd_ReadKeys(pNtk->pManGlob) - Cudd_ReadDead(pNtk->pManGlob) );
+        DdManager * dd = Abc_NtkGlobalBddMan( pNtk );
+        printf( "The shared BDD size is %d nodes.  ", Cudd_ReadKeys(dd) - Cudd_ReadDead(dd) );
         PRT( "BDD construction time", clock() - clk );
     }
 
     // create the new network
     pNtkNew = Abc_NtkFromGlobalBdds( pNtk );
-    Abc_NtkFreeGlobalBdds( pNtk );
+//    Abc_NtkFreeGlobalBdds( pNtk );
+    Abc_NtkFreeGlobalBdds( pNtk, 1 );
     if ( pNtkNew == NULL )
     {
-        Cudd_Quit( pNtk->pManGlob );
-        pNtk->pManGlob = NULL;
+//        Cudd_Quit( pNtk->pManGlob );
+//        pNtk->pManGlob = NULL;
         return NULL;
     }
-    Extra_StopManager( pNtk->pManGlob );
-    pNtk->pManGlob = NULL;
+//    Extra_StopManager( pNtk->pManGlob );
+//    pNtk->pManGlob = NULL;
 
     // make the network minimum base
     Abc_NtkMinimumBase( pNtkNew );
@@ -100,8 +102,9 @@ Abc_Ntk_t * Abc_NtkFromGlobalBdds( Abc_Ntk_t * pNtk )
 {
     ProgressBar * pProgress;
     Abc_Ntk_t * pNtkNew;
-    Abc_Obj_t * pNode, * pNodeNew;
-    DdManager * dd = pNtk->pManGlob;
+    Abc_Obj_t * pNode, * pDriver, * pNodeNew;
+//    DdManager * dd = pNtk->pManGlob;
+    DdManager * dd = Abc_NtkGlobalBddMan( pNtk );
     int i;
     // start the new network
     pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC, ABC_FUNC_BDD );
@@ -112,7 +115,14 @@ Abc_Ntk_t * Abc_NtkFromGlobalBdds( Abc_Ntk_t * pNtk )
     Abc_NtkForEachCo( pNtk, pNode, i )
     {
         Extra_ProgressBarUpdate( pProgress, i, NULL );
-        pNodeNew = Abc_NodeFromGlobalBdds( pNtkNew, dd, Vec_PtrEntry(pNtk->vFuncsGlob, i) );
+        pDriver = Abc_ObjFanin0(pNode);
+        if ( Abc_ObjIsCi(pDriver) && !strcmp(Abc_ObjName(pNode), Abc_ObjName(pDriver)) )
+        {
+            Abc_ObjAddFanin( pNode->pCopy, pDriver->pCopy );
+            continue;
+        }
+//        pNodeNew = Abc_NodeFromGlobalBdds( pNtkNew, dd, Vec_PtrEntry(pNtk->vFuncsGlob, i) );
+        pNodeNew = Abc_NodeFromGlobalBdds( pNtkNew, dd, Abc_ObjGlobalBdd(pNode) );
         Abc_ObjAddFanin( pNode->pCopy, pNodeNew );
     }
     Extra_ProgressBarStop( pProgress );
diff --git a/src/base/abci/abcCut.c b/src/base/abci/abcCut.c
index c021728a..f1dd4ab5 100644
--- a/src/base/abci/abcCut.c
+++ b/src/base/abci/abcCut.c
@@ -202,6 +202,7 @@ void Abc_NtkCutsOracle( Abc_Ntk_t * pNtk, Cut_Oracle_t * p )
 ***********************************************************************/
 Cut_Man_t * Abc_NtkSeqCuts( Abc_Ntk_t * pNtk, Cut_Params_t * pParams )
 {
+/*
     Cut_Man_t *  p;
     Abc_Obj_t * pObj, * pNode;
     int i, nIters, fStatus;
@@ -288,6 +289,8 @@ printf( "Converged after %d iterations.\n", nIters );
 }
 //Abc_NtkPrintCuts( p, pNtk, 1 );
     return p;
+*/
+    return NULL;
 }
 
 /**Function*************************************************************
diff --git a/src/base/abci/abcDebug.c b/src/base/abci/abcDebug.c
index 4d37c496..7771148e 100644
--- a/src/base/abci/abcDebug.c
+++ b/src/base/abci/abcDebug.c
@@ -86,7 +86,8 @@ void Abc_NtkAutoDebug( Abc_Ntk_t * pNtk, int (*pFuncError) (Abc_Ntk_t *) )
             else // no bug
                 Abc_NtkDelete( pNtkMod );
         }
-        printf( "Iteration %6d : Nodes = %6d. Steps = %6d. Error step = %3d.  ", nIter, Abc_NtkObjNum(pNtk), nSteps, i );
+        printf( "Iter %6d : Latches = %6d. Nodes = %6d. Steps = %6d. Error step = %3d.  ", 
+            nIter, Abc_NtkLatchNum(pNtk), Abc_NtkNodeNum(pNtk), nSteps, i );
         PRT( "Time", clock() - clk );
         if ( i == nSteps ) // could not modify it while preserving the bug
             break;
@@ -116,7 +117,11 @@ int Abc_NtkCountFaninsTotal( Abc_Ntk_t * pNtk )
     Abc_NtkForEachObj( pNtk, pObj, i )
         Abc_ObjForEachFanin( pObj, pFanin, k )
         {
-            if ( Abc_NodeIsConst(pFanin) )
+            if ( !Abc_ObjIsNode(pObj) && !Abc_ObjIsPo(pObj) )
+                continue;
+            if ( Abc_ObjIsPo(pObj) && Abc_NtkPoNum(pNtk) == 1 )
+                continue;
+            if ( Abc_ObjIsNode(pObj) && Abc_NodeIsConst(pFanin) )
                 continue;
             Counter++;
         }
@@ -141,7 +146,11 @@ int Abc_NtkFindGivenFanin( Abc_Ntk_t * pNtk, int Step, Abc_Obj_t ** ppObj, Abc_O
     Abc_NtkForEachObj( pNtk, pObj, i )
         Abc_ObjForEachFanin( pObj, pFanin, k )
         {
-            if ( Abc_NodeIsConst(pFanin) )
+            if ( !Abc_ObjIsNode(pObj) && !Abc_ObjIsPo(pObj) )
+                continue;
+            if ( Abc_ObjIsPo(pObj) && Abc_NtkPoNum(pNtk) == 1 )
+                continue;
+            if ( Abc_ObjIsNode(pObj) && Abc_NodeIsConst(pFanin) )
                 continue;
             if ( Counter++ == Step )
             {
@@ -166,6 +175,7 @@ int Abc_NtkFindGivenFanin( Abc_Ntk_t * pNtk, int Step, Abc_Obj_t ** ppObj, Abc_O
 ***********************************************************************/
 Abc_Ntk_t * Abc_NtkAutoDebugModify( Abc_Ntk_t * pNtkInit, int Step, int fConst1 )
 {
+    extern void Abc_NtkCycleInitStateSop( Abc_Ntk_t * pNtk, int nFrames, int fVerbose );
     Abc_Ntk_t * pNtk;
     Abc_Obj_t * pObj, * pFanin, * pConst;
     // copy the network
@@ -185,9 +195,9 @@ Abc_Ntk_t * Abc_NtkAutoDebugModify( Abc_Ntk_t * pNtkInit, int Step, int fConst1
     Abc_NtkDeleteAll_rec( pFanin );
 
     Abc_NtkSweep( pNtk, 0 );
-    Abc_NtkCleanupSeq( pNtk, 0 );
+    Abc_NtkCleanupSeq( pNtk, 0, 0, 0 );
     Abc_NtkLogicToSop( pNtk, 0 );
-    Abc_NtkCycleInitStateSop( pNtk, 20, 0 );
+    Abc_NtkCycleInitStateSop( pNtk, 50, 0 );
     return pNtk;
 }
 
diff --git a/src/base/abci/abcDsd.c b/src/base/abci/abcDsd.c
index b38012cd..200f4eec 100644
--- a/src/base/abci/abcDsd.c
+++ b/src/base/abci/abcDsd.c
@@ -55,31 +55,22 @@ static int             Abc_NodeFindMuxVar( DdManager * dd, DdNode * bFunc, int n
 ***********************************************************************/
 Abc_Ntk_t * Abc_NtkDsdGlobal( Abc_Ntk_t * pNtk, bool fVerbose, bool fPrint, bool fShort )
 {
+    DdManager * dd;
     Abc_Ntk_t * pNtkNew;
-
     assert( Abc_NtkIsStrash(pNtk) );
-
-    // perform FPGA mapping
-    if ( Abc_NtkGlobalBdds(pNtk, 10000000, 0, 1, fVerbose) == NULL )
+    dd = Abc_NtkBuildGlobalBdds( pNtk, 10000000, 1, 1, fVerbose );
+    if ( dd == NULL )
         return NULL;
     if ( fVerbose )
-        printf( "The shared BDD size is %d nodes.\n", Cudd_ReadKeys(pNtk->pManGlob) - Cudd_ReadDead(pNtk->pManGlob) );
-
+        printf( "The shared BDD size is %d nodes.\n", Cudd_ReadKeys(dd) - Cudd_ReadDead(dd) );
     // transform the result of mapping into a BDD network
     pNtkNew = Abc_NtkDsdInternal( pNtk, fVerbose, fPrint, fShort );
+    Extra_StopManager( dd );
     if ( pNtkNew == NULL )
-    {
-        Cudd_Quit( pNtk->pManGlob );
-        pNtk->pManGlob = NULL;
         return NULL;
-    }
-    Extra_StopManager( pNtk->pManGlob );
-    pNtk->pManGlob = NULL;
-
+    // copy EXDC network
     if ( pNtk->pExdc )
         pNtkNew->pExdc = Abc_NtkDup( pNtk->pExdc );
-
-    // make sure that everything is okay
     if ( !Abc_NtkCheck( pNtkNew ) )
     {
         printf( "Abc_NtkDsdGlobal: The network check has failed.\n" );
@@ -102,26 +93,25 @@ Abc_Ntk_t * Abc_NtkDsdGlobal( Abc_Ntk_t * pNtk, bool fVerbose, bool fPrint, bool
 ***********************************************************************/
 Abc_Ntk_t * Abc_NtkDsdInternal( Abc_Ntk_t * pNtk, bool fVerbose, bool fPrint, bool fShort )
 {
-    DdManager * dd = pNtk->pManGlob;
+    char ** ppNamesCi, ** ppNamesCo;
+    Vec_Ptr_t * vFuncsGlob;
     Dsd_Manager_t * pManDsd;
     Abc_Ntk_t * pNtkNew;
-    DdNode * bFunc;
-    char ** ppNamesCi, ** ppNamesCo;
+    DdManager * dd;
     Abc_Obj_t * pObj;
     int i;
 
     // complement the global functions
+    vFuncsGlob = Vec_PtrAlloc( Abc_NtkCoNum(pNtk) );
     Abc_NtkForEachCo( pNtk, pObj, i )
-    {
-        bFunc = Vec_PtrEntry(pNtk->vFuncsGlob, i);
-        Vec_PtrWriteEntry(pNtk->vFuncsGlob, i, Cudd_NotCond(bFunc, Abc_ObjFaninC0(pObj)) );
-    }
+        Vec_PtrPush( vFuncsGlob, Cudd_NotCond(Abc_ObjGlobalBdd(pObj), Abc_ObjFaninC0(pObj)) );
 
     // perform the decomposition
-    assert( Vec_PtrSize(pNtk->vFuncsGlob) == Abc_NtkCoNum(pNtk) );
+    dd = Abc_NtkGlobalBddMan(pNtk);
     pManDsd = Dsd_ManagerStart( dd, Abc_NtkCiNum(pNtk), fVerbose );
-    Dsd_Decompose( pManDsd, (DdNode **)pNtk->vFuncsGlob->pArray, Abc_NtkCoNum(pNtk) );
-    Abc_NtkFreeGlobalBdds( pNtk );
+    Dsd_Decompose( pManDsd, (DdNode **)vFuncsGlob->pArray, Abc_NtkCoNum(pNtk) );
+    Vec_PtrFree( vFuncsGlob );
+    Abc_NtkFreeGlobalBdds( pNtk, 0 );
     if ( pManDsd == NULL )
     {
         Cudd_Quit( dd );
@@ -138,7 +128,6 @@ Abc_Ntk_t * Abc_NtkDsdInternal( Abc_Ntk_t * pNtk, bool fVerbose, bool fPrint, bo
     Abc_NtkFinalize( pNtk, pNtkNew );
     // fix the problem with complemented and duplicated CO edges
     Abc_NtkLogicMakeSimpleCos( pNtkNew, 0 );
-
     if ( fPrint )
     {
         ppNamesCi = Abc_NtkCollectCioNames( pNtk, 0 );
diff --git a/src/base/abci/abcFpgaFast.c b/src/base/abci/abcFpgaFast.c
index 3ad29291..356b855e 100644
--- a/src/base/abci/abcFpgaFast.c
+++ b/src/base/abci/abcFpgaFast.c
@@ -118,7 +118,7 @@ Abc_Ntk_t * Ivy_ManFpgaToAbc( Abc_Ntk_t * pNtk, Ivy_Man_t * pMan )
                 // clone the node
                 pObj = Abc_NtkCloneObj( pObjAbc );
                 // set complemented functions
-                pObj->pData = Aig_Not( pObjAbc->pData );
+                pObj->pData = Hop_Not( pObjAbc->pData );
                 // return the new node
                 pObjAbc = pObj;
             }
@@ -172,9 +172,9 @@ Abc_Obj_t * Ivy_ManToAbcFast_rec( Abc_Ntk_t * pNtkNew, Ivy_Man_t * pMan, Ivy_Obj
     Ivy_ManForEachNodeVec( pMan, vNodes, pNodeIvy, i )
     {
         if ( i < Vec_IntSize(vSupp) )
-            pNodeIvy->pEquiv = (Ivy_Obj_t *)Aig_IthVar( pNtkNew->pManFunc, i );
+            pNodeIvy->pEquiv = (Ivy_Obj_t *)Hop_IthVar( pNtkNew->pManFunc, i );
         else
-            pNodeIvy->pEquiv = (Ivy_Obj_t *)Aig_And( pNtkNew->pManFunc, (Aig_Obj_t *)Ivy_ObjChild0Equiv(pNodeIvy), (Aig_Obj_t *)Ivy_ObjChild1Equiv(pNodeIvy) );
+            pNodeIvy->pEquiv = (Ivy_Obj_t *)Hop_And( pNtkNew->pManFunc, (Hop_Obj_t *)Ivy_ObjChild0Equiv(pNodeIvy), (Hop_Obj_t *)Ivy_ObjChild1Equiv(pNodeIvy) );
     }
     // set the local function
     pObjAbc->pData = (Abc_Obj_t *)pObjIvy->pEquiv;
diff --git a/src/base/abci/abcIf.c b/src/base/abci/abcIf.c
new file mode 100644
index 00000000..6b3e0e7c
--- /dev/null
+++ b/src/base/abci/abcIf.c
@@ -0,0 +1,287 @@
+/**CFile****************************************************************
+
+  FileName    [abcIf.c]
+
+  SystemName  [ABC: Logic synthesis and verification system.]
+
+  PackageName [Network and node package.]
+
+  Synopsis    [Interface with the FPGA mapping package.]
+
+  Author      [Alan Mishchenko]
+  
+  Affiliation [UC Berkeley]
+
+  Date        [Ver. 1.0. Started - November 21, 2006.]
+
+  Revision    [$Id: abcIf.c,v 1.00 2006/11/21 00:00:00 alanmi Exp $]
+
+***********************************************************************/
+
+#include "abc.h"
+#include "if.h"
+
+////////////////////////////////////////////////////////////////////////
+///                        DECLARATIONS                              ///
+////////////////////////////////////////////////////////////////////////
+
+static If_Man_t *  Abc_NtkToIf( Abc_Ntk_t * pNtk, If_Par_t * pPars );
+static Abc_Ntk_t * Abc_NtkFromIf( If_Man_t * pIfMan, Abc_Ntk_t * pNtk );
+static Abc_Obj_t * Abc_NodeFromIf_rec( Abc_Ntk_t * pNtkNew, If_Man_t * pIfMan, If_Obj_t * pIfObj );
+static Hop_Obj_t * Abc_NodeIfToHop( Hop_Man_t * pHopMan, If_Man_t * pIfMan, If_Cut_t * pCut );
+ 
+////////////////////////////////////////////////////////////////////////
+///                     FUNCTION DEFINITIONS                         ///
+////////////////////////////////////////////////////////////////////////
+
+/**Function*************************************************************
+
+  Synopsis    [Interface with the FPGA mapping package.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Abc_Ntk_t * Abc_NtkIf( Abc_Ntk_t * pNtk, If_Par_t * pPars )
+{
+    Abc_Ntk_t * pNtkNew;
+    If_Man_t * pIfMan;
+
+    assert( Abc_NtkIsStrash(pNtk) );
+
+    // print a warning about choice nodes
+    if ( Abc_NtkGetChoiceNum( pNtk ) )
+        printf( "Performing FPGA mapping with choices.\n" );
+
+    // perform FPGA mapping
+    pIfMan = Abc_NtkToIf( pNtk, pPars );    
+    if ( pIfMan == NULL )
+        return NULL;
+    if ( !If_ManPerformMapping( pIfMan ) )
+    {
+        If_ManStop( pIfMan );
+        return NULL;
+    }
+
+    // transform the result of mapping into a BDD network
+    pNtkNew = Abc_NtkFromIf( pIfMan, pNtk );
+    if ( pNtkNew == NULL )
+        return NULL;
+    If_ManStop( pIfMan );
+
+    // duplicate EXDC
+    if ( pNtk->pExdc )
+        pNtkNew->pExdc = Abc_NtkDup( pNtk->pExdc );
+
+    // make sure that everything is okay
+    if ( !Abc_NtkCheck( pNtkNew ) )
+    {
+        printf( "Abc_NtkIf: The network check has failed.\n" );
+        Abc_NtkDelete( pNtkNew );
+        return NULL;
+    }
+    return pNtkNew;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Load the network into FPGA manager.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+If_Man_t * Abc_NtkToIf( Abc_Ntk_t * pNtk, If_Par_t * pPars )
+{
+    ProgressBar * pProgress;
+    If_Man_t * pIfMan;
+    Abc_Obj_t * pNode, * pFanin, * pPrev;
+    int i;
+
+    assert( Abc_NtkIsStrash(pNtk) );
+
+    // start the mapping manager and set its parameters
+    pIfMan = If_ManStart( pPars );
+
+    // create PIs and remember them in the old nodes
+    Abc_AigConst1(pNtk)->pCopy = (Abc_Obj_t *)If_ManConst1( pIfMan );
+    Abc_NtkForEachCi( pNtk, pNode, i )
+        pNode->pCopy = (Abc_Obj_t *)If_ManCreatePi( pIfMan );
+
+    // load the AIG into the mapper
+    pProgress = Extra_ProgressBarStart( stdout, Abc_NtkNodeNum(pNtk) );
+    Abc_AigForEachAnd( pNtk, pNode, i )
+    {
+        Extra_ProgressBarUpdate( pProgress, i, NULL );
+        // add the node to the mapper
+        pNode->pCopy = (Abc_Obj_t *)If_ManCreateAnd( pIfMan, 
+            (If_Obj_t *)Abc_ObjFanin0(pNode)->pCopy, Abc_ObjFaninC0(pNode), 
+            (If_Obj_t *)Abc_ObjFanin1(pNode)->pCopy, Abc_ObjFaninC1(pNode) );
+        // set up the choice node
+        if ( Abc_AigNodeIsChoice( pNode ) )
+            for ( pPrev = pNode, pFanin = pNode->pData; pFanin; pPrev = pFanin, pFanin = pFanin->pData )
+                If_ObjSetChoice( (If_Obj_t *)pPrev->pCopy, (If_Obj_t *)pFanin->pCopy );
+    }
+    Extra_ProgressBarStop( pProgress );
+
+    // set the primary outputs without copying the phase
+    Abc_NtkForEachCo( pNtk, pNode, i )
+        If_ManCreatePo( pIfMan, (If_Obj_t *)Abc_ObjFanin0(pNode)->pCopy, Abc_ObjFaninC0(pNode) );
+    return pIfMan;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Creates the mapped network.]
+
+  Description [Assuming the copy field of the mapped nodes are NULL.]
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Abc_Ntk_t * Abc_NtkFromIf( If_Man_t * pIfMan, Abc_Ntk_t * pNtk )
+{
+    ProgressBar * pProgress;
+    Abc_Ntk_t * pNtkNew;
+    Abc_Obj_t * pNode, * pNodeNew;
+    int i, nDupGates;
+    // create the new network
+    pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC, ABC_FUNC_AIG );
+    // prepare the mapping manager
+    If_ManCleanNodeCopy( pIfMan );
+    If_ManCleanCutData( pIfMan );
+    // make the mapper point to the new network
+    If_ObjSetCopy( If_ManConst1(pIfMan), Abc_NtkCreateNodeConst1(pNtkNew) );
+    Abc_NtkForEachCi( pNtk, pNode, i )
+        If_ObjSetCopy( If_ManPi(pIfMan, i), pNode->pCopy );
+    // process the nodes in topological order
+    pProgress = Extra_ProgressBarStart( stdout, Abc_NtkCoNum(pNtk) );
+    Abc_NtkForEachCo( pNtk, pNode, i )
+    {
+        Extra_ProgressBarUpdate( pProgress, i, NULL );
+        pNodeNew = Abc_NodeFromIf_rec( pNtkNew, pIfMan, If_ObjFanin0(If_ManPo(pIfMan, i)) );
+        pNodeNew = Abc_ObjNotCond( pNodeNew, If_ObjFaninC0(If_ManPo(pIfMan, i)) );
+        Abc_ObjAddFanin( pNode->pCopy, pNodeNew );
+    }
+    Extra_ProgressBarStop( pProgress );
+    // remove the constant node if not used
+    pNodeNew = (Abc_Obj_t *)If_ObjCopy( If_ManConst1(pIfMan) );
+    if ( Abc_ObjFanoutNum(pNodeNew) == 0 )
+        Abc_NtkDeleteObj( pNodeNew );
+    // decouple the PO driver nodes to reduce the number of levels
+    nDupGates = Abc_NtkLogicMakeSimpleCos( pNtkNew, 1 );
+//    if ( nDupGates && If_ManReadVerbose(pIfMan) )
+//        printf( "Duplicated %d gates to decouple the CO drivers.\n", nDupGates );
+    return pNtkNew;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Derive one node after FPGA mapping.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Abc_Obj_t * Abc_NodeFromIf_rec( Abc_Ntk_t * pNtkNew, If_Man_t * pIfMan, If_Obj_t * pIfObj )
+{
+    Abc_Obj_t * pNodeNew;
+    If_Cut_t * pCutBest;
+    If_Obj_t * pIfLeaf;
+    int i;
+    // return if the result if known
+    pNodeNew = (Abc_Obj_t *)If_ObjCopy( pIfObj );
+    if ( pNodeNew )
+        return pNodeNew;
+    assert( pIfObj->Type == IF_AND );
+    // get the parameters of the best cut
+    // create a new node 
+    pNodeNew = Abc_NtkCreateNode( pNtkNew );
+    pCutBest = If_ObjCutBest( pIfObj );
+    If_CutForEachLeaf( pIfMan, pCutBest, pIfLeaf, i )
+        Abc_ObjAddFanin( pNodeNew, Abc_NodeFromIf_rec(pNtkNew, pIfMan, pIfLeaf) );
+    // derive the function of this node
+    pNodeNew->pData = Abc_NodeIfToHop( pNtkNew->pManFunc, pIfMan, pCutBest );
+    If_ObjSetCopy( pIfObj, pNodeNew );
+    return pNodeNew;
+}
+
+
+/**Function*************************************************************
+
+  Synopsis    [Recursively derives the truth table for the cut.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Hop_Obj_t * Abc_NodeIfToHop_rec( Hop_Man_t * pHopMan, If_Man_t * pIfMan, If_Cut_t * pCut, Vec_Ptr_t * vVisited )
+{
+    Hop_Obj_t * gFunc, * gFunc0, * gFunc1;
+    // if the cut is visited, return the result
+    if ( If_CutData(pCut) )
+        return If_CutData(pCut);
+    // compute the functions of the children
+    gFunc0 = Abc_NodeIfToHop_rec( pHopMan, pIfMan, pCut->pOne, vVisited );
+    gFunc1 = Abc_NodeIfToHop_rec( pHopMan, pIfMan, pCut->pTwo, vVisited );
+    // get the function of the cut
+    gFunc  = Hop_And( pHopMan, Hop_NotCond(gFunc0, pCut->fCompl0), Hop_NotCond(gFunc1, pCut->fCompl1) );  
+    gFunc  = Hop_NotCond( gFunc, pCut->Phase );
+    assert( If_CutData(pCut) == NULL );
+    If_CutSetData( pCut, gFunc );
+    // add this cut to the visited list
+    Vec_PtrPush( vVisited, pCut );
+    return gFunc;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Derives the truth table for one cut.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Hop_Obj_t * Abc_NodeIfToHop( Hop_Man_t * pHopMan, If_Man_t * pIfMan, If_Cut_t * pCut )
+{
+    Hop_Obj_t * gFunc;
+    If_Obj_t * pLeaf;
+    int i;
+    assert( pCut->nLeaves > 1 );
+    // set the leaf variables
+    If_CutForEachLeaf( pIfMan, pCut, pLeaf, i )
+        If_CutSetData( If_ObjCutTriv(pLeaf), Hop_IthVar(pHopMan, i) );
+    // recursively compute the function while collecting visited cuts
+    Vec_PtrClear( pIfMan->vTemp );
+    gFunc = Abc_NodeIfToHop_rec( pHopMan, pIfMan, pCut, pIfMan->vTemp ); 
+//    printf( "%d ", Vec_PtrSize(p->vTemp) );
+    // clean the cuts
+    If_CutForEachLeaf( pIfMan, pCut, pLeaf, i )
+        If_CutSetData( If_ObjCutTriv(pLeaf), NULL );
+    Vec_PtrForEachEntry( pIfMan->vTemp, pCut, i )
+        If_CutSetData( pCut, NULL );
+    return gFunc;
+}
+
+////////////////////////////////////////////////////////////////////////
+///                       END OF FILE                                ///
+////////////////////////////////////////////////////////////////////////
+
+
diff --git a/src/base/abci/abcIvy.c b/src/base/abci/abcIvy.c
index 30ed21cf..be8b8ec5 100644
--- a/src/base/abci/abcIvy.c
+++ b/src/base/abci/abcIvy.c
@@ -53,6 +53,8 @@ static inline Abc_Obj_t *  Abc_ObjFanin1Ivy( Abc_Ntk_t * p, Ivy_Obj_t * pObj ) {
 
 static Vec_Int_t * Abc_NtkCollectLatchValuesIvy( Abc_Ntk_t * pNtk, int fUseDcs );
 
+extern int timeRetime;
+
 ////////////////////////////////////////////////////////////////////////
 ///                     FUNCTION DEFINITIONS                         ///
 ////////////////////////////////////////////////////////////////////////
@@ -72,6 +74,7 @@ Ivy_Man_t * Abc_NtkIvyBefore( Abc_Ntk_t * pNtk, int fSeq, int fUseDc )
 {
     Ivy_Man_t * pMan;
     int fCleanup = 1;
+//timeRetime = clock();
     assert( !Abc_NtkIsNetlist(pNtk) );
     assert( !Abc_NtkIsSeq(pNtk) );
     if ( Abc_NtkIsBddLogic(pNtk) )
@@ -107,6 +110,7 @@ Ivy_Man_t * Abc_NtkIvyBefore( Abc_Ntk_t * pNtk, int fSeq, int fUseDc )
         Vec_IntFree( vInit );
 //        Ivy_ManPrintStats( pMan );
     }
+//timeRetime = clock() - timeRetime;
     return pMan;
 }
 
@@ -184,17 +188,22 @@ Abc_Ntk_t * Abc_NtkIvyHaig( Abc_Ntk_t * pNtk, int nIters, int fUseZeroCost, int
 {
     Abc_Ntk_t * pNtkAig;
     Ivy_Man_t * pMan;
-    int i;
+//    int i;
 
     pMan = Abc_NtkIvyBefore( pNtk, 1, 1 );
     if ( pMan == NULL )
         return NULL;
+//timeRetime = clock();
 
     Ivy_ManHaigStart( pMan, fVerbose );
 //    Ivy_ManRewriteSeq( pMan, 0, 0 );
-    for ( i = 0; i < nIters; i++ )
-        Ivy_ManRewriteSeq( pMan, fUseZeroCost, 0 );
-    Ivy_ManHaigPostprocess( pMan, fVerbose );
+//    for ( i = 0; i < nIters; i++ )
+//        Ivy_ManRewriteSeq( pMan, fUseZeroCost, 0 );
+    Ivy_ManRewriteSeq( pMan, 0, 0 );
+    Ivy_ManRewriteSeq( pMan, 1, 0 );
+//printf( "Haig size = %d.\n", Ivy_ManNodeNum(pMan->pHaig) );
+//    Ivy_ManHaigPostprocess( pMan, fVerbose );
+//timeRetime = clock() - timeRetime;
 
     // write working AIG into the current network
 //    pNtkAig = Abc_NtkIvyAfter( pNtk, pMan, 1, 0 ); 
@@ -246,7 +255,9 @@ Abc_Ntk_t * Abc_NtkIvyRewrite( Abc_Ntk_t * pNtk, int fUpdateLevel, int fUseZeroC
     pMan = Abc_NtkIvyBefore( pNtk, 0, 0 );
     if ( pMan == NULL )
         return NULL;
+//timeRetime = clock();
     Ivy_ManRewritePre( pMan, fUpdateLevel, fUseZeroCost, fVerbose );
+//timeRetime = clock() - timeRetime;
     pNtkAig = Abc_NtkIvyAfter( pNtk, pMan, 0, 0 );
     Ivy_ManStop( pMan );
     return pNtkAig;
@@ -270,7 +281,9 @@ Abc_Ntk_t * Abc_NtkIvyRewriteSeq( Abc_Ntk_t * pNtk, int fUseZeroCost, int fVerbo
     pMan = Abc_NtkIvyBefore( pNtk, 1, 1 );
     if ( pMan == NULL )
         return NULL;
+//timeRetime = clock();
     Ivy_ManRewriteSeq( pMan, fUseZeroCost, fVerbose );
+//timeRetime = clock() - timeRetime;
 //    Ivy_ManRewriteSeq( pMan, 1, 0 );
 //    Ivy_ManRewriteSeq( pMan, 1, 0 );
     pNtkAig = Abc_NtkIvyAfter( pNtk, pMan, 1, 0 );
diff --git a/src/base/abci/abcLut.c b/src/base/abci/abcLut.c
index 61b1ce78..afa76cc8 100644
--- a/src/base/abci/abcLut.c
+++ b/src/base/abci/abcLut.c
@@ -104,7 +104,7 @@ int Abc_NtkSuperChoiceLut( Abc_Ntk_t * pNtk, int nLutSize, int nCutSizeMax, int
     Abc_NtkForEachCi( pNtk, pObj, i )
         pObj->Level = 0;
 
-//Abc_NtkGetLevelNum( pNtk );
+//Abc_NtkLevel( pNtk );
  
     // start the managers
     pManScl = Abc_ManSclStart( nLutSize, nCutSizeMax, 1000 );
diff --git a/src/base/abci/abcMini.c b/src/base/abci/abcMini.c
index 014eafd3..dc90bee0 100644
--- a/src/base/abci/abcMini.c
+++ b/src/base/abci/abcMini.c
@@ -24,8 +24,8 @@
 ///                        DECLARATIONS                              ///
 ////////////////////////////////////////////////////////////////////////
 
-static Aig_Man_t * Abc_NtkToAig( Abc_Ntk_t * pNtk );
-static Abc_Ntk_t * Abc_NtkFromAig( Abc_Ntk_t * pNtkOld, Aig_Man_t * pMan );
+static Hop_Man_t * Abc_NtkToAig( Abc_Ntk_t * pNtk );
+static Abc_Ntk_t * Abc_NtkFromAig( Abc_Ntk_t * pNtkOld, Hop_Man_t * pMan );
 
 ////////////////////////////////////////////////////////////////////////
 ///                     FUNCTION DEFINITIONS                         ///
@@ -45,29 +45,29 @@ static Abc_Ntk_t * Abc_NtkFromAig( Abc_Ntk_t * pNtkOld, Aig_Man_t * pMan );
 Abc_Ntk_t * Abc_NtkMiniBalance( Abc_Ntk_t * pNtk )
 {
     Abc_Ntk_t * pNtkAig;
-    Aig_Man_t * pMan, * pTemp;
+    Hop_Man_t * pMan, * pTemp;
     assert( Abc_NtkIsStrash(pNtk) );
     // convert to the AIG manager
     pMan = Abc_NtkToAig( pNtk );
     if ( pMan == NULL )
         return NULL;
-    if ( !Aig_ManCheck( pMan ) )
+    if ( !Hop_ManCheck( pMan ) )
     {
         printf( "AIG check has failed.\n" );
-        Aig_ManStop( pMan );
+        Hop_ManStop( pMan );
         return NULL;
     }
     // perform balance
-    Aig_ManPrintStats( pMan );
-//    Aig_ManDumpBlif( pMan, "aig_temp.blif" );
-    pMan = Aig_ManBalance( pTemp = pMan, 1 );
-    Aig_ManStop( pTemp );
-    Aig_ManPrintStats( pMan );
+    Hop_ManPrintStats( pMan );
+//    Hop_ManDumpBlif( pMan, "aig_temp.blif" );
+    pMan = Hop_ManBalance( pTemp = pMan, 1 );
+    Hop_ManStop( pTemp );
+    Hop_ManPrintStats( pMan );
     // convert from the AIG manager
     pNtkAig = Abc_NtkFromAig( pNtk, pMan );
     if ( pNtkAig == NULL )
         return NULL;
-    Aig_ManStop( pMan );
+    Hop_ManStop( pMan );
     // make sure everything is okay
     if ( !Abc_NtkCheck( pNtkAig ) )
     {
@@ -89,24 +89,24 @@ Abc_Ntk_t * Abc_NtkMiniBalance( Abc_Ntk_t * pNtk )
   SeeAlso     []
 
 ***********************************************************************/
-Aig_Man_t * Abc_NtkToAig( Abc_Ntk_t * pNtk )
+Hop_Man_t * Abc_NtkToAig( Abc_Ntk_t * pNtk )
 {
-    Aig_Man_t * pMan;
+    Hop_Man_t * pMan;
     Abc_Obj_t * pObj;
     int i;
     // create the manager
-    pMan = Aig_ManStart();
+    pMan = Hop_ManStart();
     // transfer the pointers to the basic nodes
-    Abc_AigConst1(pNtk)->pCopy = (Abc_Obj_t *)Aig_ManConst1(pMan);
+    Abc_AigConst1(pNtk)->pCopy = (Abc_Obj_t *)Hop_ManConst1(pMan);
     Abc_NtkForEachCi( pNtk, pObj, i )
-        pObj->pCopy = (Abc_Obj_t *)Aig_ObjCreatePi(pMan);
+        pObj->pCopy = (Abc_Obj_t *)Hop_ObjCreatePi(pMan);
     // perform the conversion of the internal nodes (assumes DFS ordering)
     Abc_NtkForEachNode( pNtk, pObj, i )
-        pObj->pCopy = (Abc_Obj_t *)Aig_And( pMan, (Aig_Obj_t *)Abc_ObjChild0Copy(pObj), (Aig_Obj_t *)Abc_ObjChild1Copy(pObj) );
+        pObj->pCopy = (Abc_Obj_t *)Hop_And( pMan, (Hop_Obj_t *)Abc_ObjChild0Copy(pObj), (Hop_Obj_t *)Abc_ObjChild1Copy(pObj) );
     // create the POs
     Abc_NtkForEachCo( pNtk, pObj, i )
-        Aig_ObjCreatePo( pMan, (Aig_Obj_t *)Abc_ObjChild0Copy(pObj) );
-    Aig_ManCleanup( pMan );
+        Hop_ObjCreatePo( pMan, (Hop_Obj_t *)Abc_ObjChild0Copy(pObj) );
+    Hop_ManCleanup( pMan );
     return pMan;
 }
 
@@ -121,26 +121,26 @@ Aig_Man_t * Abc_NtkToAig( Abc_Ntk_t * pNtk )
   SeeAlso     []
 
 ***********************************************************************/
-Abc_Ntk_t * Abc_NtkFromAig( Abc_Ntk_t * pNtk, Aig_Man_t * pMan )
+Abc_Ntk_t * Abc_NtkFromAig( Abc_Ntk_t * pNtk, Hop_Man_t * pMan )
 {
     Vec_Ptr_t * vNodes;
     Abc_Ntk_t * pNtkNew;
-    Aig_Obj_t * pObj;
+    Hop_Obj_t * pObj;
     int i;
     // perform strashing
     pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_STRASH, ABC_FUNC_AIG );
     // transfer the pointers to the basic nodes
-    Aig_ManConst1(pMan)->pData = Abc_AigConst1(pNtkNew);
-    Aig_ManForEachPi( pMan, pObj, i )
+    Hop_ManConst1(pMan)->pData = Abc_AigConst1(pNtkNew);
+    Hop_ManForEachPi( pMan, pObj, i )
         pObj->pData = Abc_NtkCi(pNtkNew, i);
     // rebuild the AIG
-    vNodes = Aig_ManDfs( pMan );
+    vNodes = Hop_ManDfs( pMan );
     Vec_PtrForEachEntry( vNodes, pObj, i )
-        pObj->pData = Abc_AigAnd( pNtkNew->pManFunc, (Abc_Obj_t *)Aig_ObjChild0Copy(pObj), (Abc_Obj_t *)Aig_ObjChild1Copy(pObj) );
+        pObj->pData = Abc_AigAnd( pNtkNew->pManFunc, (Abc_Obj_t *)Hop_ObjChild0Copy(pObj), (Abc_Obj_t *)Hop_ObjChild1Copy(pObj) );
     Vec_PtrFree( vNodes );
     // connect the PO nodes
-    Aig_ManForEachPo( pMan, pObj, i )
-        Abc_ObjAddFanin( Abc_NtkCo(pNtkNew, i), (Abc_Obj_t *)Aig_ObjChild0Copy(pObj) );
+    Hop_ManForEachPo( pMan, pObj, i )
+        Abc_ObjAddFanin( Abc_NtkCo(pNtkNew, i), (Abc_Obj_t *)Hop_ObjChild0Copy(pObj) );
     if ( !Abc_NtkCheck( pNtkNew ) )
         fprintf( stdout, "Abc_NtkFromAig(): Network check has failed.\n" );
     return pNtkNew;
diff --git a/src/base/abci/abcNtbdd.c b/src/base/abci/abcNtbdd.c
index f99f7bce..bd035eb0 100644
--- a/src/base/abci/abcNtbdd.c
+++ b/src/base/abci/abcNtbdd.c
@@ -27,7 +27,7 @@
 static void        Abc_NtkBddToMuxesPerform( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkNew );
 static Abc_Obj_t * Abc_NodeBddToMuxes( Abc_Obj_t * pNodeOld, Abc_Ntk_t * pNtkNew );
 static Abc_Obj_t * Abc_NodeBddToMuxes_rec( DdManager * dd, DdNode * bFunc, Abc_Ntk_t * pNtkNew, st_table * tBdd2Node );
-static DdNode *    Abc_NodeGlobalBdds_rec( DdManager * dd, Abc_Obj_t * pNode, int nBddSizeMax, ProgressBar * pProgress, int * pCounter, int fVerbose );
+static DdNode *    Abc_NodeGlobalBdds_rec( DdManager * dd, Abc_Obj_t * pNode, int nBddSizeMax, int fDropInternal, ProgressBar * pProgress, int * pCounter, int fVerbose );
 
 ////////////////////////////////////////////////////////////////////////
 ///                     FUNCTION DEFINITIONS                         ///
@@ -243,85 +243,63 @@ Abc_Obj_t * Abc_NodeBddToMuxes_rec( DdManager * dd, DdNode * bFunc, Abc_Ntk_t *
   SeeAlso     []
 
 ***********************************************************************/
-DdManager * Abc_NtkGlobalBdds( Abc_Ntk_t * pNtk, int nBddSizeMax, int fLatchOnly, int fReorder, int fVerbose )
+DdManager * Abc_NtkBuildGlobalBdds( Abc_Ntk_t * pNtk, int nBddSizeMax, int fDropInternal, int fReorder, int fVerbose )
 {
     ProgressBar * pProgress;
-    Vec_Ptr_t * vFuncsGlob;
     Abc_Obj_t * pObj, * pFanin;
-    DdNode * bFunc;
+    Vec_Att_t * pAttMan;
     DdManager * dd;
+    DdNode * bFunc;
     int i, k, Counter;
 
     // remove dangling nodes
     Abc_AigCleanup( pNtk->pManFunc );
 
     // start the manager
-    assert( pNtk->pManGlob == NULL );
+    assert( Abc_NtkGlobalBdds(pNtk) == NULL );
     dd = Cudd_Init( Abc_NtkCiNum(pNtk), 0, CUDD_UNIQUE_SLOTS, CUDD_CACHE_SLOTS, 0 );
+    pAttMan = Vec_AttAlloc( 0, Abc_NtkObjNumMax(pNtk) + 1, dd, Extra_StopManager, NULL, Cudd_RecursiveDeref );
+    Vec_PtrWriteEntry( pNtk->vAttrs, VEC_ATTR_GLOBAL_BDD, pAttMan );
+
     // set reordering
     if ( fReorder )
         Cudd_AutodynEnable( dd, CUDD_REORDER_SYMM_SIFT );
 
-    // clean storage for local BDDs
-    Abc_NtkCleanCopy( pNtk );
-    // set the elementary variables
-    Abc_NtkForEachCi( pNtk, pObj, i )
-        if ( Abc_ObjFanoutNum(pObj) > 0 )
-        {
-            pObj->pCopy = (Abc_Obj_t *)dd->vars[i]; 
-            Cudd_Ref( dd->vars[i] );
-        }
     // assign the constant node BDD
     pObj = Abc_AigConst1(pNtk);
     if ( Abc_ObjFanoutNum(pObj) > 0 )
     {
-        pObj->pCopy = (Abc_Obj_t *)dd->one;   
+        Abc_ObjSetGlobalBdd( pObj, dd->one );
         Cudd_Ref( dd->one );
     }
+    // set the elementary variables
+    Abc_NtkForEachCi( pNtk, pObj, i )
+        if ( Abc_ObjFanoutNum(pObj) > 0 )
+        {
+            Abc_ObjSetGlobalBdd( pObj, dd->vars[i] );
+            Cudd_Ref( dd->vars[i] );
+        }
 
     // collect the global functions of the COs
     Counter = 0;
-    vFuncsGlob = Vec_PtrAlloc( 100 );
-    if ( fLatchOnly )
+    // construct the BDDs
+    pProgress = Extra_ProgressBarStart( stdout, Abc_NtkNodeNum(pNtk) );
+    Abc_NtkForEachCo( pNtk, pObj, i )
     {
-        // construct the BDDs
-        pProgress = Extra_ProgressBarStart( stdout, Abc_NtkNodeNum(pNtk) );
-        Abc_NtkForEachLatchInput( pNtk, pObj, i )
+        bFunc = Abc_NodeGlobalBdds_rec( dd, Abc_ObjFanin0(pObj), nBddSizeMax, fDropInternal, pProgress, &Counter, fVerbose );
+        if ( bFunc == NULL )
         {
-            bFunc = Abc_NodeGlobalBdds_rec( dd, Abc_ObjFanin0(pObj), nBddSizeMax, pProgress, &Counter, fVerbose );
-            if ( bFunc == NULL )
-            {
-                if ( fVerbose )
-                printf( "Constructing global BDDs is aborted.\n" );
-                Vec_PtrFree( vFuncsGlob );
-                Cudd_Quit( dd );
-                return NULL;
-            }
-            bFunc = Cudd_NotCond( bFunc, Abc_ObjFaninC0(pObj) );   Cudd_Ref( bFunc );
-            Vec_PtrPush( vFuncsGlob, bFunc );
-        }
-        Extra_ProgressBarStop( pProgress );
-    }
-    else
-    {
-        // construct the BDDs
-        pProgress = Extra_ProgressBarStart( stdout, Abc_NtkNodeNum(pNtk) );
-        Abc_NtkForEachCo( pNtk, pObj, i )
-        {
-            bFunc = Abc_NodeGlobalBdds_rec( dd, Abc_ObjFanin0(pObj), nBddSizeMax, pProgress, &Counter, fVerbose );
-            if ( bFunc == NULL )
-            {
-                if ( fVerbose )
-                printf( "Constructing global BDDs is aborted.\n" );
-                Vec_PtrFree( vFuncsGlob );
-                Cudd_Quit( dd );
-                return NULL;
-            }
-            bFunc = Cudd_NotCond( bFunc, Abc_ObjFaninC0(pObj) );  Cudd_Ref( bFunc ); 
-            Vec_PtrPush( vFuncsGlob, bFunc );
+            if ( fVerbose )
+            printf( "Constructing global BDDs is aborted.\n" );
+            Abc_NtkFreeGlobalBdds( pNtk, 0 );
+            Cudd_Quit( dd );
+            return NULL;
         }
-        Extra_ProgressBarStop( pProgress );
+        bFunc = Cudd_NotCond( bFunc, Abc_ObjFaninC0(pObj) );  Cudd_Ref( bFunc ); 
+        Abc_ObjSetGlobalBdd( pObj, bFunc );
     }
+    Extra_ProgressBarStop( pProgress );
+
 /*
     // derefence the intermediate BDDs
     Abc_NtkForEachNode( pNtk, pObj, i )
@@ -336,9 +314,9 @@ DdManager * Abc_NtkGlobalBdds( Abc_Ntk_t * pNtk, int nBddSizeMax, int fLatchOnly
     Abc_NtkForEachObj( pNtk, pObj, i )
     {
         if ( pObj->pCopy != NULL )
-            printf( "Abc_NtkGlobalBdds() error: Node %d has BDD assigned\n", pObj->Id );
+            printf( "Abc_NtkBuildGlobalBdds() error: Node %d has BDD assigned\n", pObj->Id );
         if ( pObj->vFanouts.nSize > 0 )
-            printf( "Abc_NtkGlobalBdds() error: Node %d has refs assigned\n", pObj->Id );
+            printf( "Abc_NtkBuildGlobalBdds() error: Node %d has refs assigned\n", pObj->Id );
     }
 */
     // reset references
@@ -353,8 +331,6 @@ DdManager * Abc_NtkGlobalBdds( Abc_Ntk_t * pNtk, int nBddSizeMax, int fLatchOnly
         Cudd_ReduceHeap( dd, CUDD_REORDER_SYMM_SIFT, 1 );
         Cudd_AutodynDisable( dd );
     }
-    pNtk->pManGlob = dd;
-    pNtk->vFuncsGlob = vFuncsGlob;
 //    Cudd_PrintInfo( dd, stdout );
     return dd;
 }
@@ -370,9 +346,10 @@ DdManager * Abc_NtkGlobalBdds( Abc_Ntk_t * pNtk, int nBddSizeMax, int fLatchOnly
   SeeAlso     []
 
 ***********************************************************************/
-DdNode * Abc_NodeGlobalBdds_rec( DdManager * dd, Abc_Obj_t * pNode, int nBddSizeMax, ProgressBar * pProgress, int * pCounter, int fVerbose )
+DdNode * Abc_NodeGlobalBdds_rec( DdManager * dd, Abc_Obj_t * pNode, int nBddSizeMax, int fDropInternal, ProgressBar * pProgress, int * pCounter, int fVerbose )
 {
     DdNode * bFunc, * bFunc0, * bFunc1, * bFuncC;
+    int fDetectMuxes = 1;
     assert( !Abc_ObjIsComplement(pNode) );
     if ( Cudd_ReadKeys(dd)-Cudd_ReadDead(dd) > (unsigned)nBddSizeMax )
     {
@@ -383,14 +360,14 @@ DdNode * Abc_NodeGlobalBdds_rec( DdManager * dd, Abc_Obj_t * pNode, int nBddSize
         return NULL;
     }
     // if the result is available return
-    if ( pNode->pCopy == NULL )
+    if ( Abc_ObjGlobalBdd(pNode) == NULL )
     {
         Abc_Obj_t * pNodeC, * pNode0, * pNode1;
         pNode0 = Abc_ObjFanin0(pNode);
         pNode1 = Abc_ObjFanin1(pNode);
         // check for the special case when it is MUX/EXOR
-//        if ( 0 )
-        if ( pNode0->pCopy == NULL && pNode1->pCopy == NULL &&
+        if ( fDetectMuxes && 
+             Abc_ObjGlobalBdd(pNode0) == NULL && Abc_ObjGlobalBdd(pNode1) == NULL &&
              Abc_ObjIsNode(pNode0) && Abc_ObjFanoutNum(pNode0) == 1 && 
              Abc_ObjIsNode(pNode1) && Abc_ObjFanoutNum(pNode1) == 1 && 
              Abc_NodeIsMuxType(pNode) )
@@ -405,15 +382,15 @@ DdNode * Abc_NodeGlobalBdds_rec( DdManager * dd, Abc_Obj_t * pNode, int nBddSize
             pNodeC->vFanouts.nSize--;
 
             // compute the result for all branches
-            bFuncC = Abc_NodeGlobalBdds_rec( dd, pNodeC, nBddSizeMax, pProgress, pCounter, fVerbose ); 
+            bFuncC = Abc_NodeGlobalBdds_rec( dd, pNodeC, nBddSizeMax, fDropInternal, pProgress, pCounter, fVerbose ); 
             if ( bFuncC == NULL )
                 return NULL;
             Cudd_Ref( bFuncC );
-            bFunc0 = Abc_NodeGlobalBdds_rec( dd, Abc_ObjRegular(pNode0), nBddSizeMax, pProgress, pCounter, fVerbose ); 
+            bFunc0 = Abc_NodeGlobalBdds_rec( dd, Abc_ObjRegular(pNode0), nBddSizeMax, fDropInternal, pProgress, pCounter, fVerbose ); 
             if ( bFunc0 == NULL )
                 return NULL;
             Cudd_Ref( bFunc0 );
-            bFunc1 = Abc_NodeGlobalBdds_rec( dd, Abc_ObjRegular(pNode1), nBddSizeMax, pProgress, pCounter, fVerbose ); 
+            bFunc1 = Abc_NodeGlobalBdds_rec( dd, Abc_ObjRegular(pNode1), nBddSizeMax, fDropInternal, pProgress, pCounter, fVerbose ); 
             if ( bFunc1 == NULL )
                 return NULL;
             Cudd_Ref( bFunc1 );
@@ -432,11 +409,11 @@ DdNode * Abc_NodeGlobalBdds_rec( DdManager * dd, Abc_Obj_t * pNode, int nBddSize
         else
         {
             // compute the result for both branches
-            bFunc0 = Abc_NodeGlobalBdds_rec( dd, Abc_ObjFanin(pNode,0), nBddSizeMax, pProgress, pCounter, fVerbose ); 
+            bFunc0 = Abc_NodeGlobalBdds_rec( dd, Abc_ObjFanin(pNode,0), nBddSizeMax, fDropInternal, pProgress, pCounter, fVerbose ); 
             if ( bFunc0 == NULL )
                 return NULL;
             Cudd_Ref( bFunc0 );
-            bFunc1 = Abc_NodeGlobalBdds_rec( dd, Abc_ObjFanin(pNode,1), nBddSizeMax, pProgress, pCounter, fVerbose ); 
+            bFunc1 = Abc_NodeGlobalBdds_rec( dd, Abc_ObjFanin(pNode,1), nBddSizeMax, fDropInternal, pProgress, pCounter, fVerbose ); 
             if ( bFunc1 == NULL )
                 return NULL;
             Cudd_Ref( bFunc1 );
@@ -450,26 +427,26 @@ DdNode * Abc_NodeGlobalBdds_rec( DdManager * dd, Abc_Obj_t * pNode, int nBddSize
             (*pCounter)++;
         }
         // set the result
-        assert( pNode->pCopy == NULL );
-        pNode->pCopy = (Abc_Obj_t *)bFunc;
+        assert( Abc_ObjGlobalBdd(pNode) == NULL );
+        Abc_ObjSetGlobalBdd( pNode, bFunc );
         // increment the progress bar
         if ( pProgress )
             Extra_ProgressBarUpdate( pProgress, *pCounter, NULL );
     }
     // prepare the return value
-    bFunc = (DdNode *)pNode->pCopy;
+    bFunc = Abc_ObjGlobalBdd(pNode);
     // dereference BDD at the node
-    if ( --pNode->vFanouts.nSize == 0 )
+    if ( --pNode->vFanouts.nSize == 0 && fDropInternal )
     {
         Cudd_Deref( bFunc );
-        pNode->pCopy = NULL;
+        Abc_ObjSetGlobalBdd( pNode, NULL );
     }
     return bFunc;
 }
 
 /**Function*************************************************************
 
-  Synopsis    [Dereferences global BDDs of the network.]
+  Synopsis    [Frees the global BDDs of the network.]
 
   Description []
                
@@ -478,16 +455,9 @@ DdNode * Abc_NodeGlobalBdds_rec( DdManager * dd, Abc_Obj_t * pNode, int nBddSize
   SeeAlso     []
 
 ***********************************************************************/
-void Abc_NtkFreeGlobalBdds( Abc_Ntk_t * pNtk )
-{
-    DdNode * bFunc;
-    int i;
-    assert( pNtk->pManGlob );
-    assert( pNtk->vFuncsGlob );
-    Vec_PtrForEachEntry( pNtk->vFuncsGlob, bFunc, i )
-        Cudd_RecursiveDeref( pNtk->pManGlob, bFunc );
-    Vec_PtrFree( pNtk->vFuncsGlob );
-    pNtk->vFuncsGlob = NULL;
+DdManager * Abc_NtkFreeGlobalBdds( Abc_Ntk_t * pNtk, int fFreeMan ) 
+{ 
+    return Abc_NtkAttrFree( pNtk, VEC_ATTR_GLOBAL_BDD, fFreeMan ); 
 }
 
 /**Function*************************************************************
@@ -503,6 +473,7 @@ void Abc_NtkFreeGlobalBdds( Abc_Ntk_t * pNtk )
 ***********************************************************************/
 double Abc_NtkSpacePercentage( Abc_Obj_t * pNode )
 {
+    /*
     Vec_Ptr_t * vNodes;
     Abc_Obj_t * pObj, * pNodeR;
     DdManager * dd;
@@ -521,7 +492,7 @@ double Abc_NtkSpacePercentage( Abc_Obj_t * pNode )
     Vec_PtrForEachEntry( vNodes, pObj, i )
         pObj->pCopy = (Abc_Obj_t *)dd->vars[i];
     // build the BDD of the cone
-    bFunc = Abc_NodeGlobalBdds_rec( dd, pNodeR, 10000000, NULL, NULL, 1 );  Cudd_Ref( bFunc );
+    bFunc = Abc_NodeGlobalBdds_rec( dd, pNodeR, 10000000, 1, NULL, NULL, 1 );  Cudd_Ref( bFunc );
     bFunc = Cudd_NotCond( bFunc, pNode != pNodeR );
     // count minterms
     Result = Cudd_CountMinterm( dd, bFunc, dd->size );
@@ -533,6 +504,8 @@ double Abc_NtkSpacePercentage( Abc_Obj_t * pNode )
     Cudd_Quit( dd );
     Vec_PtrFree( vNodes );
     return Result;
+    */
+    return 0.0;
 }
 
 
diff --git a/src/base/abci/abcPrint.c b/src/base/abci/abcPrint.c
index bdca4a8e..40bf30a6 100644
--- a/src/base/abci/abcPrint.c
+++ b/src/base/abci/abcPrint.c
@@ -113,9 +113,9 @@ void Abc_NtkPrintStats( FILE * pFile, Abc_Ntk_t * pNtk, int fFactored )
     }
 
     if ( Abc_NtkIsStrash(pNtk) )
-        fprintf( pFile, "  lev = %3d", Abc_AigGetLevelNum(pNtk) );
+        fprintf( pFile, "  lev = %3d", Abc_AigLevel(pNtk) );
     else if ( !Abc_NtkIsSeq(pNtk) )
-        fprintf( pFile, "  lev = %3d", Abc_NtkGetLevelNum(pNtk) );
+        fprintf( pFile, "  lev = %3d", Abc_NtkLevel(pNtk) );
 
     fprintf( pFile, "\n" );
     // print the statistic into a file
@@ -126,7 +126,7 @@ void Abc_NtkPrintStats( FILE * pFile, Abc_Ntk_t * pNtk, int fFactored )
         fprintf( pTable, "%s ",  pNtk->pName );
         fprintf( pTable, "%d ", Abc_NtkPiNum(pNtk) );
         fprintf( pTable, "%d ", Abc_NtkNodeNum(pNtk) );
-        fprintf( pTable, "%d ", Abc_AigGetLevelNum(pNtk) );
+        fprintf( pTable, "%d ", Abc_AigLevel(pNtk) );
         fprintf( pTable, "\n" );
         fclose( pTable );
     }
@@ -150,7 +150,7 @@ void Abc_NtkPrintStats( FILE * pFile, Abc_Ntk_t * pNtk, int fFactored )
         FILE * pTable;
         pTable = fopen( "fpga/fpga_stats.txt", "a+" );
         fprintf( pTable, "%s ",  pNtk->pName );
-        fprintf( pTable, "%d ", Abc_NtkGetLevelNum(pNtk) );
+        fprintf( pTable, "%d ", Abc_NtkLevel(pNtk) );
         fprintf( pTable, "%d ", Abc_NtkNodeNum(pNtk) );
         fprintf( pTable, "%.2f ", (float)(s_MappingMem)/(float)(1<<20) );
         fprintf( pTable, "%.2f", (float)(s_MappingTime)/(float)(CLOCKS_PER_SEC) );
@@ -159,23 +159,41 @@ void Abc_NtkPrintStats( FILE * pFile, Abc_Ntk_t * pNtk, int fFactored )
     }
 */
 
-/*
+
     // print the statistic into a file
     {
         static int Counter = 0;
         extern int timeRetime;
         FILE * pTable;
         Counter++;
-        pTable = fopen( "sap/stats_retime.txt", "a+" );
+        pTable = fopen( "a/ret__stats.txt", "a+" );
         fprintf( pTable, "%s ", pNtk->pName );
         fprintf( pTable, "%d ", Abc_NtkNodeNum(pNtk) );
         fprintf( pTable, "%d ", Abc_NtkLatchNum(pNtk) );
-        fprintf( pTable, "%d ", Abc_NtkGetLevelNum(pNtk) );
+        fprintf( pTable, "%d ", Abc_NtkLevel(pNtk) );
         fprintf( pTable, "%.2f ", (float)(timeRetime)/(float)(CLOCKS_PER_SEC) );
         if ( Counter % 4 == 0 )
             fprintf( pTable, "\n" );
         fclose( pTable );
     }
+
+/*
+    // print the statistic into a file
+    {
+        static int Counter = 0;
+        extern int timeRetime;
+        FILE * pTable;
+        Counter++;
+        pTable = fopen( "d/stats.txt", "a+" );
+        fprintf( pTable, "%s ", pNtk->pName );
+//        fprintf( pTable, "%d ", Abc_NtkPiNum(pNtk) );
+//        fprintf( pTable, "%d ", Abc_NtkPoNum(pNtk) );
+//        fprintf( pTable, "%d ", Abc_NtkLatchNum(pNtk) );
+        fprintf( pTable, "%d ", Abc_NtkNodeNum(pNtk) );
+        fprintf( pTable, "%.2f ", (float)(timeRetime)/(float)(CLOCKS_PER_SEC) );
+        fprintf( pTable, "\n" );
+        fclose( pTable );
+    }
 */
 
 /*
@@ -214,7 +232,8 @@ void Abc_NtkPrintIo( FILE * pFile, Abc_Ntk_t * pNtk )
 
     fprintf( pFile, "Latches (%d):  ", Abc_NtkLatchNum(pNtk) );  
     Abc_NtkForEachLatch( pNtk, pObj, i )
-        fprintf( pFile, " %s", Abc_ObjName(pObj) );
+        fprintf( pFile, " %s(%s=%s)", Abc_ObjName(pObj), 
+            Abc_ObjName(Abc_ObjFanout0(pObj)), Abc_ObjName(Abc_ObjFanin0(pObj)) );
     fprintf( pFile, "\n" );   
 }
 
@@ -500,7 +519,7 @@ void Abc_NtkPrintLevel( FILE * pFile, Abc_Ntk_t * pNtk, int fProfile, int fListN
     if ( fListNodes )
     {
         int nLevels;
-        nLevels = Abc_NtkGetLevelNum(pNtk);
+        nLevels = Abc_NtkLevel(pNtk);
         printf( "Nodes by level:\n" );
         for ( i = 0; i <= nLevels; i++ )
         {
@@ -553,7 +572,7 @@ void Abc_NtkPrintLevel( FILE * pFile, Abc_Ntk_t * pNtk, int fProfile, int fListN
         int nOutsSum, nOutsTotal;
 
         if ( !Abc_NtkIsStrash(pNtk) )
-            Abc_NtkGetLevelNum(pNtk);
+            Abc_NtkLevel(pNtk);
 
         LevelMax = 0;
         Abc_NtkForEachCo( pNtk, pNode, i )
@@ -840,41 +859,6 @@ void Abc_NtkPrintStrSupports( Abc_Ntk_t * pNtk )
 
 /**Function*************************************************************
 
-  Synopsis    [Prints information about the clock skew schedule.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Abc_NtkPrintSkews( FILE * pFile, Abc_Ntk_t * pNtk, int fPrintAll ) {
-
-  Abc_Obj_t * pObj;
-  int         i;
-  int         nNonZero = 0;
-  float       skew, sum = 0.0, avg;
-
-  if (fPrintAll) fprintf( pFile, "Full Clock Skew Schedule:\n\tGlobal Skew = %.2f\n", pNtk->globalSkew );
-
-  Abc_NtkForEachLatch( pNtk, pObj, i ) {
-    skew = Abc_NtkGetLatSkew( pNtk, i );
-    if ( skew != 0.0 ) {
-      nNonZero++;
-      sum += ABS( skew );
-    }
-    if (fPrintAll) fprintf( pFile, "\tLatch %d (Id = %d) \t Endpoint Skew = %.2f\n", i, pObj->Id, skew);
-  }
-
-  avg = sum / Abc_NtkLatchNum( pNtk );
- 
-  fprintf( pFile, "Endpoint Skews : Total |Skew| = %.2f\t Avg |Skew| = %.2f\t Non-Zero Skews = %d\n", 
-           sum, avg, nNonZero );
-}
-
-/**Function*************************************************************
-
   Synopsis    [Prints information about the object.]
 
   Description []
@@ -942,6 +926,12 @@ void Abc_ObjPrint( FILE * pFile, Abc_Obj_t * pObj )
     Abc_ObjForEachFanin( pObj, pFanin, i )
         fprintf( pFile, "%d ", pFanin->Id );
     fprintf( pFile, ") " );
+/*
+    fprintf( pFile, " Fanouts ( " );
+    Abc_ObjForEachFanout( pObj, pFanin, i )
+        fprintf( pFile, "%d(%c) ", pFanin->Id, Abc_NodeIsTravIdCurrent(pFanin)? '+' : '-' );
+    fprintf( pFile, ") " );
+*/
     // print the logic function
     if ( Abc_ObjIsNode(pObj) && Abc_NtkIsSopLogic(pObj->pNtk) )
         fprintf( pFile, " %s", pObj->pData );
diff --git a/src/base/abci/abcProve.c b/src/base/abci/abcProve.c
index c9e5bfd7..fcd44d30 100644
--- a/src/base/abci/abcProve.c
+++ b/src/base/abci/abcProve.c
@@ -310,7 +310,7 @@ void Abc_NtkMiterPrint( Abc_Ntk_t * pNtk, char * pString, int clk, int fVerbose
     if ( !fVerbose )
         return;
     printf( "Nodes = %7d.  Levels = %4d.  ", Abc_NtkNodeNum(pNtk), 
-        Abc_NtkIsStrash(pNtk)? Abc_AigGetLevelNum(pNtk) : Abc_NtkGetLevelNum(pNtk) );
+        Abc_NtkIsStrash(pNtk)? Abc_AigLevel(pNtk) : Abc_NtkLevel(pNtk) );
     PRT( pString, clock() - clk );
 }
 
diff --git a/src/base/abci/abcRefactor.c b/src/base/abci/abcRefactor.c
index 3d301cd6..0328d8d3 100644
--- a/src/base/abci/abcRefactor.c
+++ b/src/base/abci/abcRefactor.c
@@ -156,7 +156,7 @@ pManRef->timeTotal = clock() - clkStart;
     if ( fUpdateLevel )
         Abc_NtkStopReverseLevels( pNtk );
     else
-        Abc_NtkGetLevelNum( pNtk );
+        Abc_NtkLevel( pNtk );
     // check
     if ( !Abc_NtkCheck( pNtk ) )
     {
diff --git a/src/base/abci/abcRestruct.c b/src/base/abci/abcRestruct.c
index 9dc84999..2d4f50fb 100644
--- a/src/base/abci/abcRestruct.c
+++ b/src/base/abci/abcRestruct.c
@@ -183,7 +183,7 @@ pManRst->timeTotal = clock() - clkStart;
     if ( fUpdateLevel )
         Abc_NtkStopReverseLevels( pNtk );
     else
-        Abc_NtkGetLevelNum( pNtk );
+        Abc_NtkLevel( pNtk );
     // check
     if ( !Abc_NtkCheck( pNtk ) )
     {
diff --git a/src/base/abci/abcResub.c b/src/base/abci/abcResub.c
index 9fcc6979..19e6c50a 100644
--- a/src/base/abci/abcResub.c
+++ b/src/base/abci/abcResub.c
@@ -232,7 +232,7 @@ pManRes->timeTotal = clock() - clkStart;
     if ( fUpdateLevel )
         Abc_NtkStopReverseLevels( pNtk );
     else
-        Abc_NtkGetLevelNum( pNtk );
+        Abc_NtkLevel( pNtk );
     // check
     if ( !Abc_NtkCheck( pNtk ) )
     {
diff --git a/src/base/abci/abcRewrite.c b/src/base/abci/abcRewrite.c
index 2af10271..151b5256 100644
--- a/src/base/abci/abcRewrite.c
+++ b/src/base/abci/abcRewrite.c
@@ -158,7 +158,7 @@ Rwr_ManAddTimeTotal( pManRwr, clock() - clkStart );
     if ( fUpdateLevel )
         Abc_NtkStopReverseLevels( pNtk );
     else
-        Abc_NtkGetLevelNum( pNtk );
+        Abc_NtkLevel( pNtk );
     // check
     if ( !Abc_NtkCheck( pNtk ) )
     {
diff --git a/src/base/abci/abcRr.c b/src/base/abci/abcRr.c
index 63beac6c..b9fab415 100644
--- a/src/base/abci/abcRr.c
+++ b/src/base/abci/abcRr.c
@@ -104,7 +104,7 @@ int Abc_NtkRR( Abc_Ntk_t * pNtk, int nFaninLevels, int nFanoutLevels, int fUseFa
     p->nFaninLevels  = nFaninLevels;
     p->nFanoutLevels = nFanoutLevels;
     p->nNodesOld     = Abc_NtkNodeNum(pNtk);
-    p->nLevelsOld    = Abc_AigGetLevelNum(pNtk);
+    p->nLevelsOld    = Abc_AigLevel(pNtk);
     // remember latch values
 //    Abc_NtkForEachLatch( pNtk, pNode, i )
 //        pNode->pNext = pNode->pData;
@@ -220,7 +220,7 @@ int Abc_NtkRR( Abc_Ntk_t * pNtk, int nFaninLevels, int nFanoutLevels, int fUseFa
 //        pNode->pData = pNode->pNext, pNode->pNext = NULL;
     // put the nodes into the DFS order and reassign their IDs
     Abc_NtkReassignIds( pNtk );
-    Abc_NtkGetLevelNum( pNtk );
+    Abc_NtkLevel( pNtk );
     // check
     if ( !Abc_NtkCheck( pNtk ) )
     {
@@ -298,7 +298,7 @@ void Abc_RRManPrintStats( Abc_RRMan_t * p )
     printf( "Edges tried     = %6d.\n", p->nEdgesTried );
     printf( "Edges removed   = %6d. (%5.2f %%)\n", p->nEdgesRemoved, 100.0*p->nEdgesRemoved/p->nEdgesTried );
     printf( "Node gain       = %6d. (%5.2f %%)\n", p->nNodesOld  - Abc_NtkNodeNum(p->pNtk), Ratio );
-    printf( "Level gain      = %6d.\n", p->nLevelsOld - Abc_AigGetLevelNum(p->pNtk) );
+    printf( "Level gain      = %6d.\n", p->nLevelsOld - Abc_AigLevel(p->pNtk) );
     PRT( "Windowing      ", p->timeWindow );
     PRT( "Miter          ", p->timeMiter );
     PRT( "    Construct  ", p->timeMiter - p->timeProve );
diff --git a/src/base/abci/abcSat.c b/src/base/abci/abcSat.c
index 8d5dd2a7..55498288 100644
--- a/src/base/abci/abcSat.c
+++ b/src/base/abci/abcSat.c
@@ -458,7 +458,7 @@ int Abc_NtkMiterSatCreateInt( solver * pSat, Abc_Ntk_t * pNtk, int fJFront )
     int i, k, fUseMuxes = 1;
     int clk1 = clock(), clk;
     int fOrderCiVarsFirst = 0;
-    int nLevelsMax = Abc_AigGetLevelNum(pNtk);
+    int nLevelsMax = Abc_AigLevel(pNtk);
     int RetValue = 0;
 
     assert( Abc_NtkIsStrash(pNtk) );
diff --git a/src/base/abci/abcStrash.c b/src/base/abci/abcStrash.c
index e8dc9793..a3719b10 100644
--- a/src/base/abci/abcStrash.c
+++ b/src/base/abci/abcStrash.c
@@ -1,6 +1,6 @@
 /**CFile****************************************************************
 
-  FileName    [aigStrash.c]
+  FileName    [abcStrash.c]
 
   SystemName  [ABC: Logic synthesis and verification system.]
 
@@ -14,7 +14,7 @@
 
   Date        [Ver. 1.0. Started - June 20, 2005.]
 
-  Revision    [$Id: aigStrash.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
+  Revision    [$Id: abcStrash.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
 
 ***********************************************************************/
 
@@ -46,10 +46,12 @@ static void Abc_NtkStrashPerform( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkNew, bool fA
 ***********************************************************************/
 Abc_Ntk_t * Abc_NtkRestrash( Abc_Ntk_t * pNtk, bool fCleanup )
 {
+    extern int timeRetime;
     Abc_Ntk_t * pNtkAig;
     Abc_Obj_t * pObj;
-    int i, nNodes;
+    int i, nNodes, RetValue;
     assert( Abc_NtkIsStrash(pNtk) );
+//timeRetime = clock();
     // print warning about choice nodes
     if ( Abc_NtkGetChoiceNum( pNtk ) )
         printf( "Warning: The choice nodes in the original AIG are removed by strashing.\n" );
@@ -58,7 +60,7 @@ Abc_Ntk_t * Abc_NtkRestrash( Abc_Ntk_t * pNtk, bool fCleanup )
     // restrash the nodes (assuming a topological order of the old network)
     Abc_NtkForEachNode( pNtk, pObj, i )
         pObj->pCopy = Abc_AigAnd( pNtkAig->pManFunc, Abc_ObjChild0Copy(pObj), Abc_ObjChild1Copy(pObj) );
-    // finalize the network
+    //l finalize the network
     Abc_NtkFinalize( pNtk, pNtkAig );
     // print warning about self-feed latches
 //    if ( Abc_NtkCountSelfFeedLatches(pNtkAig) )
@@ -76,6 +78,9 @@ Abc_Ntk_t * Abc_NtkRestrash( Abc_Ntk_t * pNtk, bool fCleanup )
         Abc_NtkDelete( pNtkAig );
         return NULL;
     }
+//timeRetime = clock() - timeRetime;
+    if ( RetValue = Abc_NtkRemoveSelfFeedLatches(pNtkAig) )
+        printf( "Modified %d self-feeding latches. The result will not verify.\n", RetValue );
     return pNtkAig;
 
 }
@@ -106,7 +111,7 @@ Abc_Ntk_t * Abc_NtkStrash( Abc_Ntk_t * pNtk, bool fAllNodes, bool fCleanup )
         return NULL;
     }
     // perform strashing
-    Abc_NtkCleanCopy( pNtk );
+//    Abc_NtkCleanCopy( pNtk );
     pNtkAig = Abc_NtkStartFrom( pNtk, ABC_NTK_STRASH, ABC_FUNC_AIG );
     Abc_NtkStrashPerform( pNtk, pNtkAig, fAllNodes );
     Abc_NtkFinalize( pNtk, pNtkAig );
@@ -205,13 +210,17 @@ int Abc_NtkAppend( Abc_Ntk_t * pNtk1, Abc_Ntk_t * pNtk2, int fAddPos )
 ***********************************************************************/
 void Abc_NtkStrashPerform( Abc_Ntk_t * pNtkOld, Abc_Ntk_t * pNtkNew, bool fAllNodes )
 {
+    extern Vec_Ptr_t * Abc_NtkDfsIter( Abc_Ntk_t * pNtk, int fCollectAll );
     ProgressBar * pProgress;
     Vec_Ptr_t * vNodes;
     Abc_Obj_t * pNodeOld;
-    int i;
+    int i, clk = clock();
     assert( Abc_NtkIsLogic(pNtkOld) );
     assert( Abc_NtkIsStrash(pNtkNew) );
-    vNodes = Abc_NtkDfs( pNtkOld, fAllNodes );
+//    vNodes = Abc_NtkDfs( pNtkOld, fAllNodes );
+    vNodes = Abc_NtkDfsIter( pNtkOld, fAllNodes );
+//printf( "Nodes = %d. ", Vec_PtrSize(vNodes) );
+//PRT( "Time", clock() - clk );
     pProgress = Extra_ProgressBarStart( stdout, vNodes->nSize );
     Vec_PtrForEachEntry( vNodes, pNodeOld, i )
     {
@@ -233,16 +242,16 @@ void Abc_NtkStrashPerform( Abc_Ntk_t * pNtkOld, Abc_Ntk_t * pNtkNew, bool fAllNo
   SeeAlso     []
 
 ***********************************************************************/
-void Abc_NodeStrash_rec( Abc_Aig_t * pMan, Aig_Obj_t * pObj )
+void Abc_NodeStrash_rec( Abc_Aig_t * pMan, Hop_Obj_t * pObj )
 {
-    assert( !Aig_IsComplement(pObj) );
-    if ( !Aig_ObjIsNode(pObj) || Aig_ObjIsMarkA(pObj) )
+    assert( !Hop_IsComplement(pObj) );
+    if ( !Hop_ObjIsNode(pObj) || Hop_ObjIsMarkA(pObj) )
         return;
-    Abc_NodeStrash_rec( pMan, Aig_ObjFanin0(pObj) ); 
-    Abc_NodeStrash_rec( pMan, Aig_ObjFanin1(pObj) );
-    pObj->pData = Abc_AigAnd( pMan, (Abc_Obj_t *)Aig_ObjChild0Copy(pObj), (Abc_Obj_t *)Aig_ObjChild1Copy(pObj) );
-    assert( !Aig_ObjIsMarkA(pObj) ); // loop detection
-    Aig_ObjSetMarkA( pObj );
+    Abc_NodeStrash_rec( pMan, Hop_ObjFanin0(pObj) ); 
+    Abc_NodeStrash_rec( pMan, Hop_ObjFanin1(pObj) );
+    pObj->pData = Abc_AigAnd( pMan, (Abc_Obj_t *)Hop_ObjChild0Copy(pObj), (Abc_Obj_t *)Hop_ObjChild1Copy(pObj) );
+    assert( !Hop_ObjIsMarkA(pObj) ); // loop detection
+    Hop_ObjSetMarkA( pObj );
 }
 
 /**Function*************************************************************
@@ -258,8 +267,8 @@ void Abc_NodeStrash_rec( Abc_Aig_t * pMan, Aig_Obj_t * pObj )
 ***********************************************************************/
 Abc_Obj_t * Abc_NodeStrash( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pNodeOld )
 {
-    Aig_Man_t * pMan;
-    Aig_Obj_t * pRoot;
+    Hop_Man_t * pMan;
+    Hop_Obj_t * pRoot;
     Abc_Obj_t * pFanin;
     int i;
     assert( Abc_ObjIsNode(pNodeOld) );
@@ -269,15 +278,15 @@ Abc_Obj_t * Abc_NodeStrash( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pNodeOld )
     pRoot = pNodeOld->pData;
     // check the constant case
     if ( Abc_NodeIsConst(pNodeOld) )
-        return Abc_ObjNotCond( Abc_AigConst1(pNtkNew), Aig_IsComplement(pRoot) );
+        return Abc_ObjNotCond( Abc_AigConst1(pNtkNew), Hop_IsComplement(pRoot) );
     // set elementary variables
     Abc_ObjForEachFanin( pNodeOld, pFanin, i )
-        Aig_IthVar(pMan, i)->pData = pFanin->pCopy;
+        Hop_IthVar(pMan, i)->pData = pFanin->pCopy;
     // strash the AIG of this node
-    Abc_NodeStrash_rec( pNtkNew->pManFunc, Aig_Regular(pRoot) );
-    Aig_ConeUnmark_rec( Aig_Regular(pRoot) );
+    Abc_NodeStrash_rec( pNtkNew->pManFunc, Hop_Regular(pRoot) );
+    Hop_ConeUnmark_rec( Hop_Regular(pRoot) );
     // return the final node
-    return Abc_ObjNotCond( Aig_Regular(pRoot)->pData, Aig_IsComplement(pRoot) );
+    return Abc_ObjNotCond( Hop_Regular(pRoot)->pData, Hop_IsComplement(pRoot) );
 }
 
 
@@ -328,7 +337,7 @@ Abc_Ntk_t * Abc_NtkTopmost( Abc_Ntk_t * pNtk, int nLevels )
     assert( Abc_NtkIsStrash(pNtk) );
     assert( Abc_NtkCoNum(pNtk) == 1 );
     // get the cutoff level
-    LevelCut = ABC_MAX( 0, Abc_AigGetLevelNum(pNtk) - nLevels );
+    LevelCut = ABC_MAX( 0, Abc_AigLevel(pNtk) - nLevels );
     // start the network
     pNtkNew = Abc_NtkAlloc( ABC_NTK_STRASH, ABC_FUNC_AIG, 1 );
     pNtkNew->pName = Extra_UtilStrsav(pNtk->pName);
diff --git a/src/base/abci/abcSweep.c b/src/base/abci/abcSweep.c
index db926d17..1b63b23c 100644
--- a/src/base/abci/abcSweep.c
+++ b/src/base/abci/abcSweep.c
@@ -79,7 +79,7 @@ bool Abc_NtkFraigSweep( Abc_Ntk_t * pNtk, int fUseInv, int fExdc, int fVerbose )
     if ( fUseTrick )
     {
         extern void * Abc_FrameReadLibGen(); 
-        Aig_ManStop( pNtk->pManFunc );
+        Hop_ManStop( pNtk->pManFunc );
         pNtk->pManFunc = Abc_FrameReadLibGen();
         pNtk->ntkFunc = ABC_FUNC_MAP;
         Abc_NtkForEachNode( pNtk, pObj, i )
@@ -269,7 +269,7 @@ void Abc_NtkFraigTransform( Abc_Ntk_t * pNtk, stmm_table * tEquiv, int fUseInv,
     if ( stmm_count(tEquiv) == 0 )
         return;
     // assign levels to the nodes of the network
-    Abc_NtkGetLevelNum( pNtk );
+    Abc_NtkLevel( pNtk );
     // merge nodes in the classes
     if ( Abc_NtkHasMapping( pNtk ) )
     {
@@ -897,7 +897,7 @@ int Abc_NtkReplaceAutonomousLogic( Abc_Ntk_t * pNtk )
   SeeAlso     []
 
 ***********************************************************************/
-int Abc_NtkCleanupSeq( Abc_Ntk_t * pNtk, int fVerbose )
+int Abc_NtkCleanupSeq( Abc_Ntk_t * pNtk, int fLatchSweep, int fAutoSweep, int fVerbose )
 {
     Vec_Ptr_t * vNodes;
     int Counter;
@@ -910,20 +910,26 @@ int Abc_NtkCleanupSeq( Abc_Ntk_t * pNtk, int fVerbose )
     if ( fVerbose )
         printf( "Cleanup removed %4d dangling objects.\n", Counter );
     // check if some of the latches can be removed
-    Counter = Abc_NtkLatchSweep( pNtk );
-    if ( fVerbose )
-        printf( "Cleanup removed %4d redundant latches.\n", Counter );
+    if ( fLatchSweep )
+    {
+        Counter = Abc_NtkLatchSweep( pNtk );
+        if ( fVerbose )
+            printf( "Cleanup removed %4d redundant latches.\n", Counter );
+    }
     // detect the autonomous components
-    vNodes = Abc_NtkDfsSeqReverse( pNtk );
-    Vec_PtrFree( vNodes );
-    // replace them by PIs
-    Counter = Abc_NtkReplaceAutonomousLogic( pNtk );
-    if ( fVerbose )
-        printf( "Cleanup added   %4d additional PIs.\n", Counter );
-    // remove the non-marked nodes
-    Counter = Abc_NodeRemoveNonCurrentObjects( pNtk );
-    if ( fVerbose )
-        printf( "Cleanup removed %4d autonomous objects.\n", Counter );
+    if ( fAutoSweep )
+    {
+        vNodes = Abc_NtkDfsSeqReverse( pNtk );
+        Vec_PtrFree( vNodes );
+        // replace them by PIs
+        Counter = Abc_NtkReplaceAutonomousLogic( pNtk );
+        if ( fVerbose )
+            printf( "Cleanup added   %4d additional PIs.\n", Counter );
+        // remove the non-marked nodes
+        Counter = Abc_NodeRemoveNonCurrentObjects( pNtk );
+        if ( fVerbose )
+            printf( "Cleanup removed %4d autonomous objects.\n", Counter );
+    }
     // check
     if ( !Abc_NtkCheck( pNtk ) )
         printf( "Abc_NtkCleanupSeq: The network check has failed.\n" );
diff --git a/src/base/abci/abcSymm.c b/src/base/abci/abcSymm.c
index fad3bd92..d3fcb7c9 100644
--- a/src/base/abci/abcSymm.c
+++ b/src/base/abci/abcSymm.c
@@ -88,7 +88,7 @@ void Abc_NtkSymmetriesUsingBdds( Abc_Ntk_t * pNtk, int fNaive, int fVerbose )
 
     // compute the global functions
 clk = clock();
-    dd = Abc_NtkGlobalBdds( pNtk, 10000000, 0, 1, fVerbose );
+    dd = Abc_NtkBuildGlobalBdds( pNtk, 10000000, 1, 1, fVerbose );
     Cudd_AutodynDisable( dd );
     Cudd_zddVarsFromBddVars( dd, 2 );
 clkBdd = clock() - clk;
@@ -97,9 +97,10 @@ clk = clock();
     Ntk_NetworkSymmsBdd( dd, pNtk, fNaive, fVerbose );
 clkSym = clock() - clk;
     // undo the global functions
-    Abc_NtkFreeGlobalBdds( pNtk );
-    Extra_StopManager( dd );
-    pNtk->pManGlob = NULL;
+//    Abc_NtkFreeGlobalBdds( pNtk );
+//    Extra_StopManager( dd );
+//    pNtk->pManGlob = NULL;
+    Abc_NtkFreeGlobalBdds( pNtk, 1 );
 
 PRT( "Constructing BDDs", clkBdd );
 PRT( "Computing symms  ", clkSym );
@@ -129,7 +130,8 @@ void Ntk_NetworkSymmsBdd( DdManager * dd, Abc_Ntk_t * pNtk, int fNaive, int fVer
     // compute symmetry info for each PO
     Abc_NtkForEachCo( pNtk, pNode, i )
     {
-        bFunc = pNtk->vFuncsGlob->pArray[i];
+//      bFunc = pNtk->vFuncsGlob->pArray[i];
+        bFunc = Abc_ObjGlobalBdd( pNode );
         nSupps += Cudd_SupportSize( dd, bFunc );
         if ( Cudd_IsConstant(bFunc) )
             continue;
diff --git a/src/base/abci/abcTiming.c b/src/base/abci/abcTiming.c
index af06436f..93fa3fa5 100644
--- a/src/base/abci/abcTiming.c
+++ b/src/base/abci/abcTiming.c
@@ -648,8 +648,8 @@ void Abc_NtkStartReverseLevels( Abc_Ntk_t * pNtk )
     int i, k, nLevelsCur;
 //    assert( Abc_NtkIsStrash(pNtk) );
     // remember the maximum number of direct levels
-//    pNtk->LevelMax = Abc_AigGetLevelNum(pNtk);
-    pNtk->LevelMax = Abc_NtkGetLevelNum(pNtk);
+//    pNtk->LevelMax = Abc_AigLevel(pNtk);
+    pNtk->LevelMax = Abc_NtkLevel(pNtk);
     // start the reverse levels
     pNtk->vLevelsR = Vec_IntAlloc( 0 );
     Vec_IntFill( pNtk->vLevelsR, Abc_NtkObjNumMax(pNtk), 0 );
diff --git a/src/base/abci/abcUnate.c b/src/base/abci/abcUnate.c
index 48b7eb92..8fd2a12f 100644
--- a/src/base/abci/abcUnate.c
+++ b/src/base/abci/abcUnate.c
@@ -66,20 +66,22 @@ void Abc_NtkPrintUnateBdd( Abc_Ntk_t * pNtk, int fUseNaive, int fVerbose )
     Abc_Obj_t * pNode;
     Extra_UnateInfo_t * p;
     DdManager * dd;         // the BDD manager used to hold shared BDDs
-    DdNode ** pbGlobal;     // temporary storage for global BDDs
+//    DdNode ** pbGlobal;     // temporary storage for global BDDs
     int TotalSupps = 0;
     int TotalUnate = 0;
     int i, clk = clock();
     int clkBdd, clkUnate;
 
     // compute the global BDDs
-    if ( Abc_NtkGlobalBdds(pNtk, 10000000, 0, 1, fVerbose) == NULL )
+    dd = Abc_NtkBuildGlobalBdds(pNtk, 10000000, 1, 1, fVerbose);
+    if ( dd == NULL )
         return;
 clkBdd = clock() - clk;
 
     // get information about the network
-    dd       = pNtk->pManGlob;
-    pbGlobal = (DdNode **)Vec_PtrArray( pNtk->vFuncsGlob );
+//    dd       = pNtk->pManGlob;
+//    dd       = Abc_NtkGlobalBddMan( pNtk );
+//    pbGlobal = (DdNode **)Vec_PtrArray( pNtk->vFuncsGlob );
 
     // print the size of the BDDs
     printf( "The shared BDD size is %d nodes.\n", Cudd_ReadKeys(dd) - Cudd_ReadDead(dd) );
@@ -89,7 +91,8 @@ clkBdd = clock() - clk;
     {
         Abc_NtkForEachCo( pNtk, pNode, i )
         {
-            p = Extra_UnateComputeSlow( dd, pbGlobal[i] );
+//            p = Extra_UnateComputeSlow( dd, pbGlobal[i] );
+            p = Extra_UnateComputeSlow( dd, Abc_ObjGlobalBdd(pNode) );
             if ( fVerbose )
                 Extra_UnateInfoPrint( p );
             TotalSupps += p->nVars;
@@ -104,7 +107,8 @@ clkBdd = clock() - clk;
         Cudd_zddVarsFromBddVars( dd, 2 );
         Abc_NtkForEachCo( pNtk, pNode, i )
         {
-            p = Extra_UnateComputeFast( dd, pbGlobal[i] );
+//            p = Extra_UnateComputeFast( dd, pbGlobal[i] );
+            p = Extra_UnateComputeFast( dd, Abc_ObjGlobalBdd(pNode) );
             if ( fVerbose )
                 Extra_UnateInfoPrint( p );
             TotalSupps += p->nVars;
@@ -122,10 +126,11 @@ clkUnate = clock() - clk - clkBdd;
     PRT( "Total    ", clock() - clk );
 
     // deref the PO functions
-    Abc_NtkFreeGlobalBdds( pNtk );
+//    Abc_NtkFreeGlobalBdds( pNtk );
     // stop the global BDD manager
-    Extra_StopManager( pNtk->pManGlob );
-    pNtk->pManGlob = NULL;
+//    Extra_StopManager( pNtk->pManGlob );
+//    pNtk->pManGlob = NULL;
+    Abc_NtkFreeGlobalBdds( pNtk, 1 );
 }
 
 /**Function*************************************************************
diff --git a/src/base/abci/abcUnreach.c b/src/base/abci/abcUnreach.c
index e4873986..acd63771 100644
--- a/src/base/abci/abcUnreach.c
+++ b/src/base/abci/abcUnreach.c
@@ -58,7 +58,7 @@ int Abc_NtkExtractSequentialDcs( Abc_Ntk_t * pNtk, bool fVerbose )
     }
 
     // compute the global BDDs of the latches
-    dd = Abc_NtkGlobalBdds( pNtk, 10000000, 1, 1, fVerbose );    
+    dd = Abc_NtkBuildGlobalBdds( pNtk, 10000000, 1, 1, fVerbose );    
     if ( dd == NULL )
         return 0;
     if ( fVerbose )
@@ -92,7 +92,7 @@ int Abc_NtkExtractSequentialDcs( Abc_Ntk_t * pNtk, bool fVerbose )
     pNtk->pExdc = Abc_NtkConstructExdc( dd, pNtk, bUnreach );
     Cudd_RecursiveDeref( dd, bUnreach );
     Extra_StopManager( dd );
-    pNtk->pManGlob = NULL;
+//    pNtk->pManGlob = NULL;
 
     // make sure that everything is okay
     if ( pNtk->pExdc && !Abc_NtkCheck( pNtk->pExdc ) )
@@ -137,13 +137,15 @@ DdNode * Abc_NtkTransitionRelation( DdManager * dd, Abc_Ntk_t * pNtk, int fVerbo
     Abc_NtkForEachLatch( pNtk, pNode, i )
     {
         bVar  = Cudd_bddIthVar( dd, Abc_NtkCiNum(pNtk) + i );
-        bProd = Cudd_bddXnor( dd, bVar, pNtk->vFuncsGlob->pArray[i] );  Cudd_Ref( bProd );
+//        bProd = Cudd_bddXnor( dd, bVar, pNtk->vFuncsGlob->pArray[i] );  Cudd_Ref( bProd );
+        bProd = Cudd_bddXnor( dd, bVar, Abc_ObjGlobalBdd(Abc_ObjFanin0(pNode)) );  Cudd_Ref( bProd );
         bRel  = Cudd_bddAnd( dd, bTemp = bRel, bProd );                 Cudd_Ref( bRel );
         Cudd_RecursiveDeref( dd, bTemp ); 
         Cudd_RecursiveDeref( dd, bProd ); 
     }
     // free the global BDDs
-    Abc_NtkFreeGlobalBdds( pNtk );
+//    Abc_NtkFreeGlobalBdds( pNtk );
+    Abc_NtkFreeGlobalBdds( pNtk, 0 );
 
     // quantify the PI variables
     bInputs = Extra_bddComputeRangeCube( dd, 0, Abc_NtkPiNum(pNtk) );    Cudd_Ref( bInputs );
diff --git a/src/base/abci/module.make b/src/base/abci/module.make
index 7db26629..04ed07a7 100644
--- a/src/base/abci/module.make
+++ b/src/base/abci/module.make
@@ -15,6 +15,7 @@ SRC +=    src/base/abci/abc.c \
     src/base/abci/abcFraig.c \
         src/base/abci/abcFxu.c \
         src/base/abci/abcGen.c \
+    src/base/abci/abcIf.c \
         src/base/abci/abcIvy.c \
     src/base/abci/abcLut.c \
     src/base/abci/abcMap.c \
@@ -22,7 +23,6 @@ SRC +=    src/base/abci/abc.c \
     src/base/abci/abcMiter.c \
     src/base/abci/abcNtbdd.c \
     src/base/abci/abcOrder.c \
-    src/base/abci/abcPga.c \
     src/base/abci/abcPrint.c \
     src/base/abci/abcProve.c \
     src/base/abci/abcReconv.c \
diff --git a/src/base/io/io.c b/src/base/io/io.c
index 7a661664..b1ea03c1 100644
--- a/src/base/io/io.c
+++ b/src/base/io/io.c
@@ -1339,12 +1339,6 @@ int IoCommandWriteDot( Abc_Frame_t * pAbc, int argc, char **argv )
         return 0;
     }
 
-    if ( !Abc_NtkHasAig(pAbc->pNtkCur) )
-    {
-        fprintf( stdout, "IoCommandWriteDot(): Currently can only process AIGs.\n" );
-        return 0;
-    }
-
     if ( argc != globalUtilOptind + 1 )
     {
         goto usage;
@@ -1354,13 +1348,13 @@ int IoCommandWriteDot( Abc_Frame_t * pAbc, int argc, char **argv )
     FileName = argv[globalUtilOptind];
     // write the file
     vNodes = Abc_NtkCollectObjects( pAbc->pNtkCur );
-    Io_WriteDotAig( pAbc->pNtkCur, vNodes, NULL, FileName, 0 );
+    Io_WriteDotNtk( pAbc->pNtkCur, vNodes, NULL, FileName, 0, 0 );
     Vec_PtrFree( vNodes );
     return 0;
 
 usage:
     fprintf( pAbc->Err, "usage: write_dot [-h] <file>\n" );
-    fprintf( pAbc->Err, "\t         write the AIG into a DOT file\n" );
+    fprintf( pAbc->Err, "\t         write the current network into a DOT file\n" );
     fprintf( pAbc->Err, "\t-h     : print the help massage\n" );
     fprintf( pAbc->Err, "\tfile   : the name of the file to write\n" );
     return 1;
@@ -1598,13 +1592,13 @@ int IoCommandWritePla( Abc_Frame_t * pAbc, int argc, char **argv )
         return 0;
     }
 
-    if ( Abc_NtkGetLevelNum(pNtk) > 1 )
+    if ( Abc_NtkLevel(pNtk) > 1 )
     {
         fprintf( pAbc->Out, "PLA writing is available for collapsed networks.\n" );
         return 0;
     }
 
-    if ( Abc_NtkGetLevelNum(pNtk) > 1 )
+    if ( Abc_NtkLevel(pNtk) > 1 )
     {
         fprintf( pAbc->Out, "PLA writing is available for collapsed networks.\n" );
         return 0;
diff --git a/src/base/io/io.h b/src/base/io/io.h
index c42d2016..e7971b8d 100644
--- a/src/base/io/io.h
+++ b/src/base/io/io.h
@@ -86,8 +86,8 @@ extern int                Io_WriteBench( Abc_Ntk_t * pNtk, char * FileName );
 /*=== abcWriteCnf.c ==========================================================*/
 extern int                Io_WriteCnf( Abc_Ntk_t * pNtk, char * FileName );
 /*=== abcWriteDot.c ==========================================================*/
-extern void               Io_WriteDotAig( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesShow, char * pFileName, int fMulti );
-extern void               Io_WriteDotNtk( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesShow, char * pFileName, int fGateNames );
+extern void               Io_WriteDotNtk( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesShow, char * pFileName, int fGateNames, int fUseReverse );
+extern void               Io_WriteDotSeq( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesShow, char * pFileName, int fGateNames, int fUseReverse );
 /*=== abcWriteEqn.c ==========================================================*/
 extern void               Io_WriteEqn( Abc_Ntk_t * pNtk, char * pFileName );
 /*=== abcWriteGml.c ==========================================================*/
diff --git a/src/base/io/ioUtil.c b/src/base/io/ioUtil.c
index dff27dd1..fa2d6f25 100644
--- a/src/base/io/ioUtil.c
+++ b/src/base/io/ioUtil.c
@@ -132,7 +132,7 @@ Abc_Obj_t * Io_ReadCreateLatch( Abc_Ntk_t * pNtk, char * pNetLI, char * pNetLO )
     pNet = Abc_NtkFindOrCreateNet( pNtk, pNetLO );
     Abc_ObjAddFanin( pNet, pTerm );
     // set latch name
-    Abc_ObjAssignName( pLatch, pNetLO, "_latch" );
+    Abc_ObjAssignName( pLatch, pNetLO, "L" );
     return pLatch;
 }
 
diff --git a/src/base/io/ioWriteDot.c b/src/base/io/ioWriteDot.c
index 3cc3fcfe..084bd111 100644
--- a/src/base/io/ioWriteDot.c
+++ b/src/base/io/ioWriteDot.c
@@ -21,7 +21,6 @@
 #include "io.h"
 #include "main.h"
 #include "mio.h"
-//#include "seqInt.h"
 
 ////////////////////////////////////////////////////////////////////////
 ///                        DECLARATIONS                              ///
@@ -36,7 +35,7 @@ static int    Abc_NtkCountLogicNodes( Vec_Ptr_t * vNodes );
 
 /**Function*************************************************************
 
-  Synopsis    [Writes the graph structure of AIG for DOT.]
+  Synopsis    [Writes the graph structure of network for DOT.]
 
   Description [Useful for graph visualization using tools such as GraphViz: 
   http://www.graphviz.org/]
@@ -46,14 +45,15 @@ static int    Abc_NtkCountLogicNodes( Vec_Ptr_t * vNodes );
   SeeAlso     []
 
 ***********************************************************************/
-void Io_WriteDotAig( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesShow, char * pFileName, int fMulti )
+void Io_WriteDotNtk( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesShow, char * pFileName, int fGateNames, int fUseReverse )
 {
     FILE * pFile;
-    Abc_Obj_t * pNode, * pTemp, * pPrev;
-    int LevelMin, LevelMax, fHasCos, Level, i;
+    Abc_Obj_t * pNode, * pFanin;
+    char * pSopString;
+    int LevelMin, LevelMax, fHasCos, Level, i, k, fHasBdds, fCompl;
     int Limit = 300;
 
-    assert( Abc_NtkHasAig(pNtk) );
+    assert( Abc_NtkIsStrash(pNtk) || Abc_NtkIsLogic(pNtk) );
 
     if ( vNodes->nSize < 1 )
     {
@@ -74,6 +74,16 @@ void Io_WriteDotAig( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
         return;
     }
 
+    // transform logic functions from BDD to SOP
+    if ( fHasBdds = Abc_NtkIsBddLogic(pNtk) )
+    {
+        if ( !Abc_NtkBddToSop(pNtk, 0) )
+        {
+            printf( "Io_WriteDotNtk(): Converting to SOPs has failed.\n" );
+            return;
+        }
+    }
+
     // mark the nodes from the set
     Vec_PtrForEachEntry( vNodes, pNode, i )
         pNode->fMarkC = 1;
@@ -81,6 +91,17 @@ void Io_WriteDotAig( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
         Vec_PtrForEachEntry( vNodesShow, pNode, i )
             pNode->fMarkB = 1;
 
+    // get the levels of nodes
+    LevelMax = Abc_NtkLevel( pNtk );
+    if ( fUseReverse )
+    {
+        LevelMin = Abc_NtkLevelReverse( pNtk );
+        assert( LevelMax == LevelMin );
+        Vec_PtrForEachEntry( vNodes, pNode, i )
+            if ( Abc_ObjIsNode(pNode) )
+                pNode->Level = LevelMax - pNode->Level + 1;
+    }
+
     // find the largest and the smallest levels
     LevelMin = 10000;
     LevelMax = -1;
@@ -110,9 +131,9 @@ void Io_WriteDotAig( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
     }
 
     // write the DOT header
-    fprintf( pFile, "# %s\n",  "AIG structure generated by ABC" );
+    fprintf( pFile, "# %s\n",  "Network structure generated by ABC" );
     fprintf( pFile, "\n" );
-    fprintf( pFile, "digraph AIG {\n" );
+    fprintf( pFile, "digraph network {\n" );
     fprintf( pFile, "size = \"7.5,10\";\n" );
 //    fprintf( pFile, "size = \"10,8.5\";\n" );
 //    fprintf( pFile, "size = \"14,11\";\n" );
@@ -169,7 +190,7 @@ void Io_WriteDotAig( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
     fprintf( pFile, "          fontsize=20,\n" );
     fprintf( pFile, "          fontname = \"Times-Roman\",\n" );
     fprintf( pFile, "          label=\"" );
-    fprintf( pFile, "%s", "AIG structure visualized by ABC" );
+    fprintf( pFile, "%s", "Network structure visualized by ABC" );
     fprintf( pFile, "\\n" );
     fprintf( pFile, "Benchmark \\\"%s\\\". ", pNtk->pName );
     fprintf( pFile, "Time was %s. ",  Extra_TimeStamp() );
@@ -187,7 +208,10 @@ void Io_WriteDotAig( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
     fprintf( pFile, "          fontsize=18,\n" );
     fprintf( pFile, "          fontname = \"Times-Roman\",\n" );
     fprintf( pFile, "          label=\"" );
-    fprintf( pFile, "The set contains %d logic nodes and spans %d levels.", Abc_NtkCountLogicNodes(vNodes), LevelMax - LevelMin + 1 );
+    if ( Abc_NtkObjNum(pNtk) == Vec_PtrSize(vNodes) )
+        fprintf( pFile, "The network contains %d logic nodes and %d latches.", Abc_NtkNodeNum(pNtk), Abc_NtkLatchNum(pNtk) );
+    else
+        fprintf( pFile, "The set contains %d logic nodes and spans %d levels.", Abc_NtkCountLogicNodes(vNodes), LevelMax - LevelMin + 1 );
     fprintf( pFile, "\\n" );
     fprintf( pFile, "\"\n" );
     fprintf( pFile, "         ];\n" );
@@ -207,9 +231,11 @@ void Io_WriteDotAig( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
         {
             if ( !Abc_ObjIsCo(pNode) )
                 continue;
-            fprintf( pFile, "  Node%d%s [label = \"%s%s\"", pNode->Id, 
-                (Abc_ObjIsLatch(pNode)? "_in":""), Abc_ObjName(pNode), (Abc_ObjIsLatch(pNode)? "_in":"") );
-            fprintf( pFile, ", shape = %s", (Abc_ObjIsLatch(pNode)? "box":"invtriangle") );
+            fprintf( pFile, "  Node%d [label = \"%s%s\"", 
+                pNode->Id, 
+                (Abc_ObjIsBi(pNode)? Abc_ObjName(Abc_ObjFanout0(pNode)):Abc_ObjName(pNode)), 
+                (Abc_ObjIsBi(pNode)? "_in":"") );
+            fprintf( pFile, ", shape = %s", (Abc_ObjIsBi(pNode)? "box":"invtriangle") );
             if ( pNode->fMarkB )
                 fprintf( pFile, ", style = filled" );
             fprintf( pFile, ", color = coral, fillcolor = coral" );
@@ -231,7 +257,17 @@ void Io_WriteDotAig( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
         {
             if ( (int)pNode->Level != Level )
                 continue;
-            fprintf( pFile, "  Node%d [label = \"%d\"", pNode->Id, pNode->Id );
+//            fprintf( pFile, "  Node%d [label = \"%d\"", pNode->Id, pNode->Id );
+            if ( Abc_NtkIsStrash(pNtk) )
+                pSopString = "";
+            else if ( Abc_NtkHasMapping(pNtk) && fGateNames )
+                pSopString = Mio_GateReadName(pNode->pData);
+            else if ( Abc_NtkHasMapping(pNtk) )
+                pSopString = Abc_NtkPrintSop(Mio_GateReadSop(pNode->pData));
+            else
+                pSopString = Abc_NtkPrintSop(pNode->pData);
+            fprintf( pFile, "  Node%d [label = \"%d\\n%s\"", pNode->Id, pNode->Id, pSopString );
+
             fprintf( pFile, ", shape = ellipse" );
             if ( pNode->fMarkB )
                 fprintf( pFile, ", style = filled" );
@@ -249,7 +285,7 @@ void Io_WriteDotAig( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
         fprintf( pFile, "  rank = same;\n" );
         // the labeling node of this level
         fprintf( pFile, "  Level%d;\n",  LevelMin );
-        // generat the PO nodes
+        // generate the PO nodes
         Vec_PtrForEachEntry( vNodes, pNode, i )
         {
             if ( !Abc_ObjIsCi(pNode) )
@@ -266,9 +302,10 @@ void Io_WriteDotAig( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
                 }
                 continue;
             }
-            fprintf( pFile, "  Node%d%s [label = \"%s%s\"", pNode->Id, 
-                (Abc_ObjIsLatch(pNode)? "_out":""), Abc_ObjName(pNode), (Abc_ObjIsLatch(pNode)? "_out":"") );
-            fprintf( pFile, ", shape = %s", (Abc_ObjIsLatch(pNode)? "box":"triangle") );
+            fprintf( pFile, "  Node%d [label = \"%s\"", 
+                pNode->Id, 
+                (Abc_ObjIsBo(pNode)? Abc_ObjName(Abc_ObjFanin0(pNode)):Abc_ObjName(pNode)) );
+            fprintf( pFile, ", shape = %s", (Abc_ObjIsBo(pNode)? "box":"triangle") );
             if ( pNode->fMarkB )
                 fprintf( pFile, ", style = filled" );
             fprintf( pFile, ", color = coral, fillcolor = coral" );
@@ -285,88 +322,30 @@ void Io_WriteDotAig( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
     {
         if ( (int)pNode->Level != LevelMax )
             continue;
-        fprintf( pFile, "title2 -> Node%d%s [style = invis];\n", pNode->Id, 
-            (Abc_ObjIsLatch(pNode)? "_in":"") );
+        fprintf( pFile, "title2 -> Node%d [style = invis];\n", pNode->Id );
     }
 
     // generate edges
     Vec_PtrForEachEntry( vNodes, pNode, i )
     {
-        if ( Abc_ObjFaninNum(pNode) == 0 )
-            continue;
-
-        if ( Abc_ObjIsBo(pNode) )
-            continue;
-
-        if ( fMulti && Abc_ObjIsNode(pNode) )
-        {
-            Vec_Ptr_t * vSuper;
-            Abc_Obj_t * pFanin;
-            int k, fCompl;
-            vSuper = (Vec_Ptr_t *)pNode->pCopy;
-            assert( vSuper != NULL );
-            Vec_PtrForEachEntry( vSuper, pFanin, k )
-            {
-                fCompl = Abc_ObjIsComplement(pFanin);
-                pFanin = Abc_ObjRegular(pFanin);
-                if ( !pFanin->fMarkC )
-                    continue;
-
-                if ( Abc_ObjIsBi(pFanin) )
-                    continue;
-
-                fprintf( pFile, "Node%d",  pNode->Id );
-                fprintf( pFile, " -> " );
-                fprintf( pFile, "Node%d%s",  pFanin->Id, (Abc_ObjIsLatch(pFanin)? "_out":"") );
-                fprintf( pFile, " [" );
-                fprintf( pFile, "style = %s", fCompl? "dotted" : "bold" );
-                fprintf( pFile, "]" );
-                fprintf( pFile, ";\n" );
-            }
-            continue;
-        }
-        // generate the edge from this node to the next
-        if ( Abc_ObjFanin0(pNode)->fMarkC && !Abc_ObjIsBi(Abc_ObjFanin0(pNode)) )
-        {
-            fprintf( pFile, "Node%d%s",  pNode->Id, (Abc_ObjIsLatch(pNode)? "_in":"") );
-            fprintf( pFile, " -> " );
-            fprintf( pFile, "Node%d%s",  Abc_ObjFaninId0(pNode), (Abc_ObjIsLatch(Abc_ObjFanin0(pNode))? "_out":"") );
-            fprintf( pFile, " [" );
-            fprintf( pFile, "style = %s", Abc_ObjFaninC0(pNode)? "dotted" : "bold" );
-//            if ( Abc_NtkIsSeq(pNode->pNtk) && Seq_ObjFaninL0(pNode) > 0 )
-//            fprintf( pFile, ", label = \"%s\"", Seq_ObjFaninGetInitPrintable(pNode,0) );
-            fprintf( pFile, "]" );
-            fprintf( pFile, ";\n" );
-        }
-        if ( Abc_ObjFaninNum(pNode) == 1 )
+        if ( Abc_ObjIsLatch(pNode) )
             continue;
-        // generate the edge from this node to the next
-        if ( Abc_ObjFanin1(pNode)->fMarkC && !Abc_ObjIsBi(Abc_ObjFanin1(pNode)) )
+        Abc_ObjForEachFanin( pNode, pFanin, k )
         {
+            if ( Abc_ObjIsLatch(pFanin) )
+                continue;
+            fCompl = 0;
+            if ( Abc_NtkIsStrash(pNtk) )
+                fCompl = Abc_ObjFaninC(pNode, k);
+            // generate the edge from this node to the next
             fprintf( pFile, "Node%d",  pNode->Id );
             fprintf( pFile, " -> " );
-            fprintf( pFile, "Node%d%s",  Abc_ObjFaninId1(pNode), (Abc_ObjIsLatch(Abc_ObjFanin1(pNode))? "_out":"") );
-            fprintf( pFile, " [" );
-            fprintf( pFile, "style = %s", Abc_ObjFaninC1(pNode)? "dotted" : "bold" );
-//            if ( Abc_NtkIsSeq(pNode->pNtk) && Seq_ObjFaninL1(pNode) > 0 )
-//            fprintf( pFile, ", label = \"%s\"", Seq_ObjFaninGetInitPrintable(pNode,1) );
+            fprintf( pFile, "Node%d",  pFanin->Id );
+            fprintf( pFile, " [style = %s", fCompl? "dotted" : "bold" );
+//            fprintf( pFile, ", label = \"%c\"", 'a' + k );
             fprintf( pFile, "]" );
             fprintf( pFile, ";\n" );
         }
-        // generate the edges between the equivalent nodes
-        pPrev = pNode;
-        for ( pTemp = pNode->pData; pTemp; pTemp = pTemp->pData )
-        {
-            if ( pTemp->fMarkC )
-            {
-                fprintf( pFile, "Node%d",  pPrev->Id );
-                fprintf( pFile, " -> " );
-                fprintf( pFile, "Node%d",  pTemp->Id );
-                fprintf( pFile, " [style = %s]", (pPrev->fPhase ^ pTemp->fPhase)? "dotted" : "bold" );
-                fprintf( pFile, ";\n" );
-                pPrev = pTemp;
-            }
-        }
     }
 
     fprintf( pFile, "}" );
@@ -380,8 +359,13 @@ void Io_WriteDotAig( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
     if ( vNodesShow )
         Vec_PtrForEachEntry( vNodesShow, pNode, i )
             pNode->fMarkB = 0;
+
+    // convert the network back into BDDs if this is how it was
+    if ( fHasBdds )
+        Abc_NtkSopToBdd(pNtk);
 }
 
+
 /**Function*************************************************************
 
   Synopsis    [Writes the graph structure of network for DOT.]
@@ -394,15 +378,15 @@ void Io_WriteDotAig( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
   SeeAlso     []
 
 ***********************************************************************/
-void Io_WriteDotNtk( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesShow, char * pFileName, int fGateNames )
+void Io_WriteDotSeq( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesShow, char * pFileName, int fGateNames, int fUseReverse )
 {
     FILE * pFile;
     Abc_Obj_t * pNode, * pFanin;
     char * pSopString;
-    int LevelMin, LevelMax, fHasCos, Level, i, k, fHasBdds;
+    int LevelMin, LevelMax, fHasCos, Level, i, k, fHasBdds, fCompl;
     int Limit = 300;
 
-    assert( !Abc_NtkIsStrash(pNtk) );
+    assert( Abc_NtkIsStrash(pNtk) || Abc_NtkIsLogic(pNtk) );
 
     if ( vNodes->nSize < 1 )
     {
@@ -441,7 +425,15 @@ void Io_WriteDotNtk( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
             pNode->fMarkB = 1;
 
     // get the levels of nodes
-    Abc_NtkGetLevelNum( pNtk );
+    LevelMax = Abc_NtkLevel( pNtk );
+    if ( fUseReverse )
+    {
+        LevelMin = Abc_NtkLevelReverse( pNtk );
+        assert( LevelMax == LevelMin );
+        Vec_PtrForEachEntry( vNodes, pNode, i )
+            if ( Abc_ObjIsNode(pNode) )
+                pNode->Level = LevelMax - pNode->Level + 1;
+    }
 
     // find the largest and the smallest levels
     LevelMin = 10000;
@@ -474,12 +466,15 @@ void Io_WriteDotNtk( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
     // write the DOT header
     fprintf( pFile, "# %s\n",  "Network structure generated by ABC" );
     fprintf( pFile, "\n" );
-    fprintf( pFile, "digraph AIG {\n" );
+    fprintf( pFile, "digraph network {\n" );
     fprintf( pFile, "size = \"7.5,10\";\n" );
+//    fprintf( pFile, "size = \"10,8.5\";\n" );
+//    fprintf( pFile, "size = \"14,11\";\n" );
+//    fprintf( pFile, "page = \"8,11\";\n" );
 //  fprintf( pFile, "ranksep = 0.5;\n" );
 //  fprintf( pFile, "nodesep = 0.5;\n" );
     fprintf( pFile, "center = true;\n" );
-//  fprintf( pFile, "orientation = landscape;\n" );
+//    fprintf( pFile, "orientation = landscape;\n" );
 //  fprintf( pFile, "edge [fontsize = 10];\n" );
 //  fprintf( pFile, "edge [dir = none];\n" );
     fprintf( pFile, "edge [dir = back];\n" );
@@ -546,7 +541,10 @@ void Io_WriteDotNtk( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
     fprintf( pFile, "          fontsize=18,\n" );
     fprintf( pFile, "          fontname = \"Times-Roman\",\n" );
     fprintf( pFile, "          label=\"" );
-    fprintf( pFile, "The set contains %d logic nodes and spans %d levels.", Abc_NtkCountLogicNodes(vNodes), LevelMax - LevelMin + 1 );
+    if ( Abc_NtkObjNum(pNtk) == Vec_PtrSize(vNodes) )
+        fprintf( pFile, "The network contains %d logic nodes and %d latches.", Abc_NtkNodeNum(pNtk), Abc_NtkLatchNum(pNtk) );
+    else
+        fprintf( pFile, "The set contains %d logic nodes and spans %d levels.", Abc_NtkCountLogicNodes(vNodes), LevelMax - LevelMin + 1 );
     fprintf( pFile, "\\n" );
     fprintf( pFile, "\"\n" );
     fprintf( pFile, "         ];\n" );
@@ -564,11 +562,10 @@ void Io_WriteDotNtk( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
         // generate the PO nodes
         Vec_PtrForEachEntry( vNodes, pNode, i )
         {
-            if ( !Abc_ObjIsCo(pNode) )
+            if ( !Abc_ObjIsPo(pNode) )
                 continue;
-            fprintf( pFile, "  Node%d%s [label = \"%s%s\"", pNode->Id, 
-                (Abc_ObjIsLatch(pNode)? "_in":""), Abc_ObjName(pNode), (Abc_ObjIsLatch(pNode)? "_in":"") );
-            fprintf( pFile, ", shape = %s", (Abc_ObjIsLatch(pNode)? "box":"invtriangle") );
+            fprintf( pFile, "  Node%d [label = \"%s\"", pNode->Id, Abc_ObjName(pNode) );
+            fprintf( pFile, ", shape = %s", "invtriangle" );
             if ( pNode->fMarkB )
                 fprintf( pFile, ", style = filled" );
             fprintf( pFile, ", color = coral, fillcolor = coral" );
@@ -586,12 +583,14 @@ void Io_WriteDotNtk( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
         fprintf( pFile, "  rank = same;\n" );
         // the labeling node of this level
         fprintf( pFile, "  Level%d;\n",  Level );
-        Vec_PtrForEachEntry( vNodes, pNode, i )
+        Abc_NtkForEachNode( pNtk, pNode, i )
         {
             if ( (int)pNode->Level != Level )
                 continue;
 //            fprintf( pFile, "  Node%d [label = \"%d\"", pNode->Id, pNode->Id );
-            if ( Abc_NtkHasMapping(pNtk) && fGateNames )
+            if ( Abc_NtkIsStrash(pNtk) )
+                pSopString = "";
+            else if ( Abc_NtkHasMapping(pNtk) && fGateNames )
                 pSopString = Mio_GateReadName(pNode->pData);
             else if ( Abc_NtkHasMapping(pNtk) )
                 pSopString = Abc_NtkPrintSop(Mio_GateReadSop(pNode->pData));
@@ -619,7 +618,9 @@ void Io_WriteDotNtk( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
         // generate the PO nodes
         Vec_PtrForEachEntry( vNodes, pNode, i )
         {
-            if ( !Abc_ObjIsCi(pNode) )
+            if ( pNode->Level > 0 )
+                continue;
+            if ( !Abc_ObjIsPi(pNode) )
             {
                 // check if the costant node is present
                 if ( Abc_ObjFaninNum(pNode) == 0 && Abc_ObjFanoutNum(pNode) > 0 )
@@ -633,9 +634,8 @@ void Io_WriteDotNtk( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
                 }
                 continue;
             }
-            fprintf( pFile, "  Node%d%s [label = \"%s%s\"", pNode->Id, 
-                (Abc_ObjIsLatch(pNode)? "_out":""), Abc_ObjName(pNode), (Abc_ObjIsLatch(pNode)? "_out":"") );
-            fprintf( pFile, ", shape = %s", (Abc_ObjIsLatch(pNode)? "box":"triangle") );
+            fprintf( pFile, "  Node%d [label = \"%s\"", pNode->Id, Abc_ObjName(pNode) );
+            fprintf( pFile, ", shape = %s", "triangle" );
             if ( pNode->fMarkB )
                 fprintf( pFile, ", style = filled" );
             fprintf( pFile, ", color = coral, fillcolor = coral" );
@@ -646,34 +646,61 @@ void Io_WriteDotNtk( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
         fprintf( pFile, "\n" );
     }
 
+//    fprintf( pFile, "{\n" );
+    Vec_PtrForEachEntry( vNodes, pNode, i )
+    {
+        if ( !Abc_ObjIsLatch(pNode) )
+            continue;
+        fprintf( pFile, "Node%d [label = \"%s\"", pNode->Id, Abc_ObjName(pNode) );
+        fprintf( pFile, ", shape = box" );
+        if ( pNode->fMarkB )
+            fprintf( pFile, ", style = filled" );
+        fprintf( pFile, ", color = coral, fillcolor = coral" );
+        fprintf( pFile, "];\n" );
+    }
+//    fprintf( pFile, "}" );
+//    fprintf( pFile, "\n" );
+    fprintf( pFile, "\n" );
+
     // generate invisible edges from the square down
     fprintf( pFile, "title1 -> title2 [style = invis];\n" );
     Vec_PtrForEachEntry( vNodes, pNode, i )
     {
         if ( (int)pNode->Level != LevelMax )
             continue;
-        fprintf( pFile, "title2 -> Node%d%s [style = invis];\n", pNode->Id, 
-            (Abc_ObjIsLatch(pNode)? "_in":"") );
+        if ( !Abc_ObjIsPo(pNode) )
+            continue;
+        fprintf( pFile, "title2 -> Node%d [style = invis];\n", pNode->Id );
     }
 
     // generate edges
     Vec_PtrForEachEntry( vNodes, pNode, i )
     {
+        if ( Abc_ObjIsBi(pNode) || Abc_ObjIsBo(pNode) )
+            continue;
         Abc_ObjForEachFanin( pNode, pFanin, k )
         {
-            if ( !Abc_ObjFanin0(pNode)->fMarkC )
-                continue;
-
-            // added to fix the bug after adding boxes
-            if ( Abc_ObjIsBo(pNode) || Abc_ObjIsBi(pFanin) )
+            fCompl = 0;
+            if ( Abc_NtkIsStrash(pNtk) )
+            {
+                if ( Abc_ObjIsBi(pFanin) )
+                    fCompl = Abc_ObjFaninC(pFanin, k);
+                else
+                    fCompl = Abc_ObjFaninC(pNode, k);
+            }
+            if ( Abc_ObjIsBi(pFanin) || Abc_ObjIsBo(pFanin) )
+                pFanin = Abc_ObjFanin0(pFanin);
+            if ( Abc_ObjIsBi(pFanin) || Abc_ObjIsBo(pFanin) )
+                pFanin = Abc_ObjFanin0(pFanin);
+            if ( !pFanin->fMarkC )
                 continue;
 
             // generate the edge from this node to the next
-            fprintf( pFile, "Node%d%s",  pNode->Id, (Abc_ObjIsLatch(pNode)? "_in":"") );
+            fprintf( pFile, "Node%d",  pNode->Id );
             fprintf( pFile, " -> " );
-            fprintf( pFile, "Node%d%s",  Abc_ObjFaninId(pNode,k), (Abc_ObjIsLatch(Abc_ObjFanin(pNode,k))? "_out":"") );
-            fprintf( pFile, " [style = bold" );
-            fprintf( pFile, ", label = \"%c\"", 'a' + k );
+            fprintf( pFile, "Node%d",  pFanin->Id );
+            fprintf( pFile, " [style = %s", fCompl? "dotted" : "bold" );
+//            fprintf( pFile, ", label = \"%c\"", 'a' + k );
             fprintf( pFile, "]" );
             fprintf( pFile, ";\n" );
         }
@@ -696,6 +723,7 @@ void Io_WriteDotNtk( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho
         Abc_NtkSopToBdd(pNtk);
 }
 
+
 /**Function*************************************************************
 
   Synopsis    [Computes the printable SOP form.]
diff --git a/src/base/io/ioWritePla.c b/src/base/io/ioWritePla.c
index 4da8aca8..b119751c 100644
--- a/src/base/io/ioWritePla.c
+++ b/src/base/io/ioWritePla.c
@@ -47,7 +47,7 @@ int Io_WritePla( Abc_Ntk_t * pNtk, char * pFileName )
     FILE * pFile;
 
     assert( Abc_NtkIsSopNetlist(pNtk) );
-    assert( Abc_NtkGetLevelNum(pNtk) == 1 );
+    assert( Abc_NtkLevel(pNtk) == 1 );
 
     pFile = fopen( pFileName, "w" );
     if ( pFile == NULL )
diff --git a/src/base/io/ioWriteVer.c b/src/base/io/ioWriteVer.c
index 381e6e28..9be3d8b3 100644
--- a/src/base/io/ioWriteVer.c
+++ b/src/base/io/ioWriteVer.c
@@ -463,7 +463,7 @@ void Io_WriteVerilogVerLibStyle( FILE * pFile, Abc_Ntk_t * pNtk )
     Vec_Vec_t * vLevels;
     Abc_Ntk_t * pNtkGate;
     Abc_Obj_t * pObj, * pTerm, * pFanin;
-    Aig_Obj_t * pFunc;
+    Hop_Obj_t * pFunc;
     int i, k, Counter, nDigits;
 
     Counter = 1;
@@ -495,13 +495,13 @@ void Io_WriteVerilogVerLibStyle( FILE * pFile, Abc_Ntk_t * pNtk )
         fprintf( pFile, "  assign %s = ", Io_WriteVerilogGetName(Abc_ObjFanout0(pObj)) );
         // set the input names
         Abc_ObjForEachFanin( pObj, pFanin, k )
-            Aig_IthVar(pNtk->pManFunc, k)->pData = Extra_UtilStrsav(Io_WriteVerilogGetName(pFanin));
+            Hop_IthVar(pNtk->pManFunc, k)->pData = Extra_UtilStrsav(Io_WriteVerilogGetName(pFanin));
         // write the formula
-        Aig_ObjPrintVerilog( pFile, pFunc, vLevels, 0 );
+        Hop_ObjPrintVerilog( pFile, pFunc, vLevels, 0 );
         fprintf( pFile, ";\n" );
         // clear the input names
         Abc_ObjForEachFanin( pObj, pFanin, k )
-            free( Aig_IthVar(pNtk->pManFunc, k)->pData );
+            free( Hop_IthVar(pNtk->pManFunc, k)->pData );
     }
     Vec_VecFree( vLevels );
 }
diff --git a/src/base/main/libSupport.c b/src/base/main/libSupport.c
index cdfd98b8..471ea09e 100644
--- a/src/base/main/libSupport.c
+++ b/src/base/main/libSupport.c
@@ -49,7 +49,7 @@ void open_libs() {
 
     env = getenv ("ABC_LIB_PATH");
     if (env == NULL) {
-      printf("Warning: ABC_LIB_PATH not defined. Looking into the current directory.\n");
+//    printf("Warning: ABC_LIB_PATH not defined. Looking into the current directory.\n");
       init_p = malloc (2*sizeof(char));
       init_p[0]='.'; init_p[1] = 0;
     } else {
@@ -67,7 +67,7 @@ void open_libs() {
 
       dirp = opendir(p);
       if (dirp == NULL) {
-        printf("Warning: directory in ABC_LIB_PATH does not exist (%s).\n", p);
+//      printf("Warning: directory in ABC_LIB_PATH does not exist (%s).\n", p);
         continue;
       }
 
diff --git a/src/base/ver/module.make b/src/base/ver/module.make
new file mode 100644
index 00000000..2cc37803
--- /dev/null
+++ b/src/base/ver/module.make
@@ -0,0 +1,4 @@
+SRC +=    src/base/ver/verCore.c \
+    src/base/ver/verFormula.c \
+    src/base/ver/verParse.c \
+    src/base/ver/verStream.c 
diff --git a/src/base/ver/ver.h b/src/base/ver/ver.h
new file mode 100644
index 00000000..c7c18f79
--- /dev/null
+++ b/src/base/ver/ver.h
@@ -0,0 +1,114 @@
+/**CFile****************************************************************
+
+  FileName    [ver.h]
+
+  SystemName  [ABC: Logic synthesis and verification system.]
+
+  PackageName [Verilog parser.]
+
+  Synopsis    [External declarations.]
+
+  Author      [Alan Mishchenko]
+  
+  Affiliation [UC Berkeley]
+
+  Date        [Ver. 1.0. Started - August 19, 2006.]
+
+  Revision    [$Id: ver.h,v 1.00 2006/08/19 00:00:00 alanmi Exp $]
+
+***********************************************************************/
+
+#ifndef __VER_H__
+#define __VER_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+////////////////////////////////////////////////////////////////////////
+///                          INCLUDES                                ///
+////////////////////////////////////////////////////////////////////////
+
+#include <stdio.h>
+#include "abc.h"
+
+////////////////////////////////////////////////////////////////////////
+///                         PARAMETERS                               ///
+////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////
+///                         BASIC TYPES                              ///
+////////////////////////////////////////////////////////////////////////
+
+typedef struct Ver_Man_t_       Ver_Man_t;
+typedef struct Ver_Stream_t_    Ver_Stream_t;
+
+struct Ver_Man_t_
+{
+    // input file stream
+    char *          pFileName;
+    Ver_Stream_t *  pReader;
+    ProgressBar *   pProgress;
+    // current network and library
+    Abc_Ntk_t *     pNtkCur;       // the network under construction
+    Abc_Lib_t *     pDesign;       // the current design 
+    // parameters
+    int             fUseMemMan;    // allocate memory manager in the networks
+    int             fCheck;        // checks network for currectness
+    // error recovery
+    FILE *          Output;
+    int             fTopLevel;
+    int             fError;
+    char            sError[2000];
+    // intermediate structures
+    Vec_Ptr_t *     vNames;  
+    Vec_Ptr_t *     vStackFn;
+    Vec_Int_t *     vStackOp;
+};
+
+////////////////////////////////////////////////////////////////////////
+///                      MACRO DEFINITIONS                           ///
+////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////
+///                             ITERATORS                            ///
+////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////
+///                    FUNCTION DECLARATIONS                         ///
+////////////////////////////////////////////////////////////////////////
+
+/*=== verCore.c ========================================================*/
+extern Abc_Lib_t *    Ver_ParseFile( char * pFileName, Abc_Lib_t * pGateLib, int fCheck, int fUseMemMan );
+extern void           Ver_ParsePrintErrorMessage( Ver_Man_t * p );
+/*=== verFormula.c ========================================================*/
+extern void *         Ver_FormulaParser( char * pFormula, void * pMan, Vec_Ptr_t * vNames, Vec_Ptr_t * vStackFn, Vec_Int_t * vStackOp, char * pErrorMessage );
+extern void *         Ver_FormulaReduction( char * pFormula, void * pMan, Vec_Ptr_t * vNames, char * pErrorMessage );
+/*=== verParse.c ========================================================*/
+extern int            Ver_ParseSkipComments( Ver_Man_t * p );
+extern char *         Ver_ParseGetName( Ver_Man_t * p );
+/*=== verStream.c ========================================================*/
+extern Ver_Stream_t * Ver_StreamAlloc( char * pFileName );
+extern void           Ver_StreamFree( Ver_Stream_t * p );
+extern char *         Ver_StreamGetFileName( Ver_Stream_t * p );
+extern int            Ver_StreamGetFileSize( Ver_Stream_t * p );
+extern int            Ver_StreamGetCurPosition( Ver_Stream_t * p );
+extern int            Ver_StreamGetLineNumber( Ver_Stream_t * p );
+
+extern int            Ver_StreamIsOkey( Ver_Stream_t * p );
+extern char           Ver_StreamScanChar( Ver_Stream_t * p );
+extern char           Ver_StreamPopChar( Ver_Stream_t * p );
+extern void           Ver_StreamSkipChars( Ver_Stream_t * p, char * pCharsToSkip );
+extern void           Ver_StreamSkipToChars( Ver_Stream_t * p, char * pCharsToStop );
+extern char *         Ver_StreamGetWord( Ver_Stream_t * p, char * pCharsToStop );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+////////////////////////////////////////////////////////////////////////
+///                       END OF FILE                                ///
+////////////////////////////////////////////////////////////////////////
+
diff --git a/src/base/ver/verCore.c b/src/base/ver/verCore.c
new file mode 100644
index 00000000..9048337b
--- /dev/null
+++ b/src/base/ver/verCore.c
@@ -0,0 +1,1092 @@
+/**CFile****************************************************************
+
+  FileName    [verCore.c]
+
+  SystemName  [ABC: Logic synthesis and verification system.]
+
+  PackageName [Verilog parser.]
+
+  Synopsis    [Parses several flavors of structural Verilog.]
+
+  Author      [Alan Mishchenko]
+  
+  Affiliation [UC Berkeley]
+
+  Date        [Ver. 1.0. Started - August 19, 2006.]
+
+  Revision    [$Id: verCore.c,v 1.00 2006/08/19 00:00:00 alanmi Exp $]
+
+***********************************************************************/
+
+#include "ver.h"
+
+////////////////////////////////////////////////////////////////////////
+///                        DECLARATIONS                              ///
+////////////////////////////////////////////////////////////////////////
+
+// types of verilog signals
+typedef enum { 
+    VER_SIG_NONE = 0,
+    VER_SIG_INPUT,
+    VER_SIG_OUTPUT,
+    VER_SIG_INOUT,
+    VER_SIG_REG,
+    VER_SIG_WIRE
+} Ver_SignalType_t;
+
+// types of verilog gates
+typedef enum { 
+    VER_GATE_AND = 0,
+    VER_GATE_OR,
+    VER_GATE_XOR,
+    VER_GATE_BUF,
+    VER_GATE_NAND,
+    VER_GATE_NOR,
+    VER_GATE_XNOR,
+    VER_GATE_NOT
+} Ver_GateType_t;
+
+static Ver_Man_t * Ver_ParseStart( char * pFileName, Abc_Lib_t * pGateLib );
+static void Ver_ParseStop( Ver_Man_t * p );
+static void Ver_ParseFreeData( Ver_Man_t * p );
+static void Ver_ParseInternal( Ver_Man_t * p );
+static int  Ver_ParseModule( Ver_Man_t * p );
+static int  Ver_ParseSignal( Ver_Man_t * p, Ver_SignalType_t SigType );
+static int  Ver_ParseAssign( Ver_Man_t * p );
+static int  Ver_ParseAlways( Ver_Man_t * p );
+static int  Ver_ParseInitial( Ver_Man_t * p );
+static int  Ver_ParseGate( Ver_Man_t * p, Abc_Ntk_t * pNtkGate );
+static int  Ver_ParseGateStandard( Ver_Man_t * pMan, Ver_GateType_t GateType );
+
+static Abc_Obj_t * Ver_ParseCreatePi( Abc_Ntk_t * pNtk, char * pName );
+static Abc_Obj_t * Ver_ParseCreatePo( Abc_Ntk_t * pNtk, char * pName );
+static Abc_Obj_t * Ver_ParseCreateLatch( Abc_Ntk_t * pNtk, char * pNetLI, char * pNetLO );
+
+////////////////////////////////////////////////////////////////////////
+///                     FUNCTION DEFINITIONS                         ///
+////////////////////////////////////////////////////////////////////////
+
+/**Function*************************************************************
+
+  Synopsis    [File parser.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Abc_Lib_t * Ver_ParseFile( char * pFileName, Abc_Lib_t * pGateLib, int fCheck, int fUseMemMan )
+{
+    Ver_Man_t * p;
+    Abc_Lib_t * pDesign;
+    // start the parser
+    p = Ver_ParseStart( pFileName, pGateLib );
+    p->fCheck     = fCheck;
+    p->fUseMemMan = fUseMemMan;
+    // parse the file
+    Ver_ParseInternal( p );
+    // save the result
+    pDesign = p->pDesign;
+    p->pDesign = NULL;
+    // stop the parser
+    Ver_ParseStop( p );
+    return pDesign;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Start parser.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Ver_Man_t * Ver_ParseStart( char * pFileName, Abc_Lib_t * pGateLib )
+{
+    Ver_Man_t * p;
+    p = ALLOC( Ver_Man_t, 1 );
+    memset( p, 0, sizeof(Ver_Man_t) );
+    p->pFileName = pFileName;
+    p->pReader   = Ver_StreamAlloc( pFileName );
+    p->Output    = stdout;
+    p->pProgress = Extra_ProgressBarStart( stdout, Ver_StreamGetFileSize(p->pReader) );
+    p->vNames    = Vec_PtrAlloc( 100 );
+    p->vStackFn  = Vec_PtrAlloc( 100 );
+    p->vStackOp  = Vec_IntAlloc( 100 );
+    // create the design library and assign the technology library
+    p->pDesign   = Abc_LibCreate( pFileName );
+    p->pDesign->pLibrary = pGateLib;
+    return p;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Stop parser.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Ver_ParseStop( Ver_Man_t * p )
+{
+    assert( p->pNtkCur == NULL );
+    Ver_StreamFree( p->pReader );
+    Extra_ProgressBarStop( p->pProgress );
+    Vec_PtrFree( p->vNames   );
+    Vec_PtrFree( p->vStackFn );
+    Vec_IntFree( p->vStackOp );
+    free( p );
+}
+
+/**Function*************************************************************
+
+  Synopsis    [File parser.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Ver_ParseInternal( Ver_Man_t * pMan )
+{
+    char * pToken;
+    while ( 1 )
+    {
+        // get the next token
+        pToken = Ver_ParseGetName( pMan );
+        if ( pToken == NULL )
+            break;
+        if ( strcmp( pToken, "module" ) )
+        {
+            sprintf( pMan->sError, "Cannot read \"module\" directive." );
+            Ver_ParsePrintErrorMessage( pMan );
+            return;
+        }
+
+        // parse the module
+        if ( !Ver_ParseModule( pMan ) )
+            return;
+
+        // check the network for correctness
+        if ( pMan->fCheck && !Abc_NtkCheckRead( pMan->pNtkCur ) )
+        {
+            pMan->fTopLevel = 1;
+            sprintf( pMan->sError, "The network check has failed.", pMan->pNtkCur->pName );
+            Ver_ParsePrintErrorMessage( pMan );
+            return;
+        }
+        // add the module to the hash table
+        if ( st_is_member( pMan->pDesign->tModules, pMan->pNtkCur->pName ) )
+        {
+            pMan->fTopLevel = 1;
+            sprintf( pMan->sError, "Module \"%s\" is defined more than once.", pMan->pNtkCur->pName );
+            Ver_ParsePrintErrorMessage( pMan );
+            return;
+        }
+        Vec_PtrPush( pMan->pDesign->vModules, pMan->pNtkCur );
+        st_insert( pMan->pDesign->tModules, pMan->pNtkCur->pName, (char *)pMan->pNtkCur );
+        pMan->pNtkCur = NULL;
+    }
+}
+
+/**Function*************************************************************
+
+  Synopsis    [File parser.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Ver_ParseFreeData( Ver_Man_t * p )
+{
+    if ( p->pNtkCur )
+    {
+        p->pNtkCur->pManFunc = NULL;
+        Abc_NtkDelete( p->pNtkCur );
+        p->pNtkCur = NULL;
+    }
+    if ( p->pDesign )
+    {
+        Abc_LibFree( p->pDesign );
+        p->pDesign = NULL;
+    }
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Prints the error message including the file name and line number.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Ver_ParsePrintErrorMessage( Ver_Man_t * p )
+{
+    p->fError = 1;
+    if ( p->fTopLevel ) // the line number is not given
+        fprintf( p->Output, "%s: %s\n", p->pFileName, p->sError );
+    else // print the error message with the line number
+        fprintf( p->Output, "%s (line %d): %s\n", 
+            p->pFileName, Ver_StreamGetLineNumber(p->pReader), p->sError );
+    // free the data
+    Ver_ParseFreeData( p );
+}
+
+
+
+/**Function*************************************************************
+
+  Synopsis    [Parses one Verilog module.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+int Ver_ParseModule( Ver_Man_t * pMan )
+{
+    Ver_Stream_t * p = pMan->pReader;
+    Abc_Ntk_t * pNtk, * pNtkTemp;
+    Abc_Obj_t * pNet;
+    char * pWord, Symbol;
+    int RetValue;
+
+    // start the current network
+    assert( pMan->pNtkCur == NULL );
+    pNtk = pMan->pNtkCur = Abc_NtkAlloc( ABC_NTK_NETLIST, ABC_FUNC_BLACKBOX, pMan->fUseMemMan );
+    pNtk->ntkFunc  = ABC_FUNC_AIG;
+    pNtk->pManFunc = pMan->pDesign->pManFunc;
+
+    // get the network name
+    pWord = Ver_ParseGetName( pMan );
+    pNtk->pName = Extra_UtilStrsav( pWord );
+    pNtk->pSpec = NULL;
+
+    // create constant nets
+    Abc_NtkFindOrCreateNet( pNtk, "1'b0" );
+    Abc_NtkFindOrCreateNet( pNtk, "1'b1" );
+
+    // make sure we stopped at the opening paranthesis
+    if ( Ver_StreamPopChar(p) != '(' )
+    {
+        sprintf( pMan->sError, "Cannot find \"(\" after \"module\".", pNtk->pName );
+        Ver_ParsePrintErrorMessage( pMan );
+        return 0;
+    }
+
+    // skip to the end of parantheses
+    do {
+        if ( Ver_ParseGetName( pMan ) == NULL )
+            return 0;
+        Symbol = Ver_StreamPopChar(p);
+    } while ( Symbol == ',' );
+    assert( Symbol == ')' );
+    if ( !Ver_ParseSkipComments( pMan ) )
+        return 0;
+    Symbol = Ver_StreamPopChar(p);
+    assert( Symbol == ';' );
+
+    // parse the inputs/outputs/registers/wires/inouts
+    while ( 1 )
+    {
+        Extra_ProgressBarUpdate( pMan->pProgress, Ver_StreamGetCurPosition(p), NULL );
+        pWord = Ver_ParseGetName( pMan );
+        if ( pWord == NULL )
+            return 0;
+        if ( !strcmp( pWord, "input" ) )
+            RetValue = Ver_ParseSignal( pMan, VER_SIG_INPUT );
+        else if ( !strcmp( pWord, "output" ) )
+            RetValue = Ver_ParseSignal( pMan, VER_SIG_OUTPUT );
+        else if ( !strcmp( pWord, "reg" ) )
+            RetValue = Ver_ParseSignal( pMan, VER_SIG_REG );
+        else if ( !strcmp( pWord, "wire" ) )
+            RetValue = Ver_ParseSignal( pMan, VER_SIG_WIRE );
+        else if ( !strcmp( pWord, "inout" ) )
+            RetValue = Ver_ParseSignal( pMan, VER_SIG_INOUT );
+        else 
+            break;
+        if ( RetValue == 0 )
+            return 0;
+    }
+
+    // parse the remaining statements
+    while ( 1 )
+    {
+        Extra_ProgressBarUpdate( pMan->pProgress, Ver_StreamGetCurPosition(p), NULL );
+
+        if ( !strcmp( pWord, "and" ) )
+            RetValue = Ver_ParseGateStandard( pMan, VER_GATE_AND );
+        else if ( !strcmp( pWord, "or" ) )
+            RetValue = Ver_ParseGateStandard( pMan, VER_GATE_OR );
+        else if ( !strcmp( pWord, "xor" ) )
+            RetValue = Ver_ParseGateStandard( pMan, VER_GATE_XOR );
+        else if ( !strcmp( pWord, "buf" ) )
+            RetValue = Ver_ParseGateStandard( pMan, VER_GATE_BUF );
+        else if ( !strcmp( pWord, "nand" ) )
+            RetValue = Ver_ParseGateStandard( pMan, VER_GATE_NAND );
+        else if ( !strcmp( pWord, "nor" ) )
+            RetValue = Ver_ParseGateStandard( pMan, VER_GATE_NOR );
+        else if ( !strcmp( pWord, "xnor" ) )
+            RetValue = Ver_ParseGateStandard( pMan, VER_GATE_XNOR );
+        else if ( !strcmp( pWord, "not" ) )
+            RetValue = Ver_ParseGateStandard( pMan, VER_GATE_NOT );
+
+        else if ( !strcmp( pWord, "assign" ) )
+            RetValue = Ver_ParseAssign( pMan );
+        else if ( !strcmp( pWord, "always" ) )
+            RetValue = Ver_ParseAlways( pMan );
+        else if ( !strcmp( pWord, "initial" ) )
+            RetValue = Ver_ParseInitial( pMan );
+        else if ( !strcmp( pWord, "endmodule" ) )
+            break;
+        else if ( pMan->pDesign->pLibrary && st_lookup(pMan->pDesign->pLibrary->tModules, pWord, (char**)&pNtkTemp) ) // gate library
+            RetValue = Ver_ParseGate( pMan, pNtkTemp );
+        else if ( pMan->pDesign && st_lookup(pMan->pDesign->tModules, pWord, (char**)&pNtkTemp) ) // current design
+            RetValue = Ver_ParseGate( pMan, pNtkTemp );
+        else
+        {
+            printf( "Cannot find \"%s\".\n", pWord );
+            Ver_StreamSkipToChars( p, ";" );
+            Ver_StreamPopChar(p);
+
+//            sprintf( pMan->sError, "Cannot find \"%s\" in the library.", pWord );
+//            Ver_ParsePrintErrorMessage( pMan );
+//            return 0;
+        }
+        if ( RetValue == 0 )
+            return 0;
+        // skip the comments
+        if ( !Ver_ParseSkipComments( pMan ) )
+            return 0;
+        // get new word
+        pWord = Ver_ParseGetName( pMan );
+        if ( pWord == NULL )
+            return 0;
+    }
+
+    // check if constant 0 net is used
+    pNet = Abc_NtkFindOrCreateNet( pNtk, "1'b0" );
+    if ( Abc_ObjFanoutNum(pNet) == 0 )
+        Abc_NtkDeleteObj(pNet);
+    else
+        Abc_ObjAddFanin( pNet, Abc_NtkCreateNodeConst0(pNtk) );
+    // check if constant 1 net is used
+    pNet = Abc_NtkFindOrCreateNet( pNtk, "1'b1" );
+    if ( Abc_ObjFanoutNum(pNet) == 0 )
+        Abc_NtkDeleteObj(pNet);
+    else
+        Abc_ObjAddFanin( pNet, Abc_NtkCreateNodeConst1(pNtk) );
+
+    // fix the dangling nets
+    Abc_NtkFinalizeRead( pNtk );
+    return 1;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Parses one directive.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+int Ver_ParseSignal( Ver_Man_t * pMan, Ver_SignalType_t SigType )
+{
+    Ver_Stream_t * p = pMan->pReader;
+    Abc_Ntk_t * pNtk = pMan->pNtkCur;
+    char * pWord;
+    char Symbol;
+    while ( 1 )
+    {
+        pWord = Ver_ParseGetName( pMan );
+        if ( pWord == NULL )
+            return 0;
+        if ( SigType == VER_SIG_INPUT || SigType == VER_SIG_INOUT )
+            Ver_ParseCreatePi( pNtk, pWord );
+        if ( SigType == VER_SIG_OUTPUT || SigType == VER_SIG_INOUT )
+            Ver_ParseCreatePo( pNtk, pWord );
+        if ( SigType == VER_SIG_WIRE || SigType == VER_SIG_REG )
+            Abc_NtkFindOrCreateNet( pNtk, pWord );
+        Symbol = Ver_StreamPopChar(p);
+        if ( Symbol == ',' )
+            continue;
+        if ( Symbol == ';' )
+            return 1;
+        break;
+    }
+    sprintf( pMan->sError, "Cannot parse signal line (expected , or ;)." );
+    Ver_ParsePrintErrorMessage( pMan );
+    return 0;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Parses one directive.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+int Ver_ParseAssign( Ver_Man_t * pMan )
+{
+    Ver_Stream_t * p = pMan->pReader;
+    Abc_Ntk_t * pNtk = pMan->pNtkCur;
+    Abc_Obj_t * pNode, * pNet;
+    char * pWord, * pName, * pEquation;
+    Hop_Obj_t * pFunc;
+    char Symbol;
+    int i, Length, fReduction;
+
+    // convert from the mapped netlist into the BDD netlist
+    if ( pNtk->ntkFunc == ABC_FUNC_BLACKBOX )
+    {
+        pNtk->ntkFunc = ABC_FUNC_AIG;
+        assert( pNtk->pManFunc == NULL );
+        pNtk->pManFunc = pMan->pDesign->pManFunc;
+    }
+    else if ( pNtk->ntkFunc != ABC_FUNC_AIG )
+    {
+        sprintf( pMan->sError, "The network %s appears to mapped gates and assign statements. Currently such network are not allowed. One way to fix this problem is to replace assigns by buffers from the library.", pMan->pNtkCur );
+        Ver_ParsePrintErrorMessage( pMan );
+        return 0;
+    }
+
+    while ( 1 )
+    {
+        // get the name of the output signal
+        pWord = Ver_ParseGetName( pMan );
+        if ( pWord == NULL )
+            return 0;
+        // consider the case of reduction operations
+        fReduction = (pWord[0] == '{');
+        if ( fReduction )
+        {
+            pWord++;
+            pWord[strlen(pWord)-1] = 0;
+            assert( pWord[0] != '\\' );
+        }
+        // get the fanout net
+        pNet = Abc_NtkFindNet( pNtk, pWord );
+        if ( pNet == NULL )
+        {
+            sprintf( pMan->sError, "Cannot read the assign statement for %s (output wire is not defined).", pWord );
+            Ver_ParsePrintErrorMessage( pMan );
+            return 0;
+        }
+        // get the equal sign
+        if ( Ver_StreamPopChar(p) != '=' )
+        {
+            sprintf( pMan->sError, "Cannot read the assign statement for %s (expected equality sign).", pWord );
+            Ver_ParsePrintErrorMessage( pMan );
+            return 0;
+        }
+        // skip the comments
+        if ( !Ver_ParseSkipComments( pMan ) )
+            return 0;
+        // get the second name
+        if ( fReduction )
+            pEquation = Ver_StreamGetWord( p, ";" );
+        else
+            pEquation = Ver_StreamGetWord( p, ",;" );
+        if ( pEquation == NULL )
+            return 0;
+
+        // parse the formula
+        if ( fReduction )
+            pFunc = Ver_FormulaReduction( pEquation, pNtk->pManFunc, pMan->vNames, pMan->sError );  
+        else
+            pFunc = Ver_FormulaParser( pEquation, pNtk->pManFunc, pMan->vNames, pMan->vStackFn, pMan->vStackOp, pMan->sError );  
+        if ( pFunc == NULL )
+        {
+            Ver_ParsePrintErrorMessage( pMan );
+            return 0;
+        }
+
+        // create the node with the given inputs
+        pNode = Abc_NtkCreateNode( pMan->pNtkCur );
+        pNode->pData = pFunc;
+        Abc_ObjAddFanin( pNet, pNode );
+        // connect to fanin nets
+        for ( i = 0; i < Vec_PtrSize(pMan->vNames)/2; i++ )
+        {
+            // get the name of this signal
+            Length = (int)Vec_PtrEntry( pMan->vNames, 2*i );
+            pName  = Vec_PtrEntry( pMan->vNames, 2*i + 1 );
+            pName[Length] = 0;
+            // find the corresponding net
+            pNet = Abc_NtkFindNet( pNtk, pName );
+            if ( pNet == NULL )
+            {
+                sprintf( pMan->sError, "Cannot read the assign statement for %s (input wire %d is not defined).", pWord, pName );
+                Ver_ParsePrintErrorMessage( pMan );
+                return 0;
+            }
+            Abc_ObjAddFanin( pNode, pNet );
+        }
+        Symbol = Ver_StreamPopChar(p);
+        if ( Symbol == ',' )
+            continue;
+        if ( Symbol == ';' )
+            return 1;
+    }
+    return 1;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Parses one directive.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+int Ver_ParseAlways( Ver_Man_t * pMan )
+{
+    Ver_Stream_t * p = pMan->pReader;
+    Abc_Ntk_t * pNtk = pMan->pNtkCur;
+    Abc_Obj_t * pNet, * pNet2;
+    char * pWord, * pWord2;
+    char Symbol;
+    // parse the directive 
+    pWord = Ver_ParseGetName( pMan );
+    if ( pWord == NULL )
+        return 0;
+    if ( strcmp( pWord, "begin" ) )
+    {
+        sprintf( pMan->sError, "Cannot parse the always statement (expected \"begin\")." );
+        Ver_ParsePrintErrorMessage( pMan );
+        return 0;
+    }
+    // iterate over the initial states
+    while ( 1 )
+    {
+        // get the name of the output signal
+        pWord = Ver_ParseGetName( pMan );
+        if ( pWord == NULL )
+            return 0;
+        // look for the end of directive
+        if ( !strcmp( pWord, "end" ) )
+            break;
+        // get the fanout net
+        pNet = Abc_NtkFindNet( pNtk, pWord );
+        if ( pNet == NULL )
+        {
+            sprintf( pMan->sError, "Cannot read the always statement for %s (output wire is not defined).", pWord );
+            Ver_ParsePrintErrorMessage( pMan );
+            return 0;
+        }
+        // get the equal sign
+        if ( Ver_StreamPopChar(p) != '=' )
+        {
+            sprintf( pMan->sError, "Cannot read the always statement for %s (expected equality sign).", pWord );
+            Ver_ParsePrintErrorMessage( pMan );
+            return 0;
+        }
+        // skip the comments
+        if ( !Ver_ParseSkipComments( pMan ) )
+            return 0;
+        // get the second name
+        pWord2 = Ver_ParseGetName( pMan );
+        if ( pWord2 == NULL )
+            return 0;
+        // get the fanin net
+        pNet2 = Abc_NtkFindNet( pNtk, pWord2 );
+        if ( pNet2 == NULL )
+        {
+            sprintf( pMan->sError, "Cannot read the always statement for %s (input wire is not defined).", pWord2 );
+            Ver_ParsePrintErrorMessage( pMan );
+            return 0;
+        }
+        // create the latch
+        Ver_ParseCreateLatch( pNtk, pNet2->pData, pNet->pData );
+        // remove the last symbol
+        Symbol = Ver_StreamPopChar(p);
+        assert( Symbol == ';' );
+    }
+    return 1;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Parses one directive.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+int Ver_ParseInitial( Ver_Man_t * pMan )
+{
+    Ver_Stream_t * p = pMan->pReader;
+    Abc_Ntk_t * pNtk = pMan->pNtkCur;
+    Abc_Obj_t * pNode, * pNet;
+    char * pWord, * pEquation;
+    char Symbol;
+    // parse the directive 
+    pWord = Ver_ParseGetName( pMan );
+    if ( pWord == NULL )
+        return 0;
+    if ( strcmp( pWord, "begin" ) )
+    {
+        sprintf( pMan->sError, "Cannot parse the initial statement (expected \"begin\")." );
+        Ver_ParsePrintErrorMessage( pMan );
+        return 0;
+    }
+    // iterate over the initial states
+    while ( 1 )
+    {
+        // get the name of the output signal
+        pWord = Ver_ParseGetName( pMan );
+        if ( pWord == NULL )
+            return 0;
+        // look for the end of directive
+        if ( !strcmp( pWord, "end" ) )
+            break;
+        // get the fanout net
+        pNet = Abc_NtkFindNet( pNtk, pWord );
+        if ( pNet == NULL )
+        {
+            sprintf( pMan->sError, "Cannot read the initial statement for %s (output wire is not defined).", pWord );
+            Ver_ParsePrintErrorMessage( pMan );
+            return 0;
+        }
+        // get the equal sign
+        if ( Ver_StreamPopChar(p) != '=' )
+        {
+            sprintf( pMan->sError, "Cannot read the initial statement for %s (expected equality sign).", pWord );
+            Ver_ParsePrintErrorMessage( pMan );
+            return 0;
+        }
+        // skip the comments
+        if ( !Ver_ParseSkipComments( pMan ) )
+            return 0;
+        // get the second name
+        pEquation = Ver_StreamGetWord( p, ";" );
+        if ( pEquation == NULL )
+            return 0;
+        // find the corresponding latch
+        pNode = Abc_ObjFanin0(pNet);
+        assert( Abc_ObjIsLatch(pNode) );
+        // set the initial state
+        if ( pEquation[0] == '2' )
+            Abc_LatchSetInitDc( pNode );
+        else if ( pEquation[0] == '1')
+            Abc_LatchSetInit1( pNode );
+        else if ( pEquation[0] == '0' )
+            Abc_LatchSetInit0( pNode );
+        else
+        {
+            sprintf( pMan->sError, "Incorrect initial value of the latch %s (expected equality sign).", pWord );
+            Ver_ParsePrintErrorMessage( pMan );
+            return 0;
+        }
+        // remove the last symbol
+        Symbol = Ver_StreamPopChar(p);
+        assert( Symbol == ';' );
+    }
+    return 1;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Parses one directive.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+int Ver_ParseGate( Ver_Man_t * pMan, Abc_Ntk_t * pNtkGate )
+{
+    Ver_Stream_t * p = pMan->pReader;
+    Abc_Ntk_t * pNtk = pMan->pNtkCur;
+    Abc_Obj_t * pNetFormal, * pNetActual;
+    Abc_Obj_t * pObj, * pNode;
+    char * pWord, Symbol, * pGateName;
+    int i, fCompl, fComplUsed = 0;
+    unsigned * pPolarity;
+
+    // clean the PI/PO pointers
+    Abc_NtkForEachPi( pNtkGate, pObj, i )
+        pObj->pCopy = NULL;
+    Abc_NtkForEachPo( pNtkGate, pObj, i )
+        pObj->pCopy = NULL;
+    // parse the directive and set the pointers to the PIs/POs of the gate
+    pWord = Ver_ParseGetName( pMan );
+    if ( pWord == NULL )
+        return 0;
+    // this is gate name - throw it away
+    pGateName = pWord;
+    if ( Ver_StreamPopChar(p) != '(' )
+    {
+        sprintf( pMan->sError, "Cannot parse gate %s (expected opening paranthesis).", pNtkGate->pName );
+        Ver_ParsePrintErrorMessage( pMan );
+        return 0;
+    }
+    // parse pairs of formal/actural inputs
+    while ( 1 )
+    {
+        // process one pair of formal/actual parameters
+        if ( Ver_StreamPopChar(p) != '.' )
+        {
+            sprintf( pMan->sError, "Cannot parse gate %s (expected .).", pNtkGate->pName );
+            Ver_ParsePrintErrorMessage( pMan );
+            return 0;
+        }
+
+        // parse the formal name
+        pWord = Ver_ParseGetName( pMan );
+        if ( pWord == NULL )
+            return 0;
+        // get the formal net
+        if ( Abc_NtkIsNetlist(pNtkGate) )
+            pNetFormal = Abc_NtkFindNet( pNtkGate, pWord );
+        else // if ( Abc_NtkIsStrash(pNtkGate) )
+            assert( 0 );
+        if ( pNetFormal == NULL )
+        {
+            sprintf( pMan->sError, "Formal net is missing in gate %s.", pWord );
+            Ver_ParsePrintErrorMessage( pMan );
+            return 0;
+        }
+
+        // open the paranthesis
+        if ( Ver_StreamPopChar(p) != '(' )
+        {
+            sprintf( pMan->sError, "Cannot formal parameter %s of gate %s (expected opening paranthesis).", pWord, pNtkGate->pName );
+            Ver_ParsePrintErrorMessage( pMan );
+            return 0;
+        }
+
+        // parse the actual name
+        pWord = Ver_ParseGetName( pMan );
+        if ( pWord == NULL )
+            return 0;
+        // check if the name is complemented
+        fCompl = (pWord[0] == '~');
+        if ( fCompl )
+        {
+            fComplUsed = 1;
+            pWord++;
+            if ( pMan->pNtkCur->pData == NULL )
+                pMan->pNtkCur->pData = Extra_MmFlexStart();
+        }
+        // get the actual net
+        pNetActual = Abc_NtkFindNet( pMan->pNtkCur, pWord );
+        if ( pNetActual == NULL )
+        {
+            sprintf( pMan->sError, "Actual net is missing in gate %s.", pWord );
+            Ver_ParsePrintErrorMessage( pMan );
+            return 0;
+        }
+
+        // close the paranthesis
+        if ( Ver_StreamPopChar(p) != ')' )
+        {
+            sprintf( pMan->sError, "Cannot formal parameter %s of gate %s (expected closing paranthesis).", pWord, pNtkGate->pName );
+            Ver_ParsePrintErrorMessage( pMan );
+            return 0;
+        }
+
+        // process the pair
+        if ( Abc_ObjIsPi(Abc_ObjFanin0Ntk(pNetFormal)) )  // PI net (with polarity!)
+            Abc_ObjFanin0Ntk(pNetFormal)->pCopy = Abc_ObjNotCond( pNetActual, fCompl );
+        else if ( Abc_ObjIsPo(Abc_ObjFanout0Ntk(pNetFormal)) )  // P0 net
+        {
+            assert( fCompl == 0 );
+            Abc_ObjFanout0Ntk(pNetFormal)->pCopy = pNetActual; // Abc_ObjNotCond( pNetActual, fCompl );
+        }
+        else
+        {
+            sprintf( pMan->sError, "Cannot match formal net %s with PI or PO of the gate %s.", pWord, pNtkGate->pName );
+            Ver_ParsePrintErrorMessage( pMan );
+            return 0;
+        }
+
+        // check if it is the end of gate
+        Ver_ParseSkipComments( pMan );
+        Symbol = Ver_StreamPopChar(p);
+        if ( Symbol == ')' )
+            break;
+        // skip comma
+        if ( Symbol != ',' )
+        {
+            sprintf( pMan->sError, "Cannot formal parameter %s of gate %s (expected closing paranthesis).", pWord, pNtkGate->pName );
+            Ver_ParsePrintErrorMessage( pMan );
+            return 0;
+        }
+        Ver_ParseSkipComments( pMan );
+    }
+
+    // check if it is the end of gate
+    Ver_ParseSkipComments( pMan );
+    if ( Ver_StreamPopChar(p) != ';' )
+    {
+        sprintf( pMan->sError, "Cannot read gate %s (expected closing semicolumn).", pNtkGate->pName );
+        Ver_ParsePrintErrorMessage( pMan );
+        return 0;
+    }
+
+    // make sure each input net is driven
+    Abc_NtkForEachPi( pNtkGate, pObj, i )
+        if ( pObj->pCopy == NULL )
+        {
+            sprintf( pMan->sError, "Formal input %s of gate %s has no actual input.", Abc_ObjFanout0(pObj)->pData, pNtkGate->pName );
+            Ver_ParsePrintErrorMessage( pMan );
+            return 0;
+        }
+/*
+    // make sure each output net is driving something
+    Abc_NtkForEachPo( pNtkGate, pObj, i )
+        if ( pObj->pCopy == NULL )
+        {
+            sprintf( pMan->sError, "Formal output %s of gate %s has no actual output.", Abc_ObjFanin0(pObj)->pData, pNtkGate->pName );
+            Ver_ParsePrintErrorMessage( pMan );
+            return 0;
+        }
+*/
+
+    // allocate memory to remember the phase
+    pPolarity = NULL;
+    if ( fComplUsed )
+    {
+        int nBytes = 4 * Abc_BitWordNum( Abc_NtkPiNum(pNtkGate) );
+        pPolarity = (unsigned *)Extra_MmFlexEntryFetch( pMan->pNtkCur->pData, nBytes );
+        memset( pPolarity, 0, nBytes );
+    }
+    // create box to represent this gate
+    pNode = Abc_NtkCreateBlackbox( pMan->pNtkCur );
+/*
+    if ( pNode->Id == 57548 )
+    {
+        int x = 0;
+    }
+*/
+    pNode->pNext = (Abc_Obj_t *)pPolarity;
+    pNode->pData = pNtkGate;
+    // connect to fanin nets
+    Abc_NtkForEachPi( pNtkGate, pObj, i )
+    {
+        if ( pPolarity && Abc_ObjIsComplement(pObj->pCopy) )
+        {
+            Abc_InfoSetBit( pPolarity, i );
+            pObj->pCopy = Abc_ObjRegular( pObj->pCopy );
+        }
+        assert( !Abc_ObjIsComplement(pObj->pCopy) );
+        Abc_ObjAddFanin( pNode, pObj->pCopy );
+    }
+    // connect to fanout nets
+    Abc_NtkForEachPo( pNtkGate, pObj, i )
+    {
+        if ( pObj->pCopy )
+            Abc_ObjAddFanin( pObj->pCopy, pNode );
+        else
+            Abc_ObjAddFanin( Abc_NtkFindOrCreateNet(pNtk, NULL), pNode );
+    }
+    return 1;
+}
+
+
+/**Function*************************************************************
+
+  Synopsis    [Parses one directive.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+int Ver_ParseGateStandard( Ver_Man_t * pMan, Ver_GateType_t GateType )
+{
+    Ver_Stream_t * p = pMan->pReader;
+    Hop_Man_t * pAig = pMan->pNtkCur->pManFunc;
+    Abc_Obj_t * pNet, * pNode;
+    char * pWord, Symbol;
+    // this is gate name - throw it away
+    if ( Ver_StreamPopChar(p) != '(' )
+    {
+        sprintf( pMan->sError, "Cannot parse a standard gate (expected opening paranthesis)." );
+        Ver_ParsePrintErrorMessage( pMan );
+        return 0;
+    }
+    Ver_ParseSkipComments( pMan );
+    // create the node
+    pNode = Abc_NtkCreateNode( pMan->pNtkCur );
+    // parse pairs of formal/actural inputs
+    while ( 1 )
+    {
+        // parse the output name
+        pWord = Ver_ParseGetName( pMan );
+        if ( pWord == NULL )
+            return 0;
+        // get the net corresponding to this output
+        pNet = Abc_NtkFindNet( pMan->pNtkCur, pWord );
+        if ( pNet == NULL )
+        {
+            sprintf( pMan->sError, "Net is missing in gate %s.", pWord );
+            Ver_ParsePrintErrorMessage( pMan );
+            return 0;
+        }
+        // if this is the first net, add it as an output
+        if ( Abc_ObjFanoutNum(pNode) == 0 )
+            Abc_ObjAddFanin( pNet, pNode );
+        else
+            Abc_ObjAddFanin( pNode, pNet );
+        // check if it is the end of gate
+        Ver_ParseSkipComments( pMan );
+        Symbol = Ver_StreamPopChar(p);
+        if ( Symbol == ')' )
+            break;
+        // skip comma
+        if ( Symbol != ',' )
+        {
+            sprintf( pMan->sError, "Cannot parse a standard gate %s (expected closing paranthesis).", Abc_ObjName(Abc_ObjFanout0(pNode)) );
+            Ver_ParsePrintErrorMessage( pMan );
+            return 0;
+        }
+        Ver_ParseSkipComments( pMan );
+    }
+    if ( (GateType == VER_GATE_BUF || GateType == VER_GATE_NOT) && Abc_ObjFaninNum(pNode) != 1 )
+    {
+        sprintf( pMan->sError, "Buffer or interver with multiple fanouts %s (currently not supported).", Abc_ObjName(Abc_ObjFanout0(pNode)) );
+        Ver_ParsePrintErrorMessage( pMan );
+        return 0;
+    }
+
+    // check if it is the end of gate
+    Ver_ParseSkipComments( pMan );
+    if ( Ver_StreamPopChar(p) != ';' )
+    {
+        sprintf( pMan->sError, "Cannot read standard gate %s (expected closing semicolumn).", Abc_ObjName(Abc_ObjFanout0(pNode)) );
+        Ver_ParsePrintErrorMessage( pMan );
+        return 0;
+    }
+    // add logic function
+    if ( GateType == VER_GATE_AND || GateType == VER_GATE_NAND )
+        pNode->pData = Hop_CreateAnd( pAig, Abc_ObjFaninNum(pNode) );
+    else if ( GateType == VER_GATE_OR || GateType == VER_GATE_NOR )
+        pNode->pData = Hop_CreateOr( pAig, Abc_ObjFaninNum(pNode) );
+    else if ( GateType == VER_GATE_XOR || GateType == VER_GATE_XNOR )
+        pNode->pData = Hop_CreateExor( pAig, Abc_ObjFaninNum(pNode) );
+    else if ( GateType == VER_GATE_BUF || GateType == VER_GATE_NOT )
+        pNode->pData = Hop_CreateAnd( pAig, Abc_ObjFaninNum(pNode) );
+    if ( GateType == VER_GATE_NAND || GateType == VER_GATE_NOR || GateType == VER_GATE_XNOR || GateType == VER_GATE_NOT )
+        pNode->pData = Hop_Not( pNode->pData );
+    return 1;
+}
+
+
+/**Function*************************************************************
+
+  Synopsis    [Creates PI terminal and net.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Abc_Obj_t * Ver_ParseCreatePi( Abc_Ntk_t * pNtk, char * pName )
+{
+    Abc_Obj_t * pNet, * pTerm;
+    // get the PI net
+    pNet  = Abc_NtkFindNet( pNtk, pName );
+    if ( pNet )
+        printf( "Warning: PI \"%s\" appears twice in the list.\n", pName );
+    pNet  = Abc_NtkFindOrCreateNet( pNtk, pName );
+    // add the PI node
+    pTerm = Abc_NtkCreatePi( pNtk );
+    Abc_ObjAddFanin( pNet, pTerm );
+    return pTerm;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Creates PO terminal and net.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Abc_Obj_t * Ver_ParseCreatePo( Abc_Ntk_t * pNtk, char * pName )
+{
+    Abc_Obj_t * pNet, * pTerm;
+    // get the PO net
+    pNet  = Abc_NtkFindNet( pNtk, pName );
+    if ( pNet && Abc_ObjFaninNum(pNet) == 0 )
+        printf( "Warning: PO \"%s\" appears twice in the list.\n", pName );
+    pNet  = Abc_NtkFindOrCreateNet( pNtk, pName );
+    // add the PO node
+    pTerm = Abc_NtkCreatePo( pNtk );
+    Abc_ObjAddFanin( pTerm, pNet );
+    return pTerm;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Create a latch with the given input/output.]
+
+  Description [By default, the latch value is unknown (ABC_INIT_NONE).]
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Abc_Obj_t * Ver_ParseCreateLatch( Abc_Ntk_t * pNtk, char * pNetLI, char * pNetLO )
+{
+    Abc_Obj_t * pLatch, * pNet;
+    // create a new latch and add it to the network
+    pLatch = Abc_NtkCreateLatch( pNtk );
+    // get the LI net
+    pNet = Abc_NtkFindOrCreateNet( pNtk, pNetLI );
+    Abc_ObjAddFanin( pLatch, pNet );
+    // get the LO net
+    pNet = Abc_NtkFindOrCreateNet( pNtk, pNetLO );
+    Abc_ObjAddFanin( pNet, pLatch );
+    return pLatch;
+}
+
+
+////////////////////////////////////////////////////////////////////////
+///                       END OF FILE                                ///
+////////////////////////////////////////////////////////////////////////
+
+
diff --git a/src/base/ver/verFormula.c b/src/base/ver/verFormula.c
new file mode 100644
index 00000000..cfe3e0c8
--- /dev/null
+++ b/src/base/ver/verFormula.c
@@ -0,0 +1,469 @@
+/**CFile****************************************************************
+
+  FileName    [verFormula.c]
+
+  SystemName  [ABC: Logic synthesis and verification system.]
+
+  PackageName [Verilog parser.]
+
+  Synopsis    [Formula parser to read Verilog assign statements.]
+
+  Author      [Alan Mishchenko]
+  
+  Affiliation [UC Berkeley]
+
+  Date        [Ver. 1.0. Started - August 19, 2006.]
+
+  Revision    [$Id: verFormula.c,v 1.00 2006/08/19 00:00:00 alanmi Exp $]
+
+***********************************************************************/
+
+#include "ver.h"
+
+////////////////////////////////////////////////////////////////////////
+///                        DECLARATIONS                              ///
+////////////////////////////////////////////////////////////////////////
+
+// the list of operation symbols to be used in expressions
+#define VER_PARSE_SYM_OPEN    '('   // opening paranthesis
+#define VER_PARSE_SYM_CLOSE   ')'   // closing paranthesis
+#define VER_PARSE_SYM_CONST0  '0'   // constant 0
+#define VER_PARSE_SYM_CONST1  '1'   // constant 1
+#define VER_PARSE_SYM_NEGBEF1 '!'   // negation before the variable
+#define VER_PARSE_SYM_NEGBEF2 '~'   // negation before the variable
+#define VER_PARSE_SYM_AND     '&'   // logic AND
+#define VER_PARSE_SYM_OR      '|'   // logic OR
+#define VER_PARSE_SYM_XOR     '^'   // logic XOR
+#define VER_PARSE_SYM_MUX1    '?'   // first symbol of MUX
+#define VER_PARSE_SYM_MUX2    ':'   // second symbol of MUX
+
+// the list of opcodes (also specifying operation precedence)
+#define VER_PARSE_OPER_NEG     7    // negation (highest precedence)
+#define VER_PARSE_OPER_AND     6    // logic AND
+#define VER_PARSE_OPER_XOR     5    // logic EXOR   (a'b | ab')   
+#define VER_PARSE_OPER_OR      4    // logic OR
+#define VER_PARSE_OPER_EQU     3    // equvalence   (a'b'| ab )
+#define VER_PARSE_OPER_MUX     2    // MUX(a,b,c)   (ab | a'c )
+#define VER_PARSE_OPER_MARK    1    // OpStack token standing for an opening paranthesis
+
+// these are values of the internal Flag
+#define VER_PARSE_FLAG_START   1    // after the opening parenthesis 
+#define VER_PARSE_FLAG_VAR     2    // after operation is received
+#define VER_PARSE_FLAG_OPER    3    // after operation symbol is received
+#define VER_PARSE_FLAG_ERROR   4    // when error is detected
+
+static Hop_Obj_t * Ver_FormulaParserTopOper( Hop_Man_t * pMan, Vec_Ptr_t * vStackFn, int Oper );
+static int         Ver_FormulaParserFindVar( char * pString, Vec_Ptr_t * vNames );
+
+////////////////////////////////////////////////////////////////////////
+///                     FUNCTION DEFINITIONS                         ///
+////////////////////////////////////////////////////////////////////////
+
+/**Function*************************************************************
+
+  Synopsis    [Parser of the formula encountered in assign statements.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void * Ver_FormulaParser( char * pFormula, void * pMan, Vec_Ptr_t * vNames, Vec_Ptr_t * vStackFn, Vec_Int_t * vStackOp, char * pErrorMessage )
+{
+    Hop_Obj_t * bFunc, * bTemp;
+    char * pTemp;
+    int nParans, Flag;
+    int Oper, Oper1, Oper2;
+    int v;
+
+    // clear the stacks and the names
+    Vec_PtrClear( vNames );
+    Vec_PtrClear( vStackFn );
+    Vec_IntClear( vStackOp );
+
+    // make sure that the number of opening and closing parantheses is the same
+    nParans = 0;
+    for ( pTemp = pFormula; *pTemp; pTemp++ )
+        if ( *pTemp == '(' )
+            nParans++;
+        else if ( *pTemp == ')' )
+            nParans--;
+    if ( nParans != 0 )
+    {
+        sprintf( pErrorMessage, "Parse_FormulaParser(): Different number of opening and closing parantheses ()." );
+        return NULL;
+    }
+ 
+    // add parantheses
+    pTemp = pFormula + strlen(pFormula) + 2;
+    *pTemp-- = 0; *pTemp = ')';
+    while ( --pTemp != pFormula )
+        *pTemp = *(pTemp - 1);
+    *pTemp = '(';
+
+    // perform parsing
+    Flag = VER_PARSE_FLAG_START;
+    for ( pTemp = pFormula; *pTemp; pTemp++ )
+    {
+        switch ( *pTemp )
+        {
+        // skip all spaces, tabs, and end-of-lines
+        case ' ':
+        case '\t':
+        case '\r':
+        case '\n':
+            continue;
+
+        // treat Constant 0 as a variable
+        case VER_PARSE_SYM_CONST0:
+            Vec_PtrPush( vStackFn, Hop_ManConst0(pMan) );  // Cudd_Ref( Hop_ManConst0(pMan) );
+            if ( Flag == VER_PARSE_FLAG_VAR )
+            {
+                sprintf( pErrorMessage, "Parse_FormulaParser(): No operation symbol before constant 0." );
+                Flag = VER_PARSE_FLAG_ERROR; 
+                break;
+            }
+            Flag = VER_PARSE_FLAG_VAR; 
+            break;
+
+        // the same for Constant 1
+        case VER_PARSE_SYM_CONST1:
+            Vec_PtrPush( vStackFn, Hop_ManConst1(pMan) );  //  Cudd_Ref( Hop_ManConst1(pMan) );
+            if ( Flag == VER_PARSE_FLAG_VAR )
+            {
+                sprintf( pErrorMessage, "Parse_FormulaParser(): No operation symbol before constant 1." );
+                Flag = VER_PARSE_FLAG_ERROR; 
+                break;
+            }
+            Flag = VER_PARSE_FLAG_VAR; 
+            break;
+
+        case VER_PARSE_SYM_NEGBEF1:
+        case VER_PARSE_SYM_NEGBEF2:
+            if ( Flag == VER_PARSE_FLAG_VAR )
+            {// if NEGBEF follows a variable, AND is assumed
+                sprintf( pErrorMessage, "Parse_FormulaParser(): Variable before negation." );
+                Flag = VER_PARSE_FLAG_ERROR; 
+                break;
+            }
+            Vec_IntPush( vStackOp, VER_PARSE_OPER_NEG );
+            break;
+
+        case VER_PARSE_SYM_AND:
+        case VER_PARSE_SYM_OR:
+        case VER_PARSE_SYM_XOR:
+        case VER_PARSE_SYM_MUX1:
+        case VER_PARSE_SYM_MUX2:
+            if ( Flag != VER_PARSE_FLAG_VAR )
+            {
+                sprintf( pErrorMessage, "Parse_FormulaParser(): There is no variable before AND, EXOR, or OR." );
+                Flag = VER_PARSE_FLAG_ERROR; 
+                break;
+            }
+            if ( *pTemp == VER_PARSE_SYM_AND )
+                Vec_IntPush( vStackOp, VER_PARSE_OPER_AND );
+            else if ( *pTemp == VER_PARSE_SYM_OR )
+                Vec_IntPush( vStackOp, VER_PARSE_OPER_OR );
+            else if ( *pTemp == VER_PARSE_SYM_XOR )
+                Vec_IntPush( vStackOp, VER_PARSE_OPER_XOR );
+            else if ( *pTemp == VER_PARSE_SYM_MUX1 )
+                Vec_IntPush( vStackOp, VER_PARSE_OPER_MUX );
+//            else if ( *pTemp == VER_PARSE_SYM_MUX2 )
+//                Vec_IntPush( vStackOp, VER_PARSE_OPER_MUX );
+            Flag = VER_PARSE_FLAG_OPER; 
+            break;
+
+        case VER_PARSE_SYM_OPEN:
+            if ( Flag == VER_PARSE_FLAG_VAR )
+            {
+                sprintf( pErrorMessage, "Parse_FormulaParser(): Variable before a paranthesis." );
+                Flag = VER_PARSE_FLAG_ERROR; 
+                break;
+            }
+            Vec_IntPush( vStackOp, VER_PARSE_OPER_MARK );
+            // after an opening bracket, it feels like starting over again
+            Flag = VER_PARSE_FLAG_START; 
+            break;
+
+        case VER_PARSE_SYM_CLOSE:
+            if ( Vec_IntSize( vStackOp ) )
+            {
+                while ( 1 )
+                {
+                    if ( !Vec_IntSize( vStackOp ) )
+                    {
+                        sprintf( pErrorMessage, "Parse_FormulaParser(): There is no opening paranthesis\n" );
+                        Flag = VER_PARSE_FLAG_ERROR; 
+                        break;
+                    }
+                    Oper = Vec_IntPop( vStackOp );
+                    if ( Oper == VER_PARSE_OPER_MARK )
+                        break;
+                    // skip the second MUX operation
+//                    if ( Oper == VER_PARSE_OPER_MUX2 )
+//                    {
+//                        Oper = Vec_IntPop( vStackOp );
+//                        assert( Oper == VER_PARSE_OPER_MUX1 );
+//                    }
+
+                    // perform the given operation
+                    if ( Ver_FormulaParserTopOper( pMan, vStackFn, Oper ) == NULL )
+                    {
+                        sprintf( pErrorMessage, "Parse_FormulaParser(): Unknown operation\n" );
+                        return NULL;
+                    }
+                }
+            }
+            else
+            {
+                sprintf( pErrorMessage, "Parse_FormulaParser(): There is no opening paranthesis\n" );
+                Flag = VER_PARSE_FLAG_ERROR; 
+                break;
+            }
+            if ( Flag != VER_PARSE_FLAG_ERROR )
+                Flag = VER_PARSE_FLAG_VAR; 
+            break;
+
+
+        default:
+            // scan the next name
+            v = Ver_FormulaParserFindVar( pTemp, vNames );
+            if ( *pTemp == '\\' )
+                pTemp++;
+            pTemp += (int)Vec_PtrEntry( vNames, 2*v ) - 1;
+
+            // assume operation AND, if vars follow one another
+            if ( Flag == VER_PARSE_FLAG_VAR )
+            {
+                sprintf( pErrorMessage, "Parse_FormulaParser(): Incorrect state." );
+                return NULL;
+            }
+            bTemp = Hop_IthVar( pMan, v );
+            Vec_PtrPush( vStackFn, bTemp ); //  Cudd_Ref( bTemp );
+            Flag = VER_PARSE_FLAG_VAR; 
+            break;
+        }
+
+        if ( Flag == VER_PARSE_FLAG_ERROR )
+            break;      // error exit
+        else if ( Flag == VER_PARSE_FLAG_START )
+            continue;  //  go on parsing
+        else if ( Flag == VER_PARSE_FLAG_VAR )
+            while ( 1 )
+            {  // check if there are negations in the OpStack     
+                if ( !Vec_IntSize(vStackOp) )
+                    break;
+                Oper = Vec_IntPop( vStackOp );
+                if ( Oper != VER_PARSE_OPER_NEG )
+                {
+                    Vec_IntPush( vStackOp, Oper );
+                    break;
+                }
+                else
+                {
+//                      Vec_PtrPush( vStackFn, Cudd_Not(Vec_PtrPop(vStackFn)) );
+                      Vec_PtrPush( vStackFn, Hop_Not(Vec_PtrPop(vStackFn)) );
+                }
+            }
+        else // if ( Flag == VER_PARSE_FLAG_OPER )
+            while ( 1 )
+            {  // execute all the operations in the OpStack
+               // with precedence higher or equal than the last one
+                Oper1 = Vec_IntPop( vStackOp ); // the last operation
+                if ( !Vec_IntSize(vStackOp) ) 
+                {  // if it is the only operation, push it back
+                    Vec_IntPush( vStackOp, Oper1 );
+                    break;
+                }
+                Oper2 = Vec_IntPop( vStackOp ); // the operation before the last one
+                if ( Oper2 >= Oper1 && !(Oper1 == Oper2 && Oper1 == VER_PARSE_OPER_MUX) )  
+                {  // if Oper2 precedence is higher or equal, execute it
+                    if ( Ver_FormulaParserTopOper( pMan, vStackFn, Oper2 ) == NULL )
+                    {
+                        sprintf( pErrorMessage, "Parse_FormulaParser(): Unknown operation\n" );
+                        return NULL;
+                    }
+                    Vec_IntPush( vStackOp,  Oper1 );     // push the last operation back
+                }
+                else
+                {  // if Oper2 precedence is lower, push them back and done
+                    Vec_IntPush( vStackOp, Oper2 );
+                    Vec_IntPush( vStackOp, Oper1 );
+                    break;
+                }
+            }
+    }
+
+    if ( Flag != VER_PARSE_FLAG_ERROR )
+    {
+        if ( Vec_PtrSize(vStackFn) )
+        {    
+            bFunc = Vec_PtrPop(vStackFn);
+            if ( !Vec_PtrSize(vStackFn) )
+                if ( !Vec_IntSize(vStackOp) )
+                {
+//                    Cudd_Deref( bFunc );
+                    return bFunc;
+                }
+                else
+                    sprintf( pErrorMessage, "Parse_FormulaParser(): Something is left in the operation stack\n" );
+            else
+                sprintf( pErrorMessage, "Parse_FormulaParser(): Something is left in the function stack\n" );
+        }
+        else
+            sprintf( pErrorMessage, "Parse_FormulaParser(): The input string is empty\n" );
+    }
+//    Cudd_Ref( bFunc );
+//    Cudd_RecursiveDeref( dd, bFunc );
+    return NULL;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Performs the operation on the top entries in the stack.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Hop_Obj_t * Ver_FormulaParserTopOper( Hop_Man_t * pMan, Vec_Ptr_t * vStackFn, int Oper )
+{
+    Hop_Obj_t * bArg0, * bArg1, * bArg2, * bFunc;
+    // perform the given operation
+    bArg2 = Vec_PtrPop( vStackFn );
+    bArg1 = Vec_PtrPop( vStackFn );
+    if ( Oper == VER_PARSE_OPER_AND )
+        bFunc = Hop_And( pMan, bArg1, bArg2 );
+    else if ( Oper == VER_PARSE_OPER_XOR )
+        bFunc = Hop_Exor( pMan, bArg1, bArg2 );
+    else if ( Oper == VER_PARSE_OPER_OR )
+        bFunc = Hop_Or( pMan, bArg1, bArg2 );
+    else if ( Oper == VER_PARSE_OPER_EQU )
+        bFunc = Hop_Not( Hop_Exor( pMan, bArg1, bArg2 ) );
+    else if ( Oper == VER_PARSE_OPER_MUX )
+    {
+        bArg0 = Vec_PtrPop( vStackFn );
+//        bFunc = Cudd_bddIte( dd, bArg0, bArg1, bArg2 );  Cudd_Ref( bFunc );
+        bFunc = Hop_Mux( pMan, bArg0, bArg1, bArg2 ); 
+//        Cudd_RecursiveDeref( dd, bArg0 );
+//        Cudd_Deref( bFunc );
+    }
+    else
+        return NULL;
+//    Cudd_Ref( bFunc );
+//    Cudd_RecursiveDeref( dd, bArg1 );
+//    Cudd_RecursiveDeref( dd, bArg2 );
+    Vec_PtrPush( vStackFn,  bFunc );
+    return bFunc;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Returns the index of the new variable found.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+int Ver_FormulaParserFindVar( char * pString, Vec_Ptr_t * vNames )
+{
+    char * pTemp, * pTemp2;
+    int nLength, nLength2, i;
+    // start the string
+    pTemp = pString;
+    // find the end of the string delimited by other characters
+    if ( *pTemp == '\\' )
+    {
+        pString++;
+        while ( *pTemp && *pTemp != ' ' )
+            pTemp++;
+    }
+    else
+    {
+        while ( *pTemp && *pTemp != ' ' && *pTemp != '\t' && *pTemp != '\r' && *pTemp != '\n' && *pTemp != ',' && *pTemp != '}' && 
+                *pTemp != VER_PARSE_SYM_OPEN && *pTemp != VER_PARSE_SYM_CLOSE && 
+                *pTemp != VER_PARSE_SYM_NEGBEF1 && *pTemp != VER_PARSE_SYM_NEGBEF2 && 
+                *pTemp != VER_PARSE_SYM_AND && *pTemp != VER_PARSE_SYM_OR && *pTemp != VER_PARSE_SYM_XOR && 
+                *pTemp != VER_PARSE_SYM_MUX1 && *pTemp != VER_PARSE_SYM_MUX2 )
+                pTemp++;
+    }
+    // look for this string in the array
+    nLength = pTemp - pString;
+    for ( i = 0; i < Vec_PtrSize(vNames)/2; i++ )
+    {
+        nLength2 = (int)Vec_PtrEntry( vNames, 2*i + 0 );
+        if ( nLength2 != nLength )
+            continue;
+        pTemp2   = Vec_PtrEntry( vNames, 2*i + 1 );
+        if ( strncmp( pString, pTemp2, nLength ) )
+            continue;
+        return i;
+    }
+    // could not find - add and return the number
+    Vec_PtrPush( vNames, (void *)nLength );
+    Vec_PtrPush( vNames, pString );
+    return i;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Returns the AIG representation of the reduction formula.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void * Ver_FormulaReduction( char * pFormula, void * pMan, Vec_Ptr_t * vNames, char * pErrorMessage )
+{
+    Hop_Obj_t * pRes;
+    int v, fCompl;
+    char Symbol;
+
+    // get the operation
+    Symbol = *pFormula++;
+    fCompl = ( Symbol == '~' );
+    if ( fCompl )
+        Symbol = *pFormula++;
+    // check the operation
+    if ( Symbol != '&' && Symbol != '|' && Symbol != '^' )
+    {
+        sprintf( pErrorMessage, "Ver_FormulaReduction(): Unknown operation (%c)\n", Symbol );
+        return NULL;
+    }
+    // skip the brace
+    while ( *pFormula++ != '{' );
+    // parse the names
+    Vec_PtrClear( vNames );
+    while ( *pFormula != '}' )
+    {
+        v = Ver_FormulaParserFindVar( pFormula, vNames );
+        pFormula += (int)Vec_PtrEntry( vNames, 2*v );
+        while ( *pFormula == ' ' || *pFormula == ',' )
+            pFormula++;
+    }
+    // compute the function
+    if ( Symbol == '&' )
+        pRes = Hop_CreateAnd( pMan, Vec_PtrSize(vNames)/2 );
+    else if ( Symbol == '|' )
+        pRes = Hop_CreateOr( pMan, Vec_PtrSize(vNames)/2 );
+    else if ( Symbol == '^' )
+        pRes = Hop_CreateExor( pMan, Vec_PtrSize(vNames)/2 );
+    return Hop_NotCond( pRes, fCompl );
+}
+
+////////////////////////////////////////////////////////////////////////
+///                       END OF FILE                                ///
+////////////////////////////////////////////////////////////////////////
+
+
diff --git a/src/base/ver/verParse.c b/src/base/ver/verParse.c
new file mode 100644
index 00000000..8a78e75b
--- /dev/null
+++ b/src/base/ver/verParse.c
@@ -0,0 +1,115 @@
+/**CFile****************************************************************
+
+  FileName    [verParse.c]
+
+  SystemName  [ABC: Logic synthesis and verification system.]
+
+  PackageName [Verilog parser.]
+
+  Synopsis    [Performs some Verilog parsing tasks.]
+
+  Author      [Alan Mishchenko]
+  
+  Affiliation [UC Berkeley]
+
+  Date        [Ver. 1.0. Started - August 19, 2006.]
+
+  Revision    [$Id: verParse.c,v 1.00 2006/08/19 00:00:00 alanmi Exp $]
+
+***********************************************************************/
+
+#include "ver.h"
+
+////////////////////////////////////////////////////////////////////////
+///                        DECLARATIONS                              ///
+////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////
+///                     FUNCTION DEFINITIONS                         ///
+////////////////////////////////////////////////////////////////////////
+
+/**Function*************************************************************
+
+  Synopsis    [Skips the comments of they are present.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+int Ver_ParseSkipComments( Ver_Man_t * pMan )
+{
+    Ver_Stream_t * p = pMan->pReader;
+    char Symbol;
+    // skip spaces
+    Ver_StreamSkipChars( p, " \t\n\r" );
+    if ( !Ver_StreamIsOkey(pMan->pReader) )
+        return 1;
+    // read the first symbol
+    Symbol = Ver_StreamScanChar( p );
+    if ( Symbol != '/' )
+        return 1;
+    Ver_StreamPopChar( p );
+    // read the second symbol
+    Symbol = Ver_StreamScanChar( p );
+    if ( Symbol == '/' )
+    { // skip till the end of line
+        Ver_StreamSkipToChars( p, "\n" );
+        return Ver_ParseSkipComments( pMan );
+    }
+    if ( Symbol == '*' )
+    { // skip till the next occurance of */
+        Ver_StreamPopChar( p );
+        do {
+            Ver_StreamSkipToChars( p, "*" );
+            Ver_StreamPopChar( p );
+        } while ( Ver_StreamScanChar( p ) != '/' );
+        Ver_StreamPopChar( p );
+        return Ver_ParseSkipComments( pMan );
+    }
+    sprintf( pMan->sError, "Cannot parse after symbol \"/\"." );
+    Ver_ParsePrintErrorMessage( pMan );
+    return 0;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Parses a Verilog name that can be being with a slash.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+char * Ver_ParseGetName( Ver_Man_t * pMan )
+{
+    Ver_Stream_t * p = pMan->pReader;
+    char Symbol;
+    char * pWord;
+    if ( !Ver_StreamIsOkey(p) )
+        return NULL;
+    if ( !Ver_ParseSkipComments( pMan ) )
+        return NULL;
+    Symbol = Ver_StreamScanChar( p );
+    if ( Symbol == '\\' )
+    {
+        Ver_StreamPopChar( p );
+        pWord = Ver_StreamGetWord( p, " " );
+    }
+    else
+        pWord = Ver_StreamGetWord( p, " \t\n\r(),;" );
+    if ( !Ver_ParseSkipComments( pMan ) )
+        return NULL;
+    return pWord;
+}
+
+
+////////////////////////////////////////////////////////////////////////
+///                       END OF FILE                                ///
+////////////////////////////////////////////////////////////////////////
+
+
diff --git a/src/base/ver/verStream.c b/src/base/ver/verStream.c
new file mode 100644
index 00000000..7956b13c
--- /dev/null
+++ b/src/base/ver/verStream.c
@@ -0,0 +1,435 @@
+/**CFile****************************************************************
+
+  FileName    [verStream.c]
+
+  SystemName  [ABC: Logic synthesis and verification system.]
+
+  PackageName [Verilog parser.]
+
+  Synopsis    [Input file stream, which knows nothing about Verilog.]
+
+  Author      [Alan Mishchenko]
+  
+  Affiliation [UC Berkeley]
+
+  Date        [Ver. 1.0. Started - August 19, 2006.]
+
+  Revision    [$Id: verStream.c,v 1.00 2006/08/19 00:00:00 alanmi Exp $]
+
+***********************************************************************/
+
+#include "ver.h"
+
+////////////////////////////////////////////////////////////////////////
+///                        DECLARATIONS                              ///
+////////////////////////////////////////////////////////////////////////
+
+#define VER_BUFFER_SIZE        1048576    // 1M   - size of the data chunk stored in memory
+#define VER_OFFSET_SIZE           4096    // 4K   - load new data when less than this is left
+#define VER_WORD_SIZE             4096    // 4K   - the largest token that can be returned
+
+#define VER_MINIMUM(a,b)       (((a) < (b))? (a) : (b))
+
+struct Ver_Stream_t_
+{
+    // the input file
+    char *           pFileName;     // the input file name
+    FILE *           pFile;         // the input file pointer
+    int              nFileSize;     // the total number of bytes in the file
+    int              nFileRead;     // the number of bytes currently read from file
+    int              nLineCounter;  // the counter of lines processed
+    // temporary storage for data 
+    char *           pBuffer;       // the buffer
+    int              nBufferSize;   // the size of the buffer
+    char *           pBufferCur;    // the current reading position
+    char *           pBufferEnd;    // the first position not used by currently loaded data
+    char *           pBufferStop;   // the position where loading new data will be done
+    // tokens given to the user
+    char             pChars[VER_WORD_SIZE+5]; // temporary storage for a word (plus end-of-string and two parantheses)
+    int              nChars;        // the total number of characters in the word
+    // status of the parser
+    int              fStop;         // this flag goes high when the end of file is reached
+};
+
+static void Ver_StreamReload( Ver_Stream_t * p );
+
+////////////////////////////////////////////////////////////////////////
+///                     FUNCTION DEFINITIONS                         ///
+////////////////////////////////////////////////////////////////////////
+
+/**Function*************************************************************
+
+  Synopsis    [Starts the file reader for the given file.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Ver_Stream_t * Ver_StreamAlloc( char * pFileName )
+{
+    Ver_Stream_t * p;
+    FILE * pFile;
+    int nCharsToRead;
+    // check if the file can be opened
+    pFile = fopen( pFileName, "rb" );
+    if ( pFile == NULL )
+    {
+        printf( "Ver_StreamAlloc(): Cannot open input file \"%s\".\n", pFileName );
+        return NULL;
+    }
+    // start the file reader    
+    p = ALLOC( Ver_Stream_t, 1 );
+    memset( p, 0, sizeof(Ver_Stream_t) );
+    p->pFileName   = pFileName;
+    p->pFile       = pFile;
+    // get the file size, in bytes
+    fseek( pFile, 0, SEEK_END );  
+    p->nFileSize = ftell( pFile );  
+    rewind( pFile ); 
+    // allocate the buffer
+    p->pBuffer = ALLOC( char, VER_BUFFER_SIZE+1 );
+    p->nBufferSize = VER_BUFFER_SIZE;
+    p->pBufferCur  = p->pBuffer;
+    // determine how many chars to read
+    nCharsToRead = VER_MINIMUM(p->nFileSize, VER_BUFFER_SIZE);
+    // load the first part into the buffer
+    fread( p->pBuffer, nCharsToRead, 1, p->pFile );
+    p->nFileRead = nCharsToRead;
+    // set the ponters to the end and the stopping point
+    p->pBufferEnd  = p->pBuffer + nCharsToRead;
+    p->pBufferStop = (p->nFileRead == p->nFileSize)? p->pBufferEnd : p->pBuffer + VER_BUFFER_SIZE - VER_OFFSET_SIZE;
+    // start the arrays
+    p->nLineCounter = 1; // 1-based line counting
+    return p;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Loads new data into the file reader.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Ver_StreamReload( Ver_Stream_t * p )
+{
+    int nCharsUsed, nCharsToRead;
+    assert( !p->fStop );
+    assert( p->pBufferCur > p->pBufferStop );
+    assert( p->pBufferCur < p->pBufferEnd );
+    // figure out how many chars are still not processed
+    nCharsUsed = p->pBufferEnd - p->pBufferCur;
+    // move the remaining data to the beginning of the buffer
+    memmove( p->pBuffer, p->pBufferCur, nCharsUsed );
+    p->pBufferCur = p->pBuffer;
+    // determine how many chars we will read
+    nCharsToRead = VER_MINIMUM( p->nBufferSize - nCharsUsed, p->nFileSize - p->nFileRead );
+    // read the chars
+    fread( p->pBuffer + nCharsUsed, nCharsToRead, 1, p->pFile );
+    p->nFileRead += nCharsToRead;
+    // set the ponters to the end and the stopping point
+    p->pBufferEnd  = p->pBuffer + nCharsUsed + nCharsToRead;
+    p->pBufferStop = (p->nFileRead == p->nFileSize)? p->pBufferEnd : p->pBuffer + VER_BUFFER_SIZE - VER_OFFSET_SIZE;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Stops the file reader.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Ver_StreamFree( Ver_Stream_t * p )
+{
+    if ( p->pFile )
+        fclose( p->pFile );
+    FREE( p->pBuffer );
+    free( p );
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Returns the file size.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+char * Ver_StreamGetFileName( Ver_Stream_t * p )
+{
+    return p->pFileName;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Returns the file size.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+int Ver_StreamGetFileSize( Ver_Stream_t * p )
+{
+    return p->nFileSize;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Returns the current reading position.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+int Ver_StreamGetCurPosition( Ver_Stream_t * p )
+{
+    return p->nFileRead - (p->pBufferEnd - p->pBufferCur);
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Returns the line number for the given token.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+int Ver_StreamGetLineNumber( Ver_Stream_t * p )
+{
+    return p->nLineCounter;
+}
+
+
+
+/**Function*************************************************************
+
+  Synopsis    [Returns current symbol.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+int Ver_StreamIsOkey( Ver_Stream_t * p )
+{
+    return !p->fStop;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Returns current symbol.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+char Ver_StreamScanChar( Ver_Stream_t * p )
+{
+    assert( !p->fStop );
+    return *p->pBufferCur;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Returns current symbol and moves to the next.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+char Ver_StreamPopChar( Ver_Stream_t * p )
+{
+    assert( !p->fStop );
+    // check if the new data should to be loaded
+    if ( p->pBufferCur > p->pBufferStop )
+        Ver_StreamReload( p );
+    // check if there are symbols left
+    if ( p->pBufferCur == p->pBufferEnd ) // end of file
+    {
+        p->fStop = 1;
+        return -1;
+    }
+    return *p->pBufferCur++;
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Skips the current symbol and all symbols from the list.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Ver_StreamSkipChars( Ver_Stream_t * p, char * pCharsToSkip )
+{
+    char * pChar, * pTemp;
+    assert( !p->fStop );
+    assert( pCharsToSkip != NULL );
+    // check if the new data should to be loaded
+    if ( p->pBufferCur > p->pBufferStop )
+        Ver_StreamReload( p );
+    // skip the symbols
+    for ( pChar = p->pBufferCur; pChar < p->pBufferEnd; pChar++ )
+    {
+        // count the lines
+        if ( *pChar == '\n' )
+            p->nLineCounter++;
+        // skip symbols as long as they are in the list
+        for ( pTemp = pCharsToSkip; *pTemp; pTemp++ )
+            if ( *pChar == *pTemp )
+                break;
+        if ( *pTemp == 0 ) // pChar is not found in the list
+        {
+            p->pBufferCur = pChar;
+            return;
+        }
+    }
+    // the file is finished or the last part continued 
+    // through VER_OFFSET_SIZE chars till the end of the buffer
+    if ( p->pBufferStop == p->pBufferEnd ) // end of file
+    {
+        p->fStop = 1;
+        return;
+    }
+    printf( "Ver_StreamSkipSymbol() failed to parse the file \"%s\".\n", p->pFileName );
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Skips all symbols until encountering one from the list.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Ver_StreamSkipToChars( Ver_Stream_t * p, char * pCharsToStop )
+{
+    char * pChar, * pTemp;
+    assert( !p->fStop );
+    assert( pCharsToStop != NULL );
+    // check if the new data should to be loaded
+    if ( p->pBufferCur > p->pBufferStop )
+        Ver_StreamReload( p );
+    // skip the symbols
+    for ( pChar = p->pBufferCur; pChar < p->pBufferEnd; pChar++ )
+    {
+        // count the lines
+        if ( *pChar == '\n' )
+            p->nLineCounter++;
+        // skip symbols as long as they are NOT in the list
+        for ( pTemp = pCharsToStop; *pTemp; pTemp++ )
+            if ( *pChar == *pTemp )
+                break;
+        if ( *pTemp == 0 ) // pChar is not found in the list
+            continue;
+        // the symbol is found - move position and return
+        p->pBufferCur = pChar;
+        return;
+    }
+    // the file is finished or the last part continued 
+    // through VER_OFFSET_SIZE chars till the end of the buffer
+    if ( p->pBufferStop == p->pBufferEnd ) // end of file
+    {
+        p->fStop = 1;
+        return;
+    }
+    printf( "Ver_StreamSkipToSymbol() failed to parse the file \"%s\".\n", p->pFileName );
+}
+
+/**Function*************************************************************
+
+  Synopsis    [Returns current word delimited by the set of symbols.]
+
+  Description [Modifies the stream by inserting 0 at the first encounter
+  of one of the symbols in the list.]
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+char * Ver_StreamGetWord( Ver_Stream_t * p, char * pCharsToStop )
+{
+    char * pChar, * pTemp;
+    if ( p->fStop )
+        return NULL;
+    assert( pCharsToStop != NULL );
+    // check if the new data should to be loaded
+    if ( p->pBufferCur > p->pBufferStop )
+        Ver_StreamReload( p );
+    // skip the symbols
+    p->nChars = 0;
+    for ( pChar = p->pBufferCur; pChar < p->pBufferEnd; pChar++ )
+    {
+        // count the lines
+        if ( *pChar == '\n' )
+            p->nLineCounter++;
+        // skip symbols as long as they are NOT in the list
+        for ( pTemp = pCharsToStop; *pTemp; pTemp++ )
+            if ( *pChar == *pTemp )
+                break;
+        if ( *pTemp == 0 ) // pChar is not found in the list
+        {
+            p->pChars[p->nChars++] = *pChar;
+            if ( p->nChars == VER_WORD_SIZE )
+                return NULL;
+            continue;
+        }
+        // the symbol is found - move the position, set the word end, return the word
+        p->pBufferCur = pChar;
+        p->pChars[p->nChars] = 0;
+        return p->pChars;
+    }
+    // the file is finished or the last part continued 
+    // through VER_OFFSET_SIZE chars till the end of the buffer
+    if ( p->pBufferStop == p->pBufferEnd ) // end of file
+    {
+        p->fStop = 1;
+        p->pChars[p->nChars] = 0;
+        return p->pChars;
+    }
+    printf( "Ver_StreamGetWord() failed to parse the file \"%s\".\n", p->pFileName );
+    return NULL;
+}
+
+////////////////////////////////////////////////////////////////////////
+///                       END OF FILE                                ///
+////////////////////////////////////////////////////////////////////////
+
+
diff --git a/src/base/ver/verWords.c b/src/base/ver/verWords.c
new file mode 100644
index 00000000..f9d27010
--- /dev/null
+++ b/src/base/ver/verWords.c
@@ -0,0 +1,48 @@
+/**CFile****************************************************************
+
+  FileName    [verWords.c]
+
+  SystemName  [ABC: Logic synthesis and verification system.]
+
+  PackageName [Verilog parser.]
+
+  Synopsis    [Handles keywords that are currently supported.]
+
+  Author      [Alan Mishchenko]
+  
+  Affiliation [UC Berkeley]
+
+  Date        [Ver. 1.0. Started - August 19, 2006.]
+
+  Revision    [$Id: verWords.c,v 1.00 2006/08/19 00:00:00 alanmi Exp $]
+
+***********************************************************************/
+
+#include "ver.h"
+
+////////////////////////////////////////////////////////////////////////
+///                        DECLARATIONS                              ///
+////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////
+///                     FUNCTION DEFINITIONS                         ///
+////////////////////////////////////////////////////////////////////////
+
+/**Function*************************************************************
+
+  Synopsis    []
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+
+
+////////////////////////////////////////////////////////////////////////
+///                       END OF FILE                                ///
+////////////////////////////////////////////////////////////////////////
+
+
diff --git a/src/base/ver/ver_.c b/src/base/ver/ver_.c
new file mode 100644
index 00000000..76599dac
--- /dev/null
+++ b/src/base/ver/ver_.c
@@ -0,0 +1,48 @@
+/**CFile****************************************************************
+
+  FileName    [ver_.c]
+
+  SystemName  [ABC: Logic synthesis and verification system.]
+
+  PackageName [Verilog parser.]
+
+  Synopsis    [Parses several flavors of structural Verilog.]
+
+  Author      [Alan Mishchenko]
+  
+  Affiliation [UC Berkeley]
+
+  Date        [Ver. 1.0. Started - August 19, 2006.]
+
+  Revision    [$Id: ver_.c,v 1.00 2006/08/19 00:00:00 alanmi Exp $]
+
+***********************************************************************/
+
+#include "ver.h"
+
+////////////////////////////////////////////////////////////////////////
+///                        DECLARATIONS                              ///
+////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////
+///                     FUNCTION DEFINITIONS                         ///
+////////////////////////////////////////////////////////////////////////
+
+/**Function*************************************************************
+
+  Synopsis    []
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+
+
+////////////////////////////////////////////////////////////////////////
+///                       END OF FILE                                ///
+////////////////////////////////////////////////////////////////////////
+
+