Version abc80130

1 files changed, 14 insertions, 35 deletions

diff --git a/src/map/fpga/fpgaCore.c b/src/map/fpga/fpgaCore.c
index 634a8eb1..9ca65379 100644
--- a/src/map/fpga/fpgaCore.c
+++ b/src/map/fpga/fpgaCore.c
@@ -24,12 +24,8 @@
 
 static int  Fpga_MappingPostProcess( Fpga_Man_t * p );
 
-extern int s_MappingTime;
-extern int s_MappingMem;
-
-
 ////////////////////////////////////////////////////////////////////////
-///                     FUNCTION DEFINITIONS                         ///
+///                     FUNCTION DEFITIONS                           ///
 ////////////////////////////////////////////////////////////////////////
 
 /**Function*************************************************************
@@ -50,7 +46,7 @@ extern int s_MappingMem;
 int Fpga_Mapping( Fpga_Man_t * p )
 {
     int clk, clkTotal = clock();
- 
+
     // collect the nodes reachable from POs in the DFS order (including the choices)
     p->vAnds = Fpga_MappingDfs( p, 1 );
     Fpga_ManReportChoices( p ); // recomputes levels
@@ -68,23 +64,19 @@ int Fpga_Mapping( Fpga_Man_t * p )
     p->timeMatch = clock() - clk;
 
     // perform area recovery
-    clk = clock();
-    if ( !Fpga_MappingPostProcess( p ) )
-        return 0;
-    p->timeRecover = clock() - clk;
+    if ( p->fAreaRecovery )
+    {
+        clk = clock();
+        if ( !Fpga_MappingPostProcess( p ) )
+            return 0;
+        p->timeRecover = clock() - clk;
+    }
 //PRT( "Total mapping time", clock() - clkTotal );
 
-    s_MappingTime = clock() - clkTotal;
-    s_MappingMem = Fpga_CutCountAll(p) * (sizeof(Fpga_Cut_t) - sizeof(int) * (FPGA_MAX_LEAVES - p->nVarsMax));
-
     // print the AI-graph used for mapping
     //Fpga_ManShow( p, "test" );
-//    if ( p->fVerbose )
-//        Fpga_MappingPrintOutputArrivals( p );
     if ( p->fVerbose )
-    {
-        PRT( "Total time", clock() - clkTotal );
-    }
+        Fpga_MappingPrintOutputArrivals( p );
     return 1;
 }
 
@@ -96,7 +88,7 @@ int Fpga_Mapping( Fpga_Man_t * p )
   It iterates the loop, in which the required times are computed and
   the mapping is updated. It is conceptually similar to the paper: 
   V. Manohararajah, S. D. Brown, Z. G. Vranesic, Heuristics for area 
-  minimization in LUT-based FPGA technology mapping. Proc. IWLS '04.]
+  minimization in LUT-based FGPA technology mapping. Proc. IWLS '04.]
                
   SideEffects []
 
@@ -105,15 +97,12 @@ int Fpga_Mapping( Fpga_Man_t * p )
 ***********************************************************************/
 int Fpga_MappingPostProcess( Fpga_Man_t * p )
 {
-    int fShowSwitching    = 0;
+    int fShowSwitching    = 1;
     int fRecoverAreaFlow  = 1;
     int fRecoverArea      = 1;
     float aAreaTotalCur, aAreaTotalCur2;
     int Iter, clk;
 
-//if ( p->fVerbose )
-//    printf( "Best clock period = %5.2f\n", Fpga_TimeComputeArrivalMax(p) );
-
     // compute area, set references, and collect nodes used in the mapping
     Iter = 1;
     aAreaTotalCur = Fpga_MappingSetRefsAndArea( p );
@@ -122,20 +111,14 @@ if ( p->fVerbose )
 printf( "Iteration %dD :  Area = %8.1f  ", Iter++, aAreaTotalCur );
 if ( fShowSwitching )
 printf( "Switch = %8.1f  ", Fpga_MappingGetSwitching(p,p->vMapping) );
-else
-printf( "Delay = %5.2f  ", Fpga_TimeComputeArrivalMax(p) );
-
 PRT( "Time", p->timeMatch );
 }
 
-    if ( !p->fAreaRecovery )
-        return 1;
-
     if ( fRecoverAreaFlow )
     {
 clk = clock();
         // compute the required times and the fanouts
-        Fpga_TimeComputeRequiredGlobal( p, 1 );
+        Fpga_TimeComputeRequiredGlobal( p );
         // remap topologically
         Fpga_MappingMatches( p, 0 );
         // get the resulting area
@@ -148,8 +131,6 @@ if ( p->fVerbose )
 printf( "Iteration %dF :  Area = %8.1f  ", Iter++, aAreaTotalCur );
 if ( fShowSwitching )
 printf( "Switch = %8.1f  ", Fpga_MappingGetSwitching(p,p->vMapping) );
-else
-printf( "Delay = %5.2f  ", Fpga_TimeComputeArrivalMax(p) );
 PRT( "Time", clock() - clk );
 }
     }
@@ -162,7 +143,7 @@ PRT( "Time", clock() - clk );
     {
 clk = clock();
         // compute the required times and the fanouts
-        Fpga_TimeComputeRequiredGlobal( p, 0 );
+        Fpga_TimeComputeRequiredGlobal( p );
         // remap topologically
         if ( p->fSwitching )
             Fpga_MappingMatchesSwitch( p );
@@ -175,8 +156,6 @@ if ( p->fVerbose )
 printf( "Iteration %d%s :  Area = %8.1f  ", Iter++, (p->fSwitching?"S":"A"), aAreaTotalCur );
 if ( fShowSwitching )
 printf( "Switch = %8.1f  ", Fpga_MappingGetSwitching(p,p->vMapping) );
-else
-printf( "Delay = %5.2f  ", Fpga_TimeComputeArrivalMax(p) );
 PRT( "Time", clock() - clk );
 }
     }