Version abc90215

9 files changed, 74 insertions, 74 deletions

diff --git a/src/map/fpga/fpga.h b/src/map/fpga/fpga.h
index b2ca4882..0479847c 100644
--- a/src/map/fpga/fpga.h
+++ b/src/map/fpga/fpga.h
@@ -19,10 +19,6 @@
 #ifndef __FPGA_H__
 #define __FPGA_H__
 
-#ifdef __cplusplus
-extern "C" {
-#endif
-
 ////////////////////////////////////////////////////////////////////////
 ///                          INCLUDES                                ///
 ////////////////////////////////////////////////////////////////////////
@@ -31,6 +27,10 @@ extern "C" {
 ///                         PARAMETERS                               ///
 ////////////////////////////////////////////////////////////////////////
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 // the maximum size of LUTs used for mapping
 #define FPGA_MAX_LUTSIZE   32
 
@@ -52,10 +52,10 @@ typedef struct Fpga_LutLibStruct_t_      Fpga_LutLib_t;
 ///                       MACRO DEFINITIONS                          ///
 ////////////////////////////////////////////////////////////////////////
  
-#define Fpga_IsComplement(p)    (((int)((PORT_PTRUINT_T) (p) & 01)))
-#define Fpga_Regular(p)         ((Fpga_Node_t *)((PORT_PTRUINT_T)(p) & ~01)) 
-#define Fpga_Not(p)             ((Fpga_Node_t *)((PORT_PTRUINT_T)(p) ^ 01)) 
-#define Fpga_NotCond(p,c)       ((Fpga_Node_t *)((PORT_PTRUINT_T)(p) ^ (c)))
+#define Fpga_IsComplement(p)    (((int)((ABC_PTRUINT_T) (p) & 01)))
+#define Fpga_Regular(p)         ((Fpga_Node_t *)((ABC_PTRUINT_T)(p) & ~01)) 
+#define Fpga_Not(p)             ((Fpga_Node_t *)((ABC_PTRUINT_T)(p) ^ 01)) 
+#define Fpga_NotCond(p,c)       ((Fpga_Node_t *)((ABC_PTRUINT_T)(p) ^ (c)))
 
 #define Fpga_Ref(p)   
 #define Fpga_Deref(p)
diff --git a/src/map/fpga/fpgaCore.c b/src/map/fpga/fpgaCore.c
index 634a8eb1..17feac7c 100644
--- a/src/map/fpga/fpgaCore.c
+++ b/src/map/fpga/fpgaCore.c
@@ -72,7 +72,7 @@ int Fpga_Mapping( Fpga_Man_t * p )
     if ( !Fpga_MappingPostProcess( p ) )
         return 0;
     p->timeRecover = clock() - clk;
-//PRT( "Total mapping time", clock() - clkTotal );
+//ABC_PRT( "Total mapping time", clock() - clkTotal );
 
     s_MappingTime = clock() - clkTotal;
     s_MappingMem = Fpga_CutCountAll(p) * (sizeof(Fpga_Cut_t) - sizeof(int) * (FPGA_MAX_LEAVES - p->nVarsMax));
@@ -83,7 +83,7 @@ int Fpga_Mapping( Fpga_Man_t * p )
 //        Fpga_MappingPrintOutputArrivals( p );
     if ( p->fVerbose )
     {
-        PRT( "Total time", clock() - clkTotal );
+        ABC_PRT( "Total time", clock() - clkTotal );
     }
     return 1;
 }
@@ -125,7 +125,7 @@ printf( "Switch = %8.1f  ", Fpga_MappingGetSwitching(p,p->vMapping) );
 else
 printf( "Delay = %5.2f  ", Fpga_TimeComputeArrivalMax(p) );
 
-PRT( "Time", p->timeMatch );
+ABC_PRT( "Time", p->timeMatch );
 }
 
     if ( !p->fAreaRecovery )
@@ -150,7 +150,7 @@ if ( fShowSwitching )
 printf( "Switch = %8.1f  ", Fpga_MappingGetSwitching(p,p->vMapping) );
 else
 printf( "Delay = %5.2f  ", Fpga_TimeComputeArrivalMax(p) );
-PRT( "Time", clock() - clk );
+ABC_PRT( "Time", clock() - clk );
 }
     }
 
@@ -177,7 +177,7 @@ if ( fShowSwitching )
 printf( "Switch = %8.1f  ", Fpga_MappingGetSwitching(p,p->vMapping) );
 else
 printf( "Delay = %5.2f  ", Fpga_TimeComputeArrivalMax(p) );
-PRT( "Time", clock() - clk );
+ABC_PRT( "Time", clock() - clk );
 }
     }
 
diff --git a/src/map/fpga/fpgaCreate.c b/src/map/fpga/fpgaCreate.c
index c0bae1c7..5245f050 100644
--- a/src/map/fpga/fpgaCreate.c
+++ b/src/map/fpga/fpgaCreate.c
@@ -28,7 +28,7 @@ static void            Fpga_TableResize( Fpga_Man_t * p );
 static Fpga_Node_t *   Fpga_TableLookup( Fpga_Man_t * p, Fpga_Node_t * p1, Fpga_Node_t * p2 );
 
 // hash key for the structural hash table
-static inline unsigned Fpga_HashKey2( Fpga_Node_t * p0, Fpga_Node_t * p1, int TableSize ) { return (unsigned)(((PORT_PTRUINT_T)(p0) + (PORT_PTRUINT_T)(p1) * 12582917) % TableSize); }
+static inline unsigned Fpga_HashKey2( Fpga_Node_t * p0, Fpga_Node_t * p1, int TableSize ) { return (unsigned)(((ABC_PTRUINT_T)(p0) + (ABC_PTRUINT_T)(p1) * 12582917) % TableSize); }
 
 ////////////////////////////////////////////////////////////////////////
 ///                     FUNCTION DEFINITIONS                         ///
@@ -167,7 +167,7 @@ Fpga_Man_t * Fpga_ManCreate( int nInputs, int nOutputs, int fVerbose )
     int i;
 
     // start the manager
-    p = ALLOC( Fpga_Man_t, 1 );
+    p = ABC_ALLOC( Fpga_Man_t, 1 );
     memset( p, 0, sizeof(Fpga_Man_t) );
     p->pLutLib   = Abc_FrameReadLibLut();
     p->nVarsMax  = p->pLutLib->LutMax;
@@ -193,13 +193,13 @@ Fpga_Man_t * Fpga_ManCreate( int nInputs, int nOutputs, int fVerbose )
 
     // create the PI nodes
     p->nInputs = nInputs;
-    p->pInputs = ALLOC( Fpga_Node_t *, nInputs );
+    p->pInputs = ABC_ALLOC( Fpga_Node_t *, nInputs );
     for ( i = 0; i < nInputs; i++ )
         p->pInputs[i] = Fpga_NodeCreate( p, NULL, NULL );
 
     // create the place for the output nodes
     p->nOutputs = nOutputs;
-    p->pOutputs = ALLOC( Fpga_Node_t *, nOutputs );
+    p->pOutputs = ABC_ALLOC( Fpga_Node_t *, nOutputs );
     memset( p->pOutputs, 0, sizeof(Fpga_Node_t *) * nOutputs );
     return p;
 }
@@ -230,12 +230,12 @@ void Fpga_ManFree( Fpga_Man_t * p )
         Fpga_NodeVecFree( p->vNodesAll );
     Extra_MmFixedStop( p->mmNodes );
     Extra_MmFixedStop( p->mmCuts );
-    FREE( p->ppOutputNames );
-    FREE( p->pInputArrivals );
-    FREE( p->pInputs );
-    FREE( p->pOutputs );
-    FREE( p->pBins );
-    FREE( p );
+    ABC_FREE( p->ppOutputNames );
+    ABC_FREE( p->pInputArrivals );
+    ABC_FREE( p->pInputs );
+    ABC_FREE( p->pOutputs );
+    ABC_FREE( p->pBins );
+    ABC_FREE( p );
 }
 
 
@@ -269,14 +269,14 @@ void Fpga_ManPrintTimeStats( Fpga_Man_t * p )
 
 //    printf( "N-canonical = %d. Matchings = %d.  ", p->nCanons, p->nMatches );
 //    printf( "Choice nodes = %d. Choices = %d.\n", p->nChoiceNodes, p->nChoices );
-    PRT( "ToMap", p->timeToMap );
-    PRT( "Cuts ", p->timeCuts );
-    PRT( "Match", p->timeMatch );
-    PRT( "Area ", p->timeRecover );
-    PRT( "ToNet", p->timeToNet );
-    PRT( "TOTAL", p->timeTotal );
-    if ( p->time1 ) { PRT( "time1", p->time1 ); }
-    if ( p->time2 ) { PRT( "time2", p->time2 ); }
+    ABC_PRT( "ToMap", p->timeToMap );
+    ABC_PRT( "Cuts ", p->timeCuts );
+    ABC_PRT( "Match", p->timeMatch );
+    ABC_PRT( "Area ", p->timeRecover );
+    ABC_PRT( "ToNet", p->timeToNet );
+    ABC_PRT( "TOTAL", p->timeTotal );
+    if ( p->time1 ) { ABC_PRT( "time1", p->time1 ); }
+    if ( p->time2 ) { ABC_PRT( "time2", p->time2 ); }
 }
 
 /**Function*************************************************************
@@ -344,7 +344,7 @@ void Fpga_TableCreate( Fpga_Man_t * pMan )
 {
     assert( pMan->pBins == NULL );
     pMan->nBins = Cudd_Prime(50000);
-    pMan->pBins = ALLOC( Fpga_Node_t *, pMan->nBins );
+    pMan->pBins = ABC_ALLOC( Fpga_Node_t *, pMan->nBins );
     memset( pMan->pBins, 0, sizeof(Fpga_Node_t *) * pMan->nBins );
     pMan->nNodes = 0;
 }
@@ -429,7 +429,7 @@ clk = clock();
     // get the new table size
     nBinsNew = Cudd_Prime(2 * pMan->nBins); 
     // allocate a new array
-    pBinsNew = ALLOC( Fpga_Node_t *, nBinsNew );
+    pBinsNew = ABC_ALLOC( Fpga_Node_t *, nBinsNew );
     memset( pBinsNew, 0, sizeof(Fpga_Node_t *) * nBinsNew );
     // rehash the entries from the old table
     Counter = 0;
@@ -446,10 +446,10 @@ clk = clock();
     if ( pMan->fVerbose )
     {
 //        printf( "Increasing the unique table size from %6d to %6d. ", pMan->nBins, nBinsNew );
-//        PRT( "Time", clock() - clk );
+//        ABC_PRT( "Time", clock() - clk );
     }
     // replace the table and the parameters
-    free( pMan->pBins );
+    ABC_FREE( pMan->pBins );
     pMan->pBins = pBinsNew;
     pMan->nBins = nBinsNew;
 }
diff --git a/src/map/fpga/fpgaCut.c b/src/map/fpga/fpgaCut.c
index de558456..a9108871 100644
--- a/src/map/fpga/fpgaCut.c
+++ b/src/map/fpga/fpgaCut.c
@@ -157,7 +157,7 @@ void Fpga_MappingCuts( Fpga_Man_t * p )
         nCuts = Fpga_CutCountAll(p);
         printf( "Nodes = %6d. Total %d-cuts = %d. Cuts per node = %.1f. ", 
                p->nNodes, p->nVarsMax, nCuts, ((float)nCuts)/p->nNodes );
-        PRT( "Time", clock() - clk );
+        ABC_PRT( "Time", clock() - clk );
     }
 
     // print the cuts for the first primary output
@@ -913,15 +913,15 @@ Fpga_CutTable_t * Fpga_CutTableStart( Fpga_Man_t * pMan )
 {
     Fpga_CutTable_t * p;
     // allocate the table
-    p = ALLOC( Fpga_CutTable_t, 1 );
+    p = ABC_ALLOC( Fpga_CutTable_t, 1 );
     memset( p, 0, sizeof(Fpga_CutTable_t) );
     p->nBins = Cudd_Prime( 10 * FPGA_CUTS_MAX_COMPUTE );
-    p->pBins = ALLOC( Fpga_Cut_t *, p->nBins );
+    p->pBins = ABC_ALLOC( Fpga_Cut_t *, p->nBins );
     memset( p->pBins, 0, sizeof(Fpga_Cut_t *) * p->nBins );
-    p->pCuts = ALLOC( int, 2 * FPGA_CUTS_MAX_COMPUTE );
-    p->pArray = ALLOC( Fpga_Cut_t *, 2 * FPGA_CUTS_MAX_COMPUTE );
-    p->pCuts1 = ALLOC( Fpga_Cut_t *, 2 * FPGA_CUTS_MAX_COMPUTE );
-    p->pCuts2 = ALLOC( Fpga_Cut_t *, 2 * FPGA_CUTS_MAX_COMPUTE );
+    p->pCuts = ABC_ALLOC( int, 2 * FPGA_CUTS_MAX_COMPUTE );
+    p->pArray = ABC_ALLOC( Fpga_Cut_t *, 2 * FPGA_CUTS_MAX_COMPUTE );
+    p->pCuts1 = ABC_ALLOC( Fpga_Cut_t *, 2 * FPGA_CUTS_MAX_COMPUTE );
+    p->pCuts2 = ABC_ALLOC( Fpga_Cut_t *, 2 * FPGA_CUTS_MAX_COMPUTE );
     return p;
 }
 
@@ -938,12 +938,12 @@ Fpga_CutTable_t * Fpga_CutTableStart( Fpga_Man_t * pMan )
 ***********************************************************************/
 void Fpga_CutTableStop( Fpga_CutTable_t * p )
 {
-    free( p->pCuts1 );
-    free( p->pCuts2 );
-    free( p->pArray );
-    free( p->pBins );
-    free( p->pCuts );
-    free( p );
+    ABC_FREE( p->pCuts1 );
+    ABC_FREE( p->pCuts2 );
+    ABC_FREE( p->pArray );
+    ABC_FREE( p->pBins );
+    ABC_FREE( p->pCuts );
+    ABC_FREE( p );
 }
 
 /**Function*************************************************************
@@ -1115,7 +1115,7 @@ Fpga_Cut_t * Fpga_CutSortCuts( Fpga_Man_t * pMan, Fpga_CutTable_t * p, Fpga_Cut_
     if ( nCuts > FPGA_CUTS_MAX_USE - 1 )
     {
 //        printf( "*" );
-        // free the remaining cuts
+        // ABC_FREE the remaining cuts
         for ( i = FPGA_CUTS_MAX_USE - 1; i < nCuts; i++ )
             Extra_MmFixedEntryRecycle( pMan->mmCuts, (char *)p->pCuts1[i] );
         // update the number of cuts
diff --git a/src/map/fpga/fpgaInt.h b/src/map/fpga/fpgaInt.h
index f4145e7f..ba9538c2 100644
--- a/src/map/fpga/fpgaInt.h
+++ b/src/map/fpga/fpgaInt.h
@@ -63,19 +63,19 @@
 #define FPGA_INT_LARGE            (10000000)
 
 // the macro to compute the signature
-#define FPGA_SEQ_SIGN(p)        (1 << (((PORT_PTRUINT_T)p)%31));
+#define FPGA_SEQ_SIGN(p)        (1 << (((ABC_PTRUINT_T)p)%31));
 
 // internal macros to work with cuts
-#define Fpga_CutIsComplement(p)  (((int)((PORT_PTRUINT_T)(p) & 01)))
-#define Fpga_CutRegular(p)       ((Fpga_Cut_t *)((PORT_PTRUINT_T)(p) & ~01)) 
-#define Fpga_CutNot(p)           ((Fpga_Cut_t *)((PORT_PTRUINT_T)(p) ^ 01)) 
-#define Fpga_CutNotCond(p,c)     ((Fpga_Cut_t *)((PORT_PTRUINT_T)(p) ^ (c)))
+#define Fpga_CutIsComplement(p)  (((int)((ABC_PTRUINT_T)(p) & 01)))
+#define Fpga_CutRegular(p)       ((Fpga_Cut_t *)((ABC_PTRUINT_T)(p) & ~01)) 
+#define Fpga_CutNot(p)           ((Fpga_Cut_t *)((ABC_PTRUINT_T)(p) ^ 01)) 
+#define Fpga_CutNotCond(p,c)     ((Fpga_Cut_t *)((ABC_PTRUINT_T)(p) ^ (c)))
 
 // the cut nodes
-#define Fpga_SeqIsComplement( p )      (((int)((PORT_PTRUINT_T) (p) & 01)))
-#define Fpga_SeqRegular( p )           ((Fpga_Node_t *)((PORT_PTRUINT_T)(p) & ~015))
-#define Fpga_SeqIndex( p )             ((((PORT_PTRUINT_T)(p)) >> 1) & 07)
-#define Fpga_SeqIndexCreate( p, Ind )  (((PORT_PTRUINT_T)(p)) | (1 << (((PORT_PTRUINT_T)(Ind)) & 07)))
+#define Fpga_SeqIsComplement( p )      (((int)((ABC_PTRUINT_T) (p) & 01)))
+#define Fpga_SeqRegular( p )           ((Fpga_Node_t *)((ABC_PTRUINT_T)(p) & ~015))
+#define Fpga_SeqIndex( p )             ((((ABC_PTRUINT_T)(p)) >> 1) & 07)
+#define Fpga_SeqIndexCreate( p, Ind )  (((ABC_PTRUINT_T)(p)) | (1 << (((ABC_PTRUINT_T)(Ind)) & 07)))
 
 // internal macros for referencing of nodes
 #define Fpga_NodeReadRef(p)      ((Fpga_Regular(p))->nRefs)
diff --git a/src/map/fpga/fpgaLib.c b/src/map/fpga/fpgaLib.c
index b9615a8c..d5b12293 100644
--- a/src/map/fpga/fpgaLib.c
+++ b/src/map/fpga/fpgaLib.c
@@ -66,7 +66,7 @@ Fpga_LutLib_t * Fpga_LutLibRead( char * FileName, int fVerbose )
         return NULL;
     }
 
-    p = ALLOC( Fpga_LutLib_t, 1 );
+    p = ABC_ALLOC( Fpga_LutLib_t, 1 );
     memset( p, 0, sizeof(Fpga_LutLib_t) );
     p->pName = Extra_UtilStrsav( FileName );
 
@@ -81,7 +81,7 @@ Fpga_LutLib_t * Fpga_LutLibRead( char * FileName, int fVerbose )
         if ( i != atoi(pToken) )
         {
             printf( "Error in the LUT library file \"%s\".\n", FileName );
-            free( p );
+            ABC_FREE( p );
             return NULL;
         }
 
@@ -162,7 +162,7 @@ Fpga_LutLib_t * Fpga_LutLibRead( char * FileName, int fVerbose )
 Fpga_LutLib_t * Fpga_LutLibDup( Fpga_LutLib_t * p )
 {
     Fpga_LutLib_t * pNew;
-    pNew = ALLOC( Fpga_LutLib_t, 1 );
+    pNew = ABC_ALLOC( Fpga_LutLib_t, 1 );
     *pNew = *p;
     pNew->pName = Extra_UtilStrsav( pNew->pName );
     return pNew;
@@ -183,8 +183,8 @@ void Fpga_LutLibFree( Fpga_LutLib_t * pLutLib )
 {
     if ( pLutLib == NULL )
         return;
-    FREE( pLutLib->pName );
-    FREE( pLutLib );
+    ABC_FREE( pLutLib->pName );
+    ABC_FREE( pLutLib );
 }
 
 
diff --git a/src/map/fpga/fpgaTruth.c b/src/map/fpga/fpgaTruth.c
index 8ffb7819..7eca8e3e 100644
--- a/src/map/fpga/fpgaTruth.c
+++ b/src/map/fpga/fpgaTruth.c
@@ -44,7 +44,7 @@ DdNode * Fpga_TruthsCutBdd_rec( DdManager * dd, Fpga_Cut_t * pCut, Fpga_NodeVec_
     assert( !Fpga_IsComplement(pCut) );
     // if the cut is visited, return the result
     if ( pCut->uSign )
-        return (DdNode *)(PORT_PTRUINT_T)pCut->uSign;
+        return (DdNode *)(ABC_PTRUINT_T)pCut->uSign;
     // compute the functions of the children
     bFunc0 = Fpga_TruthsCutBdd_rec( dd, Fpga_CutRegular(pCut->pOne), vVisited );   Cudd_Ref( bFunc0 );
     bFunc0 = Cudd_NotCond( bFunc0, Fpga_CutIsComplement(pCut->pOne) );
@@ -56,7 +56,7 @@ DdNode * Fpga_TruthsCutBdd_rec( DdManager * dd, Fpga_Cut_t * pCut, Fpga_NodeVec_
     Cudd_RecursiveDeref( dd, bFunc0 );
     Cudd_RecursiveDeref( dd, bFunc1 );
     assert( pCut->uSign == 0 );
-    pCut->uSign = (unsigned)(PORT_PTRUINT_T)bFunc;
+    pCut->uSign = (unsigned)(ABC_PTRUINT_T)bFunc;
     // add this cut to the visited list
     Fpga_NodeVecPush( vVisited, (Fpga_Node_t *)pCut );
     return bFunc;
@@ -81,7 +81,7 @@ void * Fpga_TruthsCutBdd( void * dd, Fpga_Cut_t * pCut )
     assert( pCut->nLeaves > 1 );
     // set the leaf variables
     for ( i = 0; i < pCut->nLeaves; i++ )
-        pCut->ppLeaves[i]->pCuts->uSign = (unsigned)(PORT_PTRUINT_T)Cudd_bddIthVar( dd, i );
+        pCut->ppLeaves[i]->pCuts->uSign = (unsigned)(ABC_PTRUINT_T)Cudd_bddIthVar( dd, i );
     // recursively compute the function
     vVisited = Fpga_NodeVecAlloc( 10 );
     bFunc = Fpga_TruthsCutBdd_rec( dd, pCut, vVisited );   Cudd_Ref( bFunc );
@@ -91,7 +91,7 @@ void * Fpga_TruthsCutBdd( void * dd, Fpga_Cut_t * pCut )
     for ( i = 0; i < vVisited->nSize; i++ )
     {
         pCut = (Fpga_Cut_t *)vVisited->pArray[i];
-        Cudd_RecursiveDeref( dd, (DdNode*)(PORT_PTRUINT_T)pCut->uSign );
+        Cudd_RecursiveDeref( dd, (DdNode*)(ABC_PTRUINT_T)pCut->uSign );
         pCut->uSign = 0;
     }
 //    printf( "%d ", vVisited->nSize );
diff --git a/src/map/fpga/fpgaUtils.c b/src/map/fpga/fpgaUtils.c
index 77c2e2b0..f360254b 100644
--- a/src/map/fpga/fpgaUtils.c
+++ b/src/map/fpga/fpgaUtils.c
@@ -305,7 +305,7 @@ float Fpga_MappingSetRefsAndArea( Fpga_Man_t * pMan )
 
     // allocate place to store the nodes
     LevelMax = Fpga_MappingMaxLevel( pMan );
-    ppStore = ALLOC( Fpga_Node_t *, LevelMax + 1 );
+    ppStore = ABC_ALLOC( Fpga_Node_t *, LevelMax + 1 );
     memset( ppStore, 0, sizeof(Fpga_Node_t *) * (LevelMax + 1) );
 
     // collect nodes reachable from POs in the DFS order through the best cuts
@@ -324,7 +324,7 @@ float Fpga_MappingSetRefsAndArea( Fpga_Man_t * pMan )
     for ( i = LevelMax; i >= 0; i-- )
         for ( pNode = ppStore[i]; pNode; pNode = (Fpga_Node_t *)pNode->pData0 )
             Fpga_NodeVecPush( pMan->vMapping, pNode );
-    free( ppStore );
+    ABC_FREE( ppStore );
     return aArea;
 }
 
diff --git a/src/map/fpga/fpgaVec.c b/src/map/fpga/fpgaVec.c
index 79b6b43d..b17697dd 100644
--- a/src/map/fpga/fpgaVec.c
+++ b/src/map/fpga/fpgaVec.c
@@ -42,12 +42,12 @@ static int Fpga_NodeVecCompareLevels( Fpga_Node_t ** pp1, Fpga_Node_t ** pp2 );
 Fpga_NodeVec_t * Fpga_NodeVecAlloc( int nCap )
 {
     Fpga_NodeVec_t * p;
-    p = ALLOC( Fpga_NodeVec_t, 1 );
+    p = ABC_ALLOC( Fpga_NodeVec_t, 1 );
     if ( nCap > 0 && nCap < 16 )
         nCap = 16;
     p->nSize  = 0;
     p->nCap   = nCap;
-    p->pArray = p->nCap? ALLOC( Fpga_Node_t *, p->nCap ) : NULL;
+    p->pArray = p->nCap? ABC_ALLOC( Fpga_Node_t *, p->nCap ) : NULL;
     return p;
 }
 
@@ -64,8 +64,8 @@ Fpga_NodeVec_t * Fpga_NodeVecAlloc( int nCap )
 ***********************************************************************/
 void Fpga_NodeVecFree( Fpga_NodeVec_t * p )
 {
-    FREE( p->pArray );
-    FREE( p );
+    ABC_FREE( p->pArray );
+    ABC_FREE( p );
 }
 
 /**Function*************************************************************
@@ -115,7 +115,7 @@ void Fpga_NodeVecGrow( Fpga_NodeVec_t * p, int nCapMin )
 {
     if ( p->nCap >= nCapMin )
         return;
-    p->pArray = REALLOC( Fpga_Node_t *, p->pArray, nCapMin ); 
+    p->pArray = ABC_REALLOC( Fpga_Node_t *, p->pArray, nCapMin ); 
     p->nCap   = nCapMin;
 }