Version abc50819

9 files changed, 112 insertions, 658 deletions

diff --git a/src/map/fpga/fpga.h b/src/map/fpga/fpga.h
index 62a93a75..9dad1670 100644
--- a/src/map/fpga/fpga.h
+++ b/src/map/fpga/fpga.h
@@ -80,10 +80,7 @@ extern void            Fpga_ManSetTimeToNet( Fpga_Man_t * p, int Time );
 extern void            Fpga_ManSetTimeTotal( Fpga_Man_t * p, int Time );
 extern void            Fpga_ManSetOutputNames( Fpga_Man_t * p, char ** ppNames );
 extern void            Fpga_ManSetInputArrivals( Fpga_Man_t * p, float * pArrivals );
-extern void            Fpga_ManSetTree( Fpga_Man_t * p, int fTree );
-extern void            Fpga_ManSetPower( Fpga_Man_t * p, int fPower );
 extern void            Fpga_ManSetAreaRecovery( Fpga_Man_t * p, int fAreaRecovery );
-extern void            Fpga_ManSetResyn( Fpga_Man_t * p, int fResynthesis );
 extern void            Fpga_ManSetDelayLimit( Fpga_Man_t * p, float DelayLimit );
 extern void            Fpga_ManSetAreaLimit( Fpga_Man_t * p, float AreaLimit );
 extern void            Fpga_ManSetTimeLimit( Fpga_Man_t * p, float TimeLimit );
@@ -95,7 +92,6 @@ extern void            Fpga_ManSetChoiceNodeNum( Fpga_Man_t * p, int nChoiceNode
 extern void            Fpga_ManSetChoiceNum( Fpga_Man_t * p, int nChoices );
 extern void            Fpga_ManSetVerbose( Fpga_Man_t * p, int fVerbose );
 extern void            Fpga_ManSetLatchNum( Fpga_Man_t * p, int nLatches );
-extern void            Fpga_ManSetSequential( Fpga_Man_t * p, int fSequential );
 extern void            Fpga_ManSetName( Fpga_Man_t * p, char * pFileName );
 
 extern int             Fpga_LibReadLutMax( Fpga_LutLib_t * pLib );
diff --git a/src/map/fpga/fpgaCore.c b/src/map/fpga/fpgaCore.c
index 457c2384..b181e997 100644
--- a/src/map/fpga/fpgaCore.c
+++ b/src/map/fpga/fpgaCore.c
@@ -17,18 +17,12 @@
 ***********************************************************************/
 
 #include "fpgaInt.h"
-//#include "res.h"
 
 ////////////////////////////////////////////////////////////////////////
 ///                        DECLARATIONS                              ///
 ////////////////////////////////////////////////////////////////////////
 
-static int   Fpga_MappingPostProcess( Fpga_Man_t * p );
-
-extern void  Fpga_Experiment( Fpga_Man_t * p );
-extern void Fpga_MappingCutsSeq( Fpga_Man_t * p );
-extern void Fpga_MappingLValues( Fpga_Man_t * pMan, int fVerbose );
-
+static int  Fpga_MappingPostProcess( Fpga_Man_t * p );
 
 ////////////////////////////////////////////////////////////////////////
 ///                     FUNCTION DEFITIONS                           ///
@@ -51,35 +45,18 @@ extern void Fpga_MappingLValues( Fpga_Man_t * pMan, int fVerbose );
 ***********************************************************************/
 int Fpga_Mapping( Fpga_Man_t * p )
 {
-    int clk;
+    int clk, clkTotal = clock();
 
     // collect the nodes reachable from POs in the DFS order (including the choices)
     p->vAnds = Fpga_MappingDfs( p, 1 );
     Fpga_ManReportChoices( p ); // recomputes levels
     Fpga_MappingSetChoiceLevels( p );
 
-    if ( p->fSequential )
-    {
-//        Fpga_MappingCutsSeq( p );
-        Fpga_MappingCuts( p );
-//clk = clock();
-//        Fpga_MappingLValues( p, p->fVerbose );
-//PRT( "Time", clock() - clk );
-        return 0;
-    }
-
     // compute the cuts of nodes in the DFS order
     clk = clock();
     Fpga_MappingCuts( p );
     p->timeCuts = clock() - clk;
 
-//    Fpga_MappingSortByLevel( p, p->vAnds, 1 );
-
-    // derive the truth tables 
-    clk = clock();
-//    Fpga_MappingTruths( p );
-    p->timeTruth = clock() - clk;
-
     // match the truth tables to the supergates
     clk = clock();
     if ( !Fpga_MappingMatches( p, 1 ) )
@@ -94,10 +71,7 @@ int Fpga_Mapping( Fpga_Man_t * p )
             return 0;
         p->timeRecover = clock() - clk;
     }
-
-    // perform resynthesis
-//    if ( p->fResynthesis )
-//        Res_Resynthesize( p, p->DelayLimit, p->AreaLimit, p->TimeLimit, 1 );
+PRT( "Total mapping time", clock() - clkTotal );
 
     // print the AI-graph used for mapping
     //Fpga_ManShow( p, "test" );
@@ -124,128 +98,59 @@ int Fpga_Mapping( Fpga_Man_t * p )
 int Fpga_MappingPostProcess( Fpga_Man_t * p )
 {
     float aAreaTotalPrev, aAreaTotalCur, aAreaTotalCur2;
-    float aSwitchTotalPrev, aSwitchTotalCur;
     int Iter, clk;
 
-
+    // compute area, set references, and collect nodes used in the mapping
+    aAreaTotalCur = Fpga_MappingSetRefsAndArea( p );
 if ( p->fVerbose )
 {
-printf( "Iteration %dD :  Area = %11.1f  ", 0, Fpga_MappingArea( p ) );
+printf( "Iteration %dD :  Area = %11.1f  ", 0, aAreaTotalCur );
 PRT( "Time", p->timeMatch );
 }
 
-
-//    Fpga_MappingExplore( p );
-//    p->fAreaGlo = Fpga_MappingArea( p );
-//    return;
-
-
-//    aAreaTotalCur = FPGA_FLOAT_LARGE;
-    aAreaTotalCur = Fpga_MappingSetRefsAndArea( p );
-
     Iter = 1;
     do {
 clk = clock();
         // save the previous area flow
         aAreaTotalPrev = aAreaTotalCur;
-
         // compute the required times and the fanouts
         Fpga_TimeComputeRequiredGlobal( p );
         // remap topologically
         Fpga_MappingMatches( p, 0 );
         // get the resulting area
-        aAreaTotalCur = Fpga_MappingArea( p );
+//        aAreaTotalCur = Fpga_MappingSetRefsAndArea( p );
+        aAreaTotalCur = Fpga_MappingAreaTrav( p );
+        // note that here we do not update the reference counter
+        // for some reason, this works better on benchmarks
 if ( p->fVerbose )
 {
 printf( "Iteration %dF :  Area = %11.1f  ", Iter++, aAreaTotalCur );
 PRT( "Time", clock() - clk );
 }
-        if ( p->fPower )
-            aSwitchTotalCur = Fpga_MappingPrintSwitching( p );
         // quit if this iteration reduced area flow by less than 1%
     } while ( aAreaTotalPrev > 1.02 * aAreaTotalCur );
 
-
-//    Fpga_MappingExplore( p );
-//    p->fAreaGlo = Fpga_MappingArea( p );
-//    return;
-
-
-/*
-    // compute the area of each cut
-    aAreaTotalCur = Fpga_MappingSetRefsAndArea( p );
-    // compute the required times and the fanouts
-    Fpga_TimeComputeRequiredGlobal( p );
-    // perform experiment
-    Fpga_Experiment( p );
-*/
-
-
-    // compute the area of each cut
-    aAreaTotalCur = Fpga_MappingSetRefsAndArea( p );
-    aAreaTotalCur2 = Fpga_MappingComputeCutAreas( p );
+    // update reference counters
+    aAreaTotalCur2 = Fpga_MappingSetRefsAndArea( p );
     assert( aAreaTotalCur == aAreaTotalCur2 );
 
-
-//    aAreaTotalCur = FPGA_FLOAT_LARGE;
-//    Iter = 1;
     do {
 clk = clock();
         // save the previous area flow
         aAreaTotalPrev = aAreaTotalCur;
-
         // compute the required times and the fanouts
         Fpga_TimeComputeRequiredGlobal( p );
         // remap topologically
         Fpga_MappingMatchesArea( p );
         // get the resulting area
-        aAreaTotalCur = Fpga_MappingArea( p );
+        aAreaTotalCur = Fpga_MappingSetRefsAndArea( p );
 if ( p->fVerbose )
 {
 printf( "Iteration %dA :  Area = %11.1f  ", Iter++, aAreaTotalCur );
 PRT( "Time", clock() - clk );
 }
-        if ( p->fPower )
-        {
-            aSwitchTotalPrev = aSwitchTotalCur;
-            aSwitchTotalCur  = Fpga_MappingPrintSwitching( p );
-        }
         // quit if this iteration reduced area flow by less than 1%
     } while ( aAreaTotalPrev > 1.02 * aAreaTotalCur );
-
-
-    if ( p->fPower )
-    {
-        do {
-clk = clock();
-            // save the previous area flow
-            aAreaTotalPrev = aAreaTotalCur;
-
-            // compute the required times and the fanouts
-            Fpga_TimeComputeRequiredGlobal( p );
-            // remap topologically
-            Fpga_MappingMatchesSwitch( p );
-            // get the resulting area
-            aAreaTotalCur = Fpga_MappingArea( p );
-if ( p->fVerbose )
-{
-printf( "Iteration %dS :  Area = %11.1f  ", Iter++, aAreaTotalCur );
-PRT( "Time", clock() - clk );
-}
-            aSwitchTotalPrev = aSwitchTotalCur;
-            aSwitchTotalCur  = Fpga_MappingPrintSwitching( p );
-            // quit if this iteration reduced area flow by less than 1%
-        } while ( aSwitchTotalPrev > 1.01 * aSwitchTotalCur );
-    }
-
-/*
-    // compute the area of each cut
-    aAreaTotalCur = Fpga_MappingSetRefsAndArea( p );
-    // compute the required times and the fanouts
-    Fpga_TimeComputeRequiredGlobal( p );
-    // perform experiment
-    Fpga_Experiment( p );
-*/
     p->fAreaGlo = aAreaTotalCur;
     return 1;
 }
diff --git a/src/map/fpga/fpgaCreate.c b/src/map/fpga/fpgaCreate.c
index 1e654ded..f3abbedb 100644
--- a/src/map/fpga/fpgaCreate.c
+++ b/src/map/fpga/fpgaCreate.c
@@ -58,10 +58,7 @@ void            Fpga_ManSetTimeToNet( Fpga_Man_t * p, int Time )          { p->t
 void            Fpga_ManSetTimeTotal( Fpga_Man_t * p, int Time )          { p->timeTotal = Time;  }
 void            Fpga_ManSetOutputNames( Fpga_Man_t * p, char ** ppNames ) { p->ppOutputNames = ppNames; }
 void            Fpga_ManSetInputArrivals( Fpga_Man_t * p, float * pArrivals ) { p->pInputArrivals = pArrivals; }
-void            Fpga_ManSetTree( Fpga_Man_t * p, int fTree )              { p->fTree = fTree;           }
-void            Fpga_ManSetPower( Fpga_Man_t * p, int fPower )              { p->fPower = fPower;           }
 void            Fpga_ManSetAreaRecovery( Fpga_Man_t * p, int fAreaRecovery ) { p->fAreaRecovery = fAreaRecovery;}
-void            Fpga_ManSetResyn( Fpga_Man_t * p, int fResynthesis )         { p->fResynthesis = fResynthesis;  }
 void            Fpga_ManSetDelayLimit( Fpga_Man_t * p, float DelayLimit )    { p->DelayLimit   = DelayLimit;    }
 void            Fpga_ManSetAreaLimit( Fpga_Man_t * p, float AreaLimit )      { p->AreaLimit    = AreaLimit;     }
 void            Fpga_ManSetTimeLimit( Fpga_Man_t * p, float TimeLimit )      { p->TimeLimit    = TimeLimit;     }
@@ -69,7 +66,6 @@ void            Fpga_ManSetChoiceNodeNum( Fpga_Man_t * p, int nChoiceNodes ) { p
 void            Fpga_ManSetChoiceNum( Fpga_Man_t * p, int nChoices )         { p->nChoices = nChoices;          }   
 void            Fpga_ManSetVerbose( Fpga_Man_t * p, int fVerbose )           { p->fVerbose = fVerbose;          }   
 void            Fpga_ManSetLatchNum( Fpga_Man_t * p, int nLatches )          { p->nLatches = nLatches;          }   
-void            Fpga_ManSetSequential( Fpga_Man_t * p, int fSequential )     { p->fSequential = fSequential;    }   
 void            Fpga_ManSetName( Fpga_Man_t * p, char * pFileName )          { p->pFileName = pFileName;        }   
 
 /**Function*************************************************************
@@ -170,8 +166,6 @@ Fpga_Man_t * Fpga_ManCreate( int nInputs, int nOutputs, int fVerbose )
     p->nVarsMax  = p->pLutLib->LutMax;
     p->fVerbose  = fVerbose;
     p->fAreaRecovery = 1;
-    p->fTree     = 0;
-    p->fRefCount = 1;
     p->fEpsilon  = (float)0.001;
 
     Fpga_TableCreate( p );
@@ -181,13 +175,14 @@ Fpga_Man_t * Fpga_ManCreate( int nInputs, int nOutputs, int fVerbose )
     p->mmCuts   = Extra_MmFixedStart( sizeof(Fpga_Cut_t) );
 
     assert( p->nVarsMax > 0 );
-    Fpga_MappingSetupTruthTables( p->uTruths );
+//    Fpga_MappingSetupTruthTables( p->uTruths );
 
     // make sure the constant node will get index -1
     p->nNodes = -1;
     // create the constant node
     p->pConst1 = Fpga_NodeCreate( p, NULL, NULL );
-    p->vNodesAll = Fpga_NodeVecAlloc( 100 );
+    p->vNodesAll = Fpga_NodeVecAlloc( 1000 );
+    p->vMapping = Fpga_NodeVecAlloc( 1000 );
 
     // create the PI nodes
     p->nInputs = nInputs;
@@ -216,27 +211,23 @@ Fpga_Man_t * Fpga_ManCreate( int nInputs, int nOutputs, int fVerbose )
 void Fpga_ManFree( Fpga_Man_t * p )
 {
 //    Fpga_ManStats( p );
-
 //    int i;
 //    for ( i = 0; i < p->vNodesAll->nSize; i++ )
 //        Fpga_NodeVecFree( p->vNodesAll->pArray[i]->vFanouts );
 //    Fpga_NodeVecFree( p->pConst1->vFanouts );
+    if ( p->vMapping )
+        Fpga_NodeVecFree( p->vMapping );
     if ( p->vAnds )    
         Fpga_NodeVecFree( p->vAnds );
     if ( p->vNodesAll )    
         Fpga_NodeVecFree( p->vNodesAll );
     Extra_MmFixedStop( p->mmNodes, 0 );
     Extra_MmFixedStop( p->mmCuts, 0 );
+    FREE( p->ppOutputNames );
     FREE( p->pInputArrivals );
     FREE( p->pInputs );
     FREE( p->pOutputs );
     FREE( p->pBins );
-    FREE( p->ppOutputNames );
-    if ( p->pSimInfo )
-    {
-    FREE( p->pSimInfo[0] );
-    FREE( p->pSimInfo );
-    }
     FREE( p );
 }
 
@@ -316,19 +307,18 @@ Fpga_Node_t * Fpga_NodeCreate( Fpga_Man_t * p, Fpga_Node_t * p1, Fpga_Node_t * p
     // set the level of this node
     if ( p1 ) 
     {
+#ifdef FPGA_ALLOCATE_FANOUT
         // create the fanout info
         Fpga_NodeAddFaninFanout( Fpga_Regular(p1), pNode );
         Fpga_NodeAddFaninFanout( Fpga_Regular(p2), pNode );
+#endif
         // compute the level
         pNode->Level = 1 + FPGA_MAX(Fpga_Regular(p1)->Level, Fpga_Regular(p2)->Level);
         pNode->fInv  = Fpga_NodeIsSimComplement(p1) & Fpga_NodeIsSimComplement(p2);
     }
-    // reference the inputs (will be used to compute the number of fanouts)
-    if ( p->fRefCount )
-    {
-        if ( p1 ) Fpga_NodeRef(p1);
-        if ( p2 ) Fpga_NodeRef(p2);
-    }
+    // reference the inputs 
+    if ( p1 ) Fpga_NodeRef(p1);
+    if ( p2 ) Fpga_NodeRef(p2);
     return pNode;
 }
 
diff --git a/src/map/fpga/fpgaCut.c b/src/map/fpga/fpgaCut.c
index 27079953..5b5fbe69 100644
--- a/src/map/fpga/fpgaCut.c
+++ b/src/map/fpga/fpgaCut.c
@@ -206,8 +206,9 @@ Fpga_Cut_t * Fpga_CutCompute( Fpga_Man_t * p, Fpga_CutTable_t * pTable, Fpga_Nod
     Fpga_Node_t * pTemp;
     Fpga_Cut_t * pList, * pList1, * pList2;
     Fpga_Cut_t * pCut;
-    int fPivot1 = p->fTree && (Fpga_NodeReadRef(pNode->p1)>2);
-    int fPivot2 = p->fTree && (Fpga_NodeReadRef(pNode->p2)>2);
+    int fTree = 0;
+    int fPivot1 = fTree && (Fpga_NodeReadRef(pNode->p1)>2);
+    int fPivot2 = fTree && (Fpga_NodeReadRef(pNode->p2)>2);
 
     // if the cuts are computed return them
     if ( pNode->pCuts )
diff --git a/src/map/fpga/fpgaFanout.c b/src/map/fpga/fpgaFanout.c
index 50809f65..0a34ff43 100644
--- a/src/map/fpga/fpgaFanout.c
+++ b/src/map/fpga/fpgaFanout.c
@@ -18,6 +18,8 @@
 
 #include "fpgaInt.h"
 
+#ifdef MAP_ALLOCATE_FANOUT
+
 ////////////////////////////////////////////////////////////////////////
 ///                        DECLARATIONS                              ///
 ////////////////////////////////////////////////////////////////////////
@@ -26,7 +28,6 @@
 ///                     FUNCTION DEFITIONS                           ///
 ////////////////////////////////////////////////////////////////////////
 
-
 /**Function*************************************************************
 
   Synopsis    [Add the fanout to the node.]
@@ -136,4 +137,5 @@ int Fpga_NodeGetFanoutNum( Fpga_Node_t * pNode )
 ///                       END OF FILE                                ///
 ////////////////////////////////////////////////////////////////////////
 
+#endif
 
diff --git a/src/map/fpga/fpgaInt.h b/src/map/fpga/fpgaInt.h
index 63308d53..95203378 100644
--- a/src/map/fpga/fpgaInt.h
+++ b/src/map/fpga/fpgaInt.h
@@ -35,6 +35,9 @@
 ///                         PARAMETERS                               ///
 ////////////////////////////////////////////////////////////////////////
  
+// uncomment to have fanouts represented in the mapping graph
+//#define FPGA_ALLOCATE_FANOUT  1
+
 ////////////////////////////////////////////////////////////////////////
 ///                       MACRO DEFITIONS                            ///
 ////////////////////////////////////////////////////////////////////////
@@ -104,10 +107,11 @@ struct Fpga_ManStruct_t_
     Fpga_Node_t **      pOutputs;      // the array of outputs
     int                 nOutputs;      // the number of outputs
     int                 nNodes;        // the total number of nodes
-    Fpga_Node_t *       pConst1;       // the constant 1 node
-    Fpga_NodeVec_t *    vAnds;         // the array of pointer to nodes by number
-    Fpga_NodeVec_t *    vNodesAll;     // the array of pointer to nodes by number
     int                 nLatches;      // the number of latches in the circuit
+    Fpga_Node_t *       pConst1;       // the constant 1 node
+    Fpga_NodeVec_t *    vNodesAll;     // the nodes by number
+    Fpga_NodeVec_t *    vAnds;         // the nodes reachable from COs
+    Fpga_NodeVec_t *    vMapping;      // the nodes used in the current mapping
 
     // info about the original circuit
     char *              pFileName;     // the file name
@@ -116,12 +120,12 @@ struct Fpga_ManStruct_t_
 
     // mapping parameters
     int                 nVarsMax;      // the max number of variables
-    int                 fTree;         // the flag to enable tree mapping
-    int                 fPower;        // the flag to enable power optimization
+//    int                 fTree;         // the flag to enable tree mapping
+//    int                 fPower;        // the flag to enable power optimization
     int                 fAreaRecovery; // the flag to use area flow as the first parameter
     int                 fVerbose;      // the verbosiness flag
-    int                 fRefCount;     // enables reference counting
-    int                 fSequential;   // use sequential mapping
+//    int                 fRefCount;     // enables reference counting
+//    int                 fSequential;   // use sequential mapping
     int                 nTravIds;
 
     // support of choice nodes
@@ -133,16 +137,12 @@ struct Fpga_ManStruct_t_
  
     // the supergate library
     Fpga_LutLib_t *     pLutLib;       // the current LUT library
-    unsigned            uTruths[6][2]; // the elementary truth tables
+//    unsigned            uTruths[6][2]; // the elementary truth tables
 
     // the memory managers
     Extra_MmFixed_t *   mmNodes;       // the memory manager for nodes
     Extra_MmFixed_t *   mmCuts;        // the memory manager for cuts
 
-    // simulation info from the FRAIG manager
-    int                 nSimRounds;    // the number of words in the simulation info
-    unsigned **         pSimInfo;      // the simulation info for each PI
-
     // resynthesis parameters
     int                 fResynthesis;  // the resynthesis flag
     float               fRequiredGlo;  // the global required times
@@ -203,12 +203,14 @@ struct Fpga_NodeStruct_t_
     Fpga_Node_t *       p2;            // the second child
     Fpga_Node_t *       pNextE;        // the next functionally equivalent node
     Fpga_Node_t *       pRepr;         // the representative of the functionally equivalent class
-//    Fpga_NodeVec_t *    vFanouts;      // the array of fanouts of the node
 
+#ifdef FPGA_ALLOCATE_FANOUT
     // representation of node's fanouts
     Fpga_Node_t *       pFanPivot;     // the first fanout of this node
     Fpga_Node_t *       pFanFanin1;    // the next fanout of p1
     Fpga_Node_t *       pFanFanin2;    // the next fanout of p2
+//    Fpga_NodeVec_t *    vFanouts;      // the array of fanouts of the gate
+#endif
 
     // the delay information
     float               tRequired;     // the best area flow 
@@ -335,8 +337,6 @@ extern void              Fpga_TimeComputeRequiredGlobal( Fpga_Man_t * p );
 extern void              Fpga_TimeComputeRequired( Fpga_Man_t * p, float fRequired );
 extern void              Fpga_TimePropagateRequired( Fpga_Man_t * p, Fpga_NodeVec_t * vNodes );
 extern void              Fpga_TimePropagateArrival( Fpga_Man_t * p );
-/*=== fpgaTruth.c ===============================================================*/
-extern void              Fpga_MappingTruths( Fpga_Man_t * pMan );
 /*=== fpgaVec.c =============================================================*/
 extern Fpga_NodeVec_t *  Fpga_NodeVecAlloc( int nCap );
 extern void              Fpga_NodeVecFree( Fpga_NodeVec_t * p );
@@ -359,23 +359,11 @@ extern void              Fpga_NodeVecReverse( Fpga_NodeVec_t * vNodes );
 /*=== fpgaUtils.c ===============================================================*/
 extern Fpga_NodeVec_t *  Fpga_MappingDfs( Fpga_Man_t * pMan, int fCollectEquiv );
 extern Fpga_NodeVec_t *  Fpga_MappingDfsNodes( Fpga_Man_t * pMan, Fpga_Node_t ** ppNodes, int nNodes, int fEquiv );
-extern Fpga_NodeVec_t *  Fpga_MappingDfsCutsNode( Fpga_Man_t * pMan, Fpga_Node_t * pNode );
-//extern Sat_IntVec_t *    Fpga_MappingDfsNodesSat( Fpga_Man_t * pMan, Fpga_Node_t ** ppNodes, int nNodes );
-extern Fpga_NodeVec_t *  Fpga_MappingDfsCuts( Fpga_Man_t * pMan );
 extern int               Fpga_CountLevels( Fpga_Man_t * pMan );
-extern int               Fpga_CountLevelsNodes( Fpga_Man_t * pMan, Fpga_Node_t ** ppRoots, int nRoots );
-extern void              Fpga_MappingMarkUsed( Fpga_Man_t * pMan );
 extern float             Fpga_MappingGetAreaFlow( Fpga_Man_t * p );
 extern float             Fpga_MappingArea( Fpga_Man_t * pMan );
-extern float             Fpga_MappingComputeCutAreas( Fpga_Man_t * pMan );
+extern float             Fpga_MappingAreaTrav( Fpga_Man_t * pMan );
 extern float             Fpga_MappingSetRefsAndArea( Fpga_Man_t * pMan );
-extern Fpga_NodeVec_t *  Fpga_MappingCollectRefed( Fpga_Man_t * pMan );
-extern int               Fpga_MappingCountLevels( Fpga_Man_t * pMan );
-extern void              Fpga_MappingUnmark( Fpga_Man_t * pMan );
-extern void              Fpga_MappingUnmark_rec( Fpga_Node_t * pNode );
-extern void              Fpga_MappingMark_rec( Fpga_Node_t * pNode );
-extern void              Fpga_MappedMark_rec( Fpga_Node_t * pNode );
-extern void              Fpga_MappedUnmark_rec( Fpga_Node_t * pNode );
 extern void              Fpga_MappingPrintOutputArrivals( Fpga_Man_t * p );
 extern void              Fpga_MappingSetupTruthTables( unsigned uTruths[][2] );
 extern void              Fpga_MappingSetupMask( unsigned uMask[], int nVarsMax );
@@ -383,7 +371,7 @@ extern void              Fpga_MappingSortByLevel( Fpga_Man_t * pMan, Fpga_NodeVe
 extern Fpga_NodeVec_t *  Fpga_DfsLim( Fpga_Man_t * pMan, Fpga_Node_t * pNode, int nLevels );
 extern Fpga_NodeVec_t *  Fpga_MappingLevelize( Fpga_Man_t * pMan, Fpga_NodeVec_t * vNodes );
 extern float             Fpga_MappingPrintSwitching( Fpga_Man_t * pMan );
-extern int               Fpga_GetMaxLevel( Fpga_Man_t * pMan );
+extern int               Fpga_MappingMaxLevel( Fpga_Man_t * pMan );
 extern void              Fpga_ManReportChoices( Fpga_Man_t * pMan );
 extern void              Fpga_MappingSetChoiceLevels( Fpga_Man_t * pMan );
 
diff --git a/src/map/fpga/fpgaMatch.c b/src/map/fpga/fpgaMatch.c
index 599662f7..63ee682d 100644
--- a/src/map/fpga/fpgaMatch.c
+++ b/src/map/fpga/fpgaMatch.c
@@ -777,59 +777,6 @@ float Fpga_FindBestNode( Fpga_Man_t * p, Fpga_NodeVec_t * vNodes, Fpga_Node_t **
     return Gain;
 }
 
-/**function*************************************************************
-
-  synopsis    [Performs area minimization using a heuristic algorithm.]
-
-  description []
-               
-  sideeffects []
-
-  seealso     []
-
-***********************************************************************/
-void Fpga_MappingExplore( Fpga_Man_t * p )
-{
-    Fpga_Cut_t * pCutBest;
-    Fpga_Node_t * pNodeBest;
-    Fpga_NodeVec_t * vNodes;
-    float Area, Gain, CutArea1, CutArea2;
-    int i;
-
-    // compute the arrival times
-    Fpga_TimePropagateArrival( p );
-    p->fRequiredGlo = Fpga_TimeComputeArrivalMax( p );
-    Fpga_TimeComputeRequired( p, p->fRequiredGlo );
-
-    // assign the refs
-    Area = Fpga_MappingSetRefsAndArea( p );
-    // collect the nodes
-    vNodes = Fpga_MappingCollectRefed( p );
-    // find the best node to update
-    for ( i = 0; Gain = Fpga_FindBestNode(p, vNodes, &pNodeBest, &pCutBest); i++ )
-    {
-        // update the node
-        assert( pNodeBest->pCutBest != pCutBest );
-        // deref the current cut
-        CutArea1 = Fpga_CutDeref( p, pNodeBest, pNodeBest->pCutBest, 0 );
-        // ref the new cut
-        CutArea2 = Fpga_CutRef( p, pNodeBest, pCutBest, 0 );
-        assert( CutArea1 - CutArea2 == Gain );
-        printf( "Iteration %2d: Gain = %5.2f.\n", i, Gain );
-        // update the node
-        pNodeBest->pCutBest = pCutBest;
-        // collect new nodes
-        Fpga_NodeVecFree( vNodes );
-        vNodes = Fpga_MappingCollectRefed( p );
-        // compute the arrival and required times
-        Fpga_TimePropagateArrival( p );
-        Fpga_TimeComputeRequired( p, p->fRequiredGlo );
-    }
-
-
-}
-
-
 ////////////////////////////////////////////////////////////////////////
 ///                       END OF FILE                                ///
 ////////////////////////////////////////////////////////////////////////
diff --git a/src/map/fpga/fpgaTime.c b/src/map/fpga/fpgaTime.c
index 066ae215..6cbe16f9 100644
--- a/src/map/fpga/fpgaTime.c
+++ b/src/map/fpga/fpgaTime.c
@@ -128,21 +128,15 @@ void Fpga_TimeComputeRequiredGlobal( Fpga_Man_t * p )
 ***********************************************************************/
 void Fpga_TimeComputeRequired( Fpga_Man_t * p, float fRequired )
 {
-    Fpga_NodeVec_t * vNodes;
     int i;
-
     // clean the required times and the fanout counts for all nodes
     for ( i = 0; i < p->vAnds->nSize; i++ )
         p->vAnds->pArray[i]->tRequired = FPGA_FLOAT_LARGE;
-
     // set the required times for the POs
     for ( i = 0; i < p->nOutputs; i++ )
         Fpga_Regular(p->pOutputs[i])->tRequired = fRequired;
-
     // collect nodes reachable from POs in the DFS order through the best cuts
-    vNodes = Fpga_MappingDfsCuts( p );
-    Fpga_TimePropagateRequired( p, vNodes );
-    Fpga_NodeVecFree( vNodes );
+    Fpga_TimePropagateRequired( p, p->vMapping );
 }
 
 /**Function*************************************************************
@@ -163,7 +157,9 @@ void Fpga_TimePropagateRequired( Fpga_Man_t * p, Fpga_NodeVec_t * vNodes )
     int i, k;
 
     // sorts the nodes in the decreasing order of levels
-    Fpga_MappingSortByLevel( p, vNodes, 0 );
+//    Fpga_MappingSortByLevel( p, vNodes, 0 );
+    // the nodes area already sorted in Fpga_MappingSetRefsAndArea()
+
     // go through the nodes in the reverse topological order
     for ( k = 0; k < vNodes->nSize; k++ )
     {
diff --git a/src/map/fpga/fpgaUtils.c b/src/map/fpga/fpgaUtils.c
index fc67d52b..bf334afa 100644
--- a/src/map/fpga/fpgaUtils.c
+++ b/src/map/fpga/fpgaUtils.c
@@ -24,15 +24,10 @@
 
 static void  Fpga_MappingDfs_rec( Fpga_Node_t * pNode, Fpga_NodeVec_t * vNodes, int fCollectEquiv );
 static void  Fpga_MappingDfsCuts_rec( Fpga_Node_t * pNode, Fpga_NodeVec_t * vNodes );
-static float Fpga_MappingArea_rec( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_NodeVec_t * vNodes );
-static int   Fpga_MappingCountLevels_rec( Fpga_Node_t * pNode );
-static void  Fpga_MappingMarkUsed_rec( Fpga_Node_t * pNode );
 static int   Fpga_MappingCompareOutputDelay( int * pOut1, int * pOut2 );
-static float Fpga_MappingSetRefsAndArea_rec( Fpga_Man_t * pMan, Fpga_Node_t * pNode );
-static Fpga_Man_t * s_pMan = NULL;
-
 static void  Fpga_DfsLim_rec( Fpga_Node_t * pNode, int Level, Fpga_NodeVec_t * vNodes );
-static int Fpga_CollectNodeTfo_rec( Fpga_Node_t * pNode, Fpga_Node_t * pPivot, Fpga_NodeVec_t * vVisited, Fpga_NodeVec_t * vTfo );
+static int   Fpga_CollectNodeTfo_rec( Fpga_Node_t * pNode, Fpga_Node_t * pPivot, Fpga_NodeVec_t * vVisited, Fpga_NodeVec_t * vTfo );
+static Fpga_Man_t * s_pMan = NULL;
 
 ////////////////////////////////////////////////////////////////////////
 ///                     FUNCTION DEFITIONS                           ///
@@ -131,184 +126,6 @@ Fpga_NodeVec_t * Fpga_MappingDfsNodes( Fpga_Man_t * pMan, Fpga_Node_t ** ppNodes
     return vNodes;
 }
 
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the number of logic levels not counting PIs/POs.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_CountLevels( Fpga_Man_t * pMan )
-{
-    int i, LevelsMax, LevelsCur;
-    // perform the traversal
-    LevelsMax = -1;
-    for ( i = 0; i < pMan->nOutputs; i++ )
-    {
-        LevelsCur = Fpga_Regular(pMan->pOutputs[i])->Level;
-        if ( LevelsMax < LevelsCur )
-            LevelsMax = LevelsCur;
-    }
-    return LevelsMax;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the number of logic levels not counting PIs/POs.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_CountLevelsNodes( Fpga_Man_t * pMan, Fpga_Node_t ** ppRoots, int nRoots )
-{
-    int i, LevelsMax, LevelsCur;
-    // perform the traversal
-    LevelsMax = -1;
-    for ( i = 0; i < nRoots; i++ )
-    {
-        LevelsCur = Fpga_Regular(ppRoots[i])->Level;
-        if ( LevelsMax < LevelsCur )
-            LevelsMax = LevelsCur;
-    }
-    return LevelsMax;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the DFS ordering of the nodes visible in current mapping.]
-
-  Description [The node is visible if it appears as a root of one of the best
-  cuts (that is cuts selected for the current mapping).]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_NodeVec_t * Fpga_MappingDfsCuts( Fpga_Man_t * pMan )
-{
-    Fpga_NodeVec_t * vNodes;
-    int i;
-    // perform the traversal
-    vNodes = Fpga_NodeVecAlloc( 100 );
-    for ( i = 0; i < pMan->nOutputs; i++ )
-        Fpga_MappingDfsCuts_rec( Fpga_Regular(pMan->pOutputs[i]), vNodes );
-    for ( i = 0; i < vNodes->nSize; i++ )
-        vNodes->pArray[i]->fMark0 = 0;
-    return vNodes;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the DFS ordering of the nodes visible in current mapping.]
-
-  Description [The node is visible if it appears as a root of one of the best
-  cuts (that is cuts selected for the current mapping).]
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-Fpga_NodeVec_t * Fpga_MappingDfsCutsNode( Fpga_Man_t * pMan, Fpga_Node_t * pNode )
-{
-    Fpga_NodeVec_t * vNodes;
-    int i;
-    // perform the traversal
-    vNodes = Fpga_NodeVecAlloc( 100 );
-    Fpga_MappingDfsCuts_rec( pNode, vNodes );
-    for ( i = 0; i < vNodes->nSize; i++ )
-        vNodes->pArray[i]->fMark0 = 0;
-    return vNodes;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Recursively computes the DFS ordering of the nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_MappingDfsCuts_rec( Fpga_Node_t * pNode, Fpga_NodeVec_t * vNodes )
-{
-    int i;
-    assert( !Fpga_IsComplement(pNode) );
-    if ( !Fpga_NodeIsAnd(pNode) )
-        return;
-    if ( pNode->fMark0 )
-        return;
-    assert( pNode->pCutBest != NULL );
-    // visit the transitive fanin of the selected cut
-    for ( i = 0; i < pNode->pCutBest->nLeaves; i++ )
-        Fpga_MappingDfsCuts_rec( pNode->pCutBest->ppLeaves[i], vNodes );
-    // make sure the node is not visited through the fanin nodes
-    assert( pNode->fMark0 == 0 );
-    // mark the node as visited
-    pNode->fMark0 = 1;
-    // add the node to the list
-    Fpga_NodeVecPush( vNodes, pNode );
-}
-
-
-/**Function*************************************************************
-
-  Synopsis    [Marks the nodes used in the mapping.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_MappingMarkUsed( Fpga_Man_t * pMan )
-{
-    int i;
-    for ( i = 0; i < pMan->nOutputs; i++ )
-        Fpga_MappingMarkUsed_rec( Fpga_Regular(pMan->pOutputs[i]) );
-}
-
-/**Function*************************************************************
-
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_MappingMarkUsed_rec( Fpga_Node_t * pNode )
-{
-    int i;
-    assert( !Fpga_IsComplement(pNode) );
-    if ( pNode->fUsed )
-        return;
-    pNode->fUsed = 1;
-    if ( !Fpga_NodeIsAnd(pNode) )
-        return;
-    assert( pNode->pCutBest != NULL );
-    // visit the transitive fanin of the selected cut
-    for ( i = 0; i < pNode->pCutBest->nLeaves; i++ )
-        Fpga_MappingMarkUsed_rec( pNode->pCutBest->ppLeaves[i] );
-}
-
-
-
 /**Function*************************************************************
 
   Synopsis    []
@@ -346,22 +163,16 @@ float Fpga_MappingGetAreaFlow( Fpga_Man_t * p )
 ***********************************************************************/
 float Fpga_MappingArea( Fpga_Man_t * pMan )
 {
-    Fpga_NodeVec_t * vNodes;
+    Fpga_Node_t * pNode;
     float aTotal;
     int i;
     // perform the traversal
     aTotal = 0;
-    vNodes = Fpga_NodeVecAlloc( 100 );
-    for ( i = 0; i < pMan->nOutputs; i++ )
+    for ( i = 0; i < pMan->vMapping->nSize; i++ )
     {
-        aTotal += Fpga_MappingArea_rec( pMan, Fpga_Regular(pMan->pOutputs[i]), vNodes );
-        // add the area for single-input nodes (if any) at the POs
-//        if ( Fpga_NodeIsVar(pMan->pOutputs[i]) || Fpga_IsComplement(pMan->pOutputs[i]) )
-//            aTotal += pMan->pLutLib->pLutAreas[1];
+        pNode = pMan->vMapping->pArray[i];
+        aTotal += pMan->pLutLib->pLutAreas[pNode->pCutBest->nLeaves];
     }
-    for ( i = 0; i < vNodes->nSize; i++ )
-        vNodes->pArray[i]->fMark0 = 0;
-    Fpga_NodeVecFree( vNodes );
     return aTotal;
 }
 
@@ -401,10 +212,9 @@ float Fpga_MappingArea_rec( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_NodeVec
     return aArea;
 }
 
-
 /**Function*************************************************************
 
-  Synopsis    [Sets the correct reference counts for the mapping.]
+  Synopsis    [Computes the area of the current mapping.]
 
   Description []
                
@@ -413,55 +223,22 @@ float Fpga_MappingArea_rec( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_NodeVec
   SeeAlso     []
 
 ***********************************************************************/
-float Fpga_MappingComputeCutAreas( Fpga_Man_t * pMan )
+float Fpga_MappingAreaTrav( Fpga_Man_t * pMan )
 {
     Fpga_NodeVec_t * vNodes;
-    Fpga_Node_t * pNode;
-    float Area = 0;
+    float aTotal;
     int i;
-    // collect nodes reachable from POs in the DFS order through the best cuts
-    vNodes = Fpga_MappingDfsCuts( pMan );
+    // perform the traversal
+    aTotal = 0;
+    vNodes = Fpga_NodeVecAlloc( 100 );
+    for ( i = 0; i < pMan->nOutputs; i++ )
+        aTotal += Fpga_MappingArea_rec( pMan, Fpga_Regular(pMan->pOutputs[i]), vNodes );
     for ( i = 0; i < vNodes->nSize; i++ )
-    {
-        pNode = vNodes->pArray[i];
-        pNode->pCutBest->aFlow = Fpga_CutGetAreaRefed( pMan, pNode->pCutBest );
-        Area += pMan->pLutLib->pLutAreas[pNode->pCutBest->nLeaves];
-    }
+        vNodes->pArray[i]->fMark0 = 0;
     Fpga_NodeVecFree( vNodes );
-    return Area;
+    return aTotal;
 }
 
-/**Function*************************************************************
-
-  Synopsis    [Sets the correct reference counts for the mapping.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-float Fpga_MappingSetRefsAndArea( Fpga_Man_t * pMan )
-{
-    Fpga_Node_t * pNode;
-    float aArea;
-    int i;
-    // clean all references
-    for ( i = 0; i < pMan->vNodesAll->nSize; i++ )
-        pMan->vNodesAll->pArray[i]->nRefs = 0;
-    // collect nodes reachable from POs in the DFS order through the best cuts
-    aArea = 0;
-    for ( i = 0; i < pMan->nOutputs; i++ )
-    {
-        pNode = Fpga_Regular(pMan->pOutputs[i]);
-        if ( pNode == pMan->pConst1 )
-            continue;
-        aArea += Fpga_MappingSetRefsAndArea_rec( pMan, pNode );
-        pNode->nRefs++;
-    }
-    return aArea;
-}
 
 /**Function*************************************************************
 
@@ -474,7 +251,7 @@ float Fpga_MappingSetRefsAndArea( Fpga_Man_t * pMan )
   SeeAlso     []
 
 ***********************************************************************/
-float Fpga_MappingSetRefsAndArea_rec( Fpga_Man_t * pMan, Fpga_Node_t * pNode )
+float Fpga_MappingSetRefsAndArea_rec( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_Node_t ** ppStore )
 {
     float aArea;
     int i;
@@ -484,217 +261,63 @@ float Fpga_MappingSetRefsAndArea_rec( Fpga_Man_t * pMan, Fpga_Node_t * pNode )
     if ( !Fpga_NodeIsAnd(pNode) )
         return 0;
     assert( pNode->pCutBest != NULL );
+    // store the node in the structure by level
+    pNode->pData0 = (char *)ppStore[pNode->Level]; 
+    ppStore[pNode->Level] = pNode;
     // visit the transitive fanin of the selected cut
     aArea = pMan->pLutLib->pLutAreas[pNode->pCutBest->nLeaves];
     for ( i = 0; i < pNode->pCutBest->nLeaves; i++ )
-        aArea += Fpga_MappingSetRefsAndArea_rec( pMan, pNode->pCutBest->ppLeaves[i] );
+        aArea += Fpga_MappingSetRefsAndArea_rec( pMan, pNode->pCutBest->ppLeaves[i], ppStore );
     return aArea;
 }
 
 /**Function*************************************************************
 
-  Synopsis    [Collect the referenced nodes.]
+  Synopsis    [Sets the correct reference counts for the mapping.]
 
-  Description []
+  Description [Collects the nodes in reverse topological order
+  and places in them in array pMan->vMapping.]
                
   SideEffects []
 
   SeeAlso     []
 
 ***********************************************************************/
-Fpga_NodeVec_t * Fpga_MappingCollectRefed( Fpga_Man_t * pMan )
+float Fpga_MappingSetRefsAndArea( Fpga_Man_t * pMan )
 {
-    Fpga_NodeVec_t * vNodes;
-    int i;
-    vNodes = Fpga_NodeVecAlloc( 100 );
-    for ( i = 0; i < pMan->vNodesAll->nSize; i++ )
-    {
-        if ( Fpga_NodeIsVar(pMan->vNodesAll->pArray[i]) )
-            continue;
-        if ( pMan->vNodesAll->pArray[i]->nRefs )
-            Fpga_NodeVecPush( vNodes, pMan->vNodesAll->pArray[i] );
-    }
-    return vNodes;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Computes the number of logic levels not counting PIs/POs.]
+    Fpga_Node_t * pNode, ** ppStore;
+    float aArea;
+    int i, LevelMax;
 
-  Description []
-               
-  SideEffects [Note that this procedure will reassign the levels assigned
-  originally by NodeCreate() because it counts the number of levels with 
-  choices differently!]
+    // clean all references
+    for ( i = 0; i < pMan->vNodesAll->nSize; i++ )
+        pMan->vNodesAll->pArray[i]->nRefs = 0;
 
-  SeeAlso     []
+    // allocate place to store the nodes
+    LevelMax = Fpga_MappingMaxLevel( pMan );
+    ppStore = ALLOC( Fpga_Node_t *, LevelMax + 1 );
+    memset( ppStore, 0, sizeof(Fpga_Node_t *) * (LevelMax + 1) );
 
-***********************************************************************/
-int Fpga_MappingCountLevels( Fpga_Man_t * pMan )
-{
-    int i, LevelsMax, LevelsCur;
-    // perform the traversal
-    LevelsMax = -1;
-    for ( i = 0; i < pMan->nOutputs; i++ )
-    {
-        LevelsCur = Fpga_MappingCountLevels_rec( Fpga_Regular(pMan->pOutputs[i]) );
-        if ( LevelsMax < LevelsCur )
-            LevelsMax = LevelsCur;
-    }
+    // collect nodes reachable from POs in the DFS order through the best cuts
+    aArea = 0;
     for ( i = 0; i < pMan->nOutputs; i++ )
-        Fpga_MappingUnmark_rec( Fpga_Regular(pMan->pOutputs[i]) );
-    return LevelsMax;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Recursively computes the number of logic levels.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-int Fpga_MappingCountLevels_rec( Fpga_Node_t * pNode )
-{
-    int Level1, Level2;
-    assert( !Fpga_IsComplement(pNode) );
-    if ( !Fpga_NodeIsAnd(pNode) )
     {
-        pNode->Level = 0;
-        return 0;
+        pNode = Fpga_Regular(pMan->pOutputs[i]);
+        if ( pNode == pMan->pConst1 )
+            continue;
+        aArea += Fpga_MappingSetRefsAndArea_rec( pMan, pNode, ppStore );
+        pNode->nRefs++;
     }
-    if ( pNode->fMark0 )
-        return pNode->Level;
-    pNode->fMark0 = 1;
-    // visit the transitive fanin
-    Level1 = Fpga_MappingCountLevels_rec( Fpga_Regular(pNode->p1) );
-    Level2 = Fpga_MappingCountLevels_rec( Fpga_Regular(pNode->p2) );
-    // set the number of levels
-    pNode->Level = 1 + ((Level1>Level2)? Level1: Level2);
-    return pNode->Level;
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Unmarks the nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_MappingUnmark( Fpga_Man_t * pMan )
-{
-    int i;
-    for ( i = 0; i < pMan->nOutputs; i++ )
-        Fpga_MappingUnmark_rec( Fpga_Regular(pMan->pOutputs[i]) );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Recursively unmarks the nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_MappingUnmark_rec( Fpga_Node_t * pNode )
-{
-    assert( !Fpga_IsComplement(pNode) );
-    if ( pNode->fMark0 == 0 )
-        return;
-    pNode->fMark0 = 0;
-    if ( !Fpga_NodeIsAnd(pNode) )
-        return;
-    Fpga_MappingUnmark_rec( Fpga_Regular(pNode->p1) );
-    Fpga_MappingUnmark_rec( Fpga_Regular(pNode->p2) );
-    // visit the equivalent nodes
-    if ( pNode->pNextE )
-        Fpga_MappingUnmark_rec( pNode->pNextE );
-}
-
-/**Function*************************************************************
-
-  Synopsis    [Recursively unmarks the nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_MappingMark_rec( Fpga_Node_t * pNode )
-{
-    assert( !Fpga_IsComplement(pNode) );
-    if ( pNode->fMark0 == 1 )
-        return;
-    pNode->fMark0 = 1;
-    if ( !Fpga_NodeIsAnd(pNode) )
-        return;
-    Fpga_MappingMark_rec( Fpga_Regular(pNode->p1) );
-    Fpga_MappingMark_rec( Fpga_Regular(pNode->p2) );
-}
-
-/**Function*************************************************************
 
-  Synopsis    []
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_MappedMark_rec( Fpga_Node_t * pNode )
-{
-    int i;
-    assert( !Fpga_IsComplement(pNode) );
-    if ( pNode->fMark0 == 1 )
-        return;
-    pNode->fMark0 = 1;
-    if ( !Fpga_NodeIsAnd(pNode) )
-        return;
-    assert( pNode->pCutBest != NULL );
-    // visit the transitive fanin of the selected cut
-    for ( i = 0; i < pNode->pCutBest->nLeaves; i++ )
-        Fpga_MappedMark_rec( pNode->pCutBest->ppLeaves[i] );
+    // reconnect the nodes in reverse topological order
+    pMan->vMapping->nSize = 0;
+    for ( i = LevelMax; i > 0; i-- )
+        for ( pNode = ppStore[i]; pNode; pNode = (Fpga_Node_t *)pNode->pData0 )
+            Fpga_NodeVecPush( pMan->vMapping, pNode );
+    free( ppStore );
+    return aArea;
 }
 
-/**Function*************************************************************
-
-  Synopsis    [Recursively unmarks the nodes.]
-
-  Description []
-               
-  SideEffects []
-
-  SeeAlso     []
-
-***********************************************************************/
-void Fpga_MappedUnmark_rec( Fpga_Node_t * pNode )
-{
-    int i;
-    assert( !Fpga_IsComplement(pNode) );
-    if ( pNode->fMark0 == 0 )
-        return;
-    pNode->fMark0 = 0;
-    if ( !Fpga_NodeIsAnd(pNode) )
-        return;
-    assert( pNode->pCutBest != NULL );
-    // visit the transitive fanin of the selected cut
-    for ( i = 0; i < pNode->pCutBest->nLeaves; i++ )
-        Fpga_MappedUnmark_rec( pNode->pCutBest->ppLeaves[i] );
-}
 
 /**Function*************************************************************
 
@@ -710,7 +333,7 @@ void Fpga_MappedUnmark_rec( Fpga_Node_t * pNode )
 void Fpga_MappingPrintOutputArrivals( Fpga_Man_t * p )
 {
     Fpga_Node_t * pNode;
-    int fCompl, Limit, i;
+    int fCompl, Limit, MaxNameSize, i;
     int * pSorted;
 
     // sort outputs by arrival time
@@ -723,15 +346,21 @@ void Fpga_MappingPrintOutputArrivals( Fpga_Man_t * p )
     assert( Fpga_MappingCompareOutputDelay( pSorted, pSorted + p->nOutputs - 1 ) <= 0 );
     s_pMan = NULL;
 
-    // print the latest outputs
+    // determine max size of the node's name
+    MaxNameSize = 0;
     Limit = (p->nOutputs > 5)? 5 : p->nOutputs;
     for ( i = 0; i < Limit; i++ )
+        if ( MaxNameSize < (int)strlen(p->ppOutputNames[pSorted[i]]) )
+            MaxNameSize = strlen(p->ppOutputNames[pSorted[i]]);
+
+    // print the latest outputs
+    for ( i = 0; i < Limit; i++ )
     {
         // get the i-th latest output
         pNode  = Fpga_Regular(p->pOutputs[pSorted[i]]);
         fCompl = Fpga_IsComplement(p->pOutputs[pSorted[i]]);
         // print out the best arrival time
-        printf( "Output  %20s : ", p->ppOutputNames[pSorted[i]] );
+        printf( "Output  %-*s : ", MaxNameSize + 3, p->ppOutputNames[pSorted[i]] );
         printf( "Delay = %8.2f  ",     (double)pNode->pCutBest->tArrival );
         if ( fCompl )
             printf( "NEG" );
@@ -1169,7 +798,7 @@ float Fpga_MappingPrintSwitching( Fpga_Man_t * p )
   SeeAlso     []
 
 ***********************************************************************/
-int Fpga_GetMaxLevel( Fpga_Man_t * pMan )
+int Fpga_MappingMaxLevel( Fpga_Man_t * pMan )
 {
     int nLevelMax, i;
     nLevelMax = 0;
@@ -1269,11 +898,11 @@ void Fpga_ManReportChoices( Fpga_Man_t * pMan )
     int i, LevelMax1, LevelMax2;
 
     // report the number of levels
-    LevelMax1 = Fpga_GetMaxLevel( pMan );
+    LevelMax1 = Fpga_MappingMaxLevel( pMan );
     pMan->nTravIds++;
     for ( i = 0; i < pMan->nOutputs; i++ )
         Fpga_MappingUpdateLevel_rec( pMan, Fpga_Regular(pMan->pOutputs[i]), 0 );
-    LevelMax2 = Fpga_GetMaxLevel( pMan );
+    LevelMax2 = Fpga_MappingMaxLevel( pMan );
 
     // report statistics about choices
     nChoiceNodes = nChoices = 0;