Version abc50806

5 files changed, 174 insertions, 0 deletions

diff --git a/src/map/fpga/fpgaCore.c b/src/map/fpga/fpgaCore.c
index 37726542..457c2384 100644
--- a/src/map/fpga/fpgaCore.c
+++ b/src/map/fpga/fpgaCore.c
@@ -127,12 +127,19 @@ int Fpga_MappingPostProcess( Fpga_Man_t * p )
     float aSwitchTotalPrev, aSwitchTotalCur;
     int Iter, clk;
 
+
 if ( p->fVerbose )
 {
 printf( "Iteration %dD :  Area = %11.1f  ", 0, Fpga_MappingArea( p ) );
 PRT( "Time", p->timeMatch );
 }
 
+
+//    Fpga_MappingExplore( p );
+//    p->fAreaGlo = Fpga_MappingArea( p );
+//    return;
+
+
 //    aAreaTotalCur = FPGA_FLOAT_LARGE;
     aAreaTotalCur = Fpga_MappingSetRefsAndArea( p );
 
@@ -159,6 +166,11 @@ PRT( "Time", clock() - clk );
     } while ( aAreaTotalPrev > 1.02 * aAreaTotalCur );
 
 
+//    Fpga_MappingExplore( p );
+//    p->fAreaGlo = Fpga_MappingArea( p );
+//    return;
+
+
 /*
     // compute the area of each cut
     aAreaTotalCur = Fpga_MappingSetRefsAndArea( p );
diff --git a/src/map/fpga/fpgaInt.h b/src/map/fpga/fpgaInt.h
index 0fea9ec8..63308d53 100644
--- a/src/map/fpga/fpgaInt.h
+++ b/src/map/fpga/fpgaInt.h
@@ -334,6 +334,7 @@ extern float             Fpga_TimeComputeArrivalMax( Fpga_Man_t * p );
 extern void              Fpga_TimeComputeRequiredGlobal( Fpga_Man_t * p );
 extern void              Fpga_TimeComputeRequired( Fpga_Man_t * p, float fRequired );
 extern void              Fpga_TimePropagateRequired( Fpga_Man_t * p, Fpga_NodeVec_t * vNodes );
+extern void              Fpga_TimePropagateArrival( Fpga_Man_t * p );
 /*=== fpgaTruth.c ===============================================================*/
 extern void              Fpga_MappingTruths( Fpga_Man_t * pMan );
 /*=== fpgaVec.c =============================================================*/
@@ -368,6 +369,7 @@ extern float             Fpga_MappingGetAreaFlow( Fpga_Man_t * p );
 extern float             Fpga_MappingArea( Fpga_Man_t * pMan );
 extern float             Fpga_MappingComputeCutAreas( Fpga_Man_t * pMan );
 extern float             Fpga_MappingSetRefsAndArea( Fpga_Man_t * pMan );
+extern Fpga_NodeVec_t *  Fpga_MappingCollectRefed( Fpga_Man_t * pMan );
 extern int               Fpga_MappingCountLevels( Fpga_Man_t * pMan );
 extern void              Fpga_MappingUnmark( Fpga_Man_t * pMan );
 extern void              Fpga_MappingUnmark_rec( Fpga_Node_t * pNode );
diff --git a/src/map/fpga/fpgaMatch.c b/src/map/fpga/fpgaMatch.c
index 8668ce4b..599662f7 100644
--- a/src/map/fpga/fpgaMatch.c
+++ b/src/map/fpga/fpgaMatch.c
@@ -724,6 +724,112 @@ clk = clock();
 }
 
 #endif
+
+
+/**function*************************************************************
+
+  synopsis    [Performs area minimization using a heuristic algorithm.]
+
+  description []
+               
+  sideeffects []
+
+  seealso     []
+
+***********************************************************************/
+float Fpga_FindBestNode( Fpga_Man_t * p, Fpga_NodeVec_t * vNodes, Fpga_Node_t ** ppNode, Fpga_Cut_t ** ppCutBest )
+{
+    Fpga_Node_t * pNode;
+    Fpga_Cut_t * pCut;
+    float Gain, CutArea1, CutArea2, CutArea3;
+    int i;
+
+    Gain = 0;
+    for ( i = 0; i < vNodes->nSize; i++ )
+    {
+        pNode = vNodes->pArray[i];
+        // deref the current cut
+        CutArea1 = Fpga_CutDeref( p, pNode, pNode->pCutBest, 0 );
+
+        // ref all the cuts
+        for ( pCut = pNode->pCuts->pNext; pCut; pCut = pCut->pNext )
+        {
+            if ( pCut == pNode->pCutBest )
+                continue;
+            if ( pCut->tArrival > pNode->tRequired )
+                continue;
+
+            CutArea2 = Fpga_CutGetAreaDerefed( p, pCut );
+            if ( Gain < CutArea1 - CutArea2 )
+            {
+                *ppNode = pNode;
+                *ppCutBest = pCut;
+                Gain = CutArea1 - CutArea2;
+            }
+        }
+        // ref the old cut
+        CutArea3 = Fpga_CutRef( p, pNode, pNode->pCutBest, 0 );
+        assert( CutArea1 == CutArea3 );
+    }
+    if ( Gain == 0 )
+        printf( "Returning no gain.\n" );
+
+    return Gain;
+}
+
+/**function*************************************************************
+
+  synopsis    [Performs area minimization using a heuristic algorithm.]
+
+  description []
+               
+  sideeffects []
+
+  seealso     []
+
+***********************************************************************/
+void Fpga_MappingExplore( Fpga_Man_t * p )
+{
+    Fpga_Cut_t * pCutBest;
+    Fpga_Node_t * pNodeBest;
+    Fpga_NodeVec_t * vNodes;
+    float Area, Gain, CutArea1, CutArea2;
+    int i;
+
+    // compute the arrival times
+    Fpga_TimePropagateArrival( p );
+    p->fRequiredGlo = Fpga_TimeComputeArrivalMax( p );
+    Fpga_TimeComputeRequired( p, p->fRequiredGlo );
+
+    // assign the refs
+    Area = Fpga_MappingSetRefsAndArea( p );
+    // collect the nodes
+    vNodes = Fpga_MappingCollectRefed( p );
+    // find the best node to update
+    for ( i = 0; Gain = Fpga_FindBestNode(p, vNodes, &pNodeBest, &pCutBest); i++ )
+    {
+        // update the node
+        assert( pNodeBest->pCutBest != pCutBest );
+        // deref the current cut
+        CutArea1 = Fpga_CutDeref( p, pNodeBest, pNodeBest->pCutBest, 0 );
+        // ref the new cut
+        CutArea2 = Fpga_CutRef( p, pNodeBest, pCutBest, 0 );
+        assert( CutArea1 - CutArea2 == Gain );
+        printf( "Iteration %2d: Gain = %5.2f.\n", i, Gain );
+        // update the node
+        pNodeBest->pCutBest = pCutBest;
+        // collect new nodes
+        Fpga_NodeVecFree( vNodes );
+        vNodes = Fpga_MappingCollectRefed( p );
+        // compute the arrival and required times
+        Fpga_TimePropagateArrival( p );
+        Fpga_TimeComputeRequired( p, p->fRequiredGlo );
+    }
+
+
+}
+
+
 ////////////////////////////////////////////////////////////////////////
 ///                       END OF FILE                                ///
 ////////////////////////////////////////////////////////////////////////
diff --git a/src/map/fpga/fpgaTime.c b/src/map/fpga/fpgaTime.c
index df98faa1..066ae215 100644
--- a/src/map/fpga/fpgaTime.c
+++ b/src/map/fpga/fpgaTime.c
@@ -182,6 +182,34 @@ void Fpga_TimePropagateRequired( Fpga_Man_t * p, Fpga_NodeVec_t * vNodes )
 }
 
 
+
+/**Function*************************************************************
+
+  Synopsis    [Computes the required times of all nodes.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Fpga_TimePropagateArrival( Fpga_Man_t * p )
+{
+    Fpga_Node_t * pNode;
+    Fpga_Cut_t * pCut;
+    int i;
+
+    // clean the required times and the fanout counts for all nodes
+    for ( i = 0; i < p->vAnds->nSize; i++ )
+    {
+        pNode = p->vAnds->pArray[i];
+        for ( pCut = pNode->pCuts->pNext; pCut; pCut = pCut->pNext )
+            pCut->tArrival = Fpga_TimeCutComputeArrival( p, pCut );
+    }
+}
+
+
 ////////////////////////////////////////////////////////////////////////
 ///                       END OF FILE                                ///
 ////////////////////////////////////////////////////////////////////////
diff --git a/src/map/fpga/fpgaUtils.c b/src/map/fpga/fpgaUtils.c
index a5b2cb32..fc67d52b 100644
--- a/src/map/fpga/fpgaUtils.c
+++ b/src/map/fpga/fpgaUtils.c
@@ -493,6 +493,32 @@ float Fpga_MappingSetRefsAndArea_rec( Fpga_Man_t * pMan, Fpga_Node_t * pNode )
 
 /**Function*************************************************************
 
+  Synopsis    [Collect the referenced nodes.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+Fpga_NodeVec_t * Fpga_MappingCollectRefed( Fpga_Man_t * pMan )
+{
+    Fpga_NodeVec_t * vNodes;
+    int i;
+    vNodes = Fpga_NodeVecAlloc( 100 );
+    for ( i = 0; i < pMan->vNodesAll->nSize; i++ )
+    {
+        if ( Fpga_NodeIsVar(pMan->vNodesAll->pArray[i]) )
+            continue;
+        if ( pMan->vNodesAll->pArray[i]->nRefs )
+            Fpga_NodeVecPush( vNodes, pMan->vNodesAll->pArray[i] );
+    }
+    return vNodes;
+}
+
+/**Function*************************************************************
+
   Synopsis    [Computes the number of logic levels not counting PIs/POs.]
 
   Description []