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author | Alan Mishchenko <alanmi@berkeley.edu> | 2014-09-19 19:06:01 -0700 |
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committer | Alan Mishchenko <alanmi@berkeley.edu> | 2014-09-19 19:06:01 -0700 |
commit | a02b0203568f4c20f50c81e26603c3a5ee4083eb (patch) | |
tree | fe1bda9a7f1699798a9e56c22615c2749ff22069 /src/map/if/ifDelay.c | |
parent | f989aea224760cc35f5b3bf232e9dccac4f1baa4 (diff) | |
download | abc-a02b0203568f4c20f50c81e26603c3a5ee4083eb.tar.gz abc-a02b0203568f4c20f50c81e26603c3a5ee4083eb.tar.bz2 abc-a02b0203568f4c20f50c81e26603c3a5ee4083eb.zip |
Updating DSD balance to handle XOR gate as having the same delay as AND gate.
Diffstat (limited to 'src/map/if/ifDelay.c')
-rw-r--r-- | src/map/if/ifDelay.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/map/if/ifDelay.c b/src/map/if/ifDelay.c index da4801b4..5afb77eb 100644 --- a/src/map/if/ifDelay.c +++ b/src/map/if/ifDelay.c @@ -204,9 +204,9 @@ int If_CutSopBalanceEvalInt( Vec_Int_t * vCover, int * pTimes, int * pFaninLits, { Literal = 3 & (Entry >> (k << 1)); if ( Literal == 1 ) // neg literal - nLits++, Delay = If_LogCounterAddAig( pCounterAnd, &nCounterAnd, pFaninLitsAnd, pTimes[k], Abc_LitNot(pFaninLits[k]), vAig, nSuppAll, 0 ); + nLits++, Delay = If_LogCounterAddAig( pCounterAnd, &nCounterAnd, pFaninLitsAnd, pTimes[k], Abc_LitNot(pFaninLits[k]), vAig, nSuppAll, 0, 0 ); else if ( Literal == 2 ) // pos literal - nLits++, Delay = If_LogCounterAddAig( pCounterAnd, &nCounterAnd, pFaninLitsAnd, pTimes[k], pFaninLits[k], vAig, nSuppAll, 0 ); + nLits++, Delay = If_LogCounterAddAig( pCounterAnd, &nCounterAnd, pFaninLitsAnd, pTimes[k], pFaninLits[k], vAig, nSuppAll, 0, 0 ); else if ( Literal != 0 ) assert( 0 ); } @@ -216,7 +216,7 @@ int If_CutSopBalanceEvalInt( Vec_Int_t * vCover, int * pTimes, int * pFaninLits, iRes = If_LogCreateAndXorMulti( vAig, pFaninLitsAnd, nCounterAnd, nSuppAll, 0 ); else *pArea += nLits == 1 ? 0 : nLits - 1; - Delay = If_LogCounterAddAig( pCounterOr, &nCounterOr, pFaninLitsOr, Delay, Abc_LitNot(iRes), vAig, nSuppAll, 0 ); + Delay = If_LogCounterAddAig( pCounterOr, &nCounterOr, pFaninLitsOr, Delay, Abc_LitNot(iRes), vAig, nSuppAll, 0, 0 ); } assert( nCounterOr > 0 ); if ( vAig ) |