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author | Alan Mishchenko <alanmi@berkeley.edu> | 2013-09-15 18:23:49 -0700 |
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committer | Alan Mishchenko <alanmi@berkeley.edu> | 2013-09-15 18:23:49 -0700 |
commit | ff5d3591d1e7d90199d7395cde9fc6d902ed4b41 (patch) | |
tree | 26a2307c387d50bcd1a01e007bfe370ca8a5a9e3 /src/map/scl/sclLibUtil.c | |
parent | d1fed2dd89bc0549655f8375832628b18b35edd9 (diff) | |
download | abc-ff5d3591d1e7d90199d7395cde9fc6d902ed4b41.tar.gz abc-ff5d3591d1e7d90199d7395cde9fc6d902ed4b41.tar.bz2 abc-ff5d3591d1e7d90199d7395cde9fc6d902ed4b41.zip |
Infrastructure to support full Liberty format and unitification of library representations.
Diffstat (limited to 'src/map/scl/sclLibUtil.c')
-rw-r--r-- | src/map/scl/sclLibUtil.c | 608 |
1 files changed, 608 insertions, 0 deletions
diff --git a/src/map/scl/sclLibUtil.c b/src/map/scl/sclLibUtil.c new file mode 100644 index 00000000..53792098 --- /dev/null +++ b/src/map/scl/sclLibUtil.c @@ -0,0 +1,608 @@ +/**CFile**************************************************************** + + FileName [sclLibUtil.c] + + SystemName [ABC: Logic synthesis and verification system.] + + PackageName [Standard-cell library representation.] + + Synopsis [Various library utilities.] + + Author [Alan Mishchenko, Niklas Een] + + Affiliation [UC Berkeley] + + Date [Ver. 1.0. Started - August 24, 2012.] + + Revision [$Id: sclLibUtil.c,v 1.0 2012/08/24 00:00:00 alanmi Exp $] + +***********************************************************************/ + +#include "sclLib.h" +#include "misc/st/st.h" +#include "map/mio/mio.h" +#include "bool/kit/kit.h" + +ABC_NAMESPACE_IMPL_START + + +//////////////////////////////////////////////////////////////////////// +/// DECLARATIONS /// +//////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////// +/// FUNCTION DEFINITIONS /// +//////////////////////////////////////////////////////////////////////// + +/**Function************************************************************* + + Synopsis [Reading library from file.] + + Description [] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ +static unsigned Abc_SclHashString( char * pName, int TableSize ) +{ + static int s_Primes[10] = { 1291, 1699, 2357, 4177, 5147, 5647, 6343, 7103, 7873, 8147 }; + unsigned i, Key = 0; + for ( i = 0; pName[i] != '\0'; i++ ) + Key += s_Primes[i%10]*pName[i]*pName[i]; + return Key % TableSize; +} +int * Abc_SclHashLookup( SC_Lib * p, char * pName ) +{ + int i; + for ( i = Abc_SclHashString(pName, p->nBins); i < p->nBins; i = (i + 1) % p->nBins ) + if ( p->pBins[i] == -1 || !strcmp(pName, SC_LibCell(p, p->pBins[i])->pName) ) + return p->pBins + i; + assert( 0 ); + return NULL; +} +void Abc_SclHashCells( SC_Lib * p ) +{ + SC_Cell * pCell; + int i, * pPlace; + assert( p->nBins == 0 ); + p->nBins = Abc_PrimeCudd( 5 * Vec_PtrSize(p->vCells) ); + p->pBins = ABC_FALLOC( int, p->nBins ); + SC_LibForEachCell( p, pCell, i ) + { + pPlace = Abc_SclHashLookup( p, pCell->pName ); + assert( *pPlace == -1 ); + *pPlace = i; + } +} +int Abc_SclCellFind( SC_Lib * p, char * pName ) +{ + int *pPlace = Abc_SclHashLookup( p, pName ); + return pPlace ? *pPlace : -1; +} +int Abc_SclClassCellNum( SC_Cell * pClass ) +{ + SC_Cell * pCell; + int i, Count = 0; + SC_RingForEachCell( pClass, pCell, i ) + if ( !pCell->fSkip ) + Count++; + return Count; +} + +/**Function************************************************************* + + Synopsis [Links equal gates into rings while sorting them by area.] + + Description [] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ +static int Abc_SclCompareCells( SC_Cell ** pp1, SC_Cell ** pp2 ) +{ + if ( (*pp1)->n_inputs < (*pp2)->n_inputs ) + return -1; + if ( (*pp1)->n_inputs > (*pp2)->n_inputs ) + return 1; +// if ( (*pp1)->area < (*pp2)->area ) +// return -1; +// if ( (*pp1)->area > (*pp2)->area ) +// return 1; + if ( SC_CellPinCapAve(*pp1) < SC_CellPinCapAve(*pp2) ) + return -1; + if ( SC_CellPinCapAve(*pp1) > SC_CellPinCapAve(*pp2) ) + return 1; + return strcmp( (*pp1)->pName, (*pp2)->pName ); +} +void Abc_SclLinkCells( SC_Lib * p ) +{ + Vec_Ptr_t * vList; + SC_Cell * pCell, * pRepr = NULL; + int i, k; + assert( Vec_PtrSize(p->vCellClasses) == 0 ); + SC_LibForEachCell( p, pCell, i ) + { + // find gate with the same function + SC_LibForEachCellClass( p, pRepr, k ) + if ( pCell->n_inputs == pRepr->n_inputs && + pCell->n_outputs == pRepr->n_outputs && + Vec_WrdEqual(SC_CellFunc(pCell), SC_CellFunc(pRepr)) ) + break; + if ( k == Vec_PtrSize(p->vCellClasses) ) + { + Vec_PtrPush( p->vCellClasses, pCell ); + pCell->pNext = pCell->pPrev = pCell; + continue; + } + // add it to the list before the cell + pRepr->pPrev->pNext = pCell; pCell->pNext = pRepr; + pCell->pPrev = pRepr->pPrev; pRepr->pPrev = pCell; + } + // sort cells by size then by name + qsort( (void *)Vec_PtrArray(p->vCellClasses), Vec_PtrSize(p->vCellClasses), sizeof(void *), (int(*)(const void *,const void *))Abc_SclCompareCells ); + // sort cell lists + vList = Vec_PtrAlloc( 100 ); + SC_LibForEachCellClass( p, pRepr, k ) + { + Vec_PtrClear( vList ); + SC_RingForEachCell( pRepr, pCell, i ) + Vec_PtrPush( vList, pCell ); + qsort( (void *)Vec_PtrArray(vList), Vec_PtrSize(vList), sizeof(void *), (int(*)(const void *,const void *))Abc_SclCompareCells ); + // create new representative + pRepr = (SC_Cell *)Vec_PtrEntry( vList, 0 ); + pRepr->pNext = pRepr->pPrev = pRepr; + pRepr->pRepr = pRepr; + pRepr->pAve = (SC_Cell *)Vec_PtrEntry( vList, Vec_PtrSize(vList)/2 ); + pRepr->Order = 0; + pRepr->nGates = Vec_PtrSize(vList); + // relink cells + Vec_PtrForEachEntryStart( SC_Cell *, vList, pCell, i, 1 ) + { + pRepr->pPrev->pNext = pCell; pCell->pNext = pRepr; + pCell->pPrev = pRepr->pPrev; pRepr->pPrev = pCell; + pCell->pRepr = pRepr; + pCell->pAve = (SC_Cell *)Vec_PtrEntry( vList, Vec_PtrSize(vList)/2 ); + pCell->Order = i; + pCell->nGates = Vec_PtrSize(vList); + } + // update list + Vec_PtrWriteEntry( p->vCellClasses, k, pRepr ); + } + Vec_PtrFree( vList ); +} + +/**Function************************************************************* + + Synopsis [Returns the largest inverter.] + + Description [] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ +SC_Cell * Abc_SclFindInvertor( SC_Lib * p, int fFindBuff ) +{ + SC_Cell * pCell = NULL; + word Truth = fFindBuff ? ABC_CONST(0xAAAAAAAAAAAAAAAA) : ABC_CONST(0x5555555555555555); + int k; + SC_LibForEachCellClass( p, pCell, k ) + if ( pCell->n_inputs == 1 && Vec_WrdEntry(SC_CellPin(pCell, 1)->vFunc, 0) == Truth ) + break; + // take representative + return pCell ? pCell->pRepr : NULL; +} +SC_Cell * Abc_SclFindSmallestGate( SC_Cell * p, float CinMin ) +{ + SC_Cell * pRes = NULL; + int i; + SC_RingForEachCell( p->pRepr, pRes, i ) + if ( SC_CellPinCapAve(pRes) > CinMin ) + return pRes; + // take the largest gate + return p->pRepr->pPrev; +} + +/**Function************************************************************* + + Synopsis [Returns the wireload model for the given area.] + + Description [] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ +SC_WireLoad * Abc_SclFetchWireLoadModel( SC_Lib * p, char * pWLoadUsed ) +{ + SC_WireLoad * pWL = NULL; + int i; + // Get the actual table and reformat it for 'wire_cap' output: + assert( pWLoadUsed != NULL ); + SC_LibForEachWireLoad( p, pWL, i ) + if ( !strcmp(pWL->pName, pWLoadUsed) ) + break; + if ( i == Vec_PtrSize(p->vWireLoads) ) + { + Abc_Print( -1, "Cannot find wire load model \"%s\".\n", pWLoadUsed ); + exit(1); + } +// printf( "Using wireload model \"%s\".\n", pWL->pName ); + return pWL; +} +SC_WireLoad * Abc_SclFindWireLoadModel( SC_Lib * p, float Area ) +{ + char * pWLoadUsed = NULL; + int i; + if ( p->default_wire_load_sel && strlen(p->default_wire_load_sel) ) + { + SC_WireLoadSel * pWLS = NULL; + SC_LibForEachWireLoadSel( p, pWLS, i ) + if ( !strcmp(pWLS->pName, p->default_wire_load_sel) ) + break; + if ( i == Vec_PtrSize(p->vWireLoadSels) ) + { + Abc_Print( -1, "Cannot find wire load selection model \"%s\".\n", p->default_wire_load_sel ); + exit(1); + } + for ( i = 0; i < Vec_FltSize(pWLS->vAreaFrom); i++) + if ( Area >= Vec_FltEntry(pWLS->vAreaFrom, i) && Area < Vec_FltEntry(pWLS->vAreaTo, i) ) + { + pWLoadUsed = (char *)Vec_PtrEntry(pWLS->vWireLoadModel, i); + break; + } + if ( i == Vec_FltSize(pWLS->vAreaFrom) ) + pWLoadUsed = (char *)Vec_PtrEntryLast(pWLS->vWireLoadModel); + } + else if ( p->default_wire_load && strlen(p->default_wire_load) ) + pWLoadUsed = p->default_wire_load; + else + { + Abc_Print( 0, "No wire model given.\n" ); + return NULL; + } + return Abc_SclFetchWireLoadModel( p, pWLoadUsed ); +} + +/**Function************************************************************* + + Synopsis [Compute delay parameters of pin/cell/class.] + + Description [] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ +void Abc_SclComputeParametersPin( SC_Lib * p, SC_Cell * pCell, int iPin, float Slew, float * pLD, float * pPD ) +{ + SC_Pair Load0, Load1, Load2; + SC_Pair ArrIn = { 0.0, 0.0 }; + SC_Pair SlewIn = { Slew, Slew }; + SC_Pair ArrOut0 = { 0.0, 0.0 }; + SC_Pair ArrOut1 = { 0.0, 0.0 }; + SC_Pair ArrOut2 = { 0.0, 0.0 }; + SC_Pair SlewOut = { 0.0, 0.0 }; + SC_Timing * pTime = Scl_CellPinTime( pCell, iPin ); + Vec_Flt_t * vIndex = pTime->pCellRise->vIndex1; // capacitance + // get load points + Load0.rise = Load0.fall = 0.0; + Load1.rise = Load1.fall = Vec_FltEntry( vIndex, 0 ); + Load2.rise = Load2.fall = Vec_FltEntry( vIndex, Vec_FltSize(vIndex) - 2 ); + // compute delay + Scl_LibPinArrival( pTime, &ArrIn, &SlewIn, &Load0, &ArrOut0, &SlewOut ); + Scl_LibPinArrival( pTime, &ArrIn, &SlewIn, &Load1, &ArrOut1, &SlewOut ); + Scl_LibPinArrival( pTime, &ArrIn, &SlewIn, &Load2, &ArrOut2, &SlewOut ); + ArrOut0.rise = 0.5 * ArrOut0.rise + 0.5 * ArrOut0.fall; + ArrOut1.rise = 0.5 * ArrOut1.rise + 0.5 * ArrOut1.fall; + ArrOut2.rise = 0.5 * ArrOut2.rise + 0.5 * ArrOut2.fall; + // get tangent + *pLD = (ArrOut2.rise - ArrOut1.rise) / ((Load2.rise - Load1.rise) / SC_CellPinCap(pCell, iPin)); + // get constant + *pPD = ArrOut0.rise; +} +void Abc_SclComputeParametersCell( SC_Lib * p, SC_Cell * pCell, float Slew, float * pLD, float * pPD ) +{ + SC_Pin * pPin; + float LD, PD, ld, pd; + int i; + LD = PD = ld = pd = 0; + SC_CellForEachPinIn( pCell, pPin, i ) + { + Abc_SclComputeParametersPin( p, pCell, i, Slew, &ld, &pd ); + LD += ld; PD += pd; + } + *pLD = LD / Abc_MaxInt(1, pCell->n_inputs); + *pPD = PD / Abc_MaxInt(1, pCell->n_inputs); +} +void Abc_SclComputeParametersClass( SC_Lib * p, SC_Cell * pRepr, float Slew, float * pLD, float * pPD ) +{ + SC_Cell * pCell; + float LD, PD, ld, pd; + int i, Count = 0; + LD = PD = ld = pd = 0; + SC_RingForEachCell( pRepr, pCell, i ) + { + Abc_SclComputeParametersCell( p, pCell, Slew, &ld, &pd ); + LD += ld; PD += pd; + Count++; + } + *pLD = LD / Abc_MaxInt(1, Count); + *pPD = PD / Abc_MaxInt(1, Count); +} +void Abc_SclComputeParametersClassPin( SC_Lib * p, SC_Cell * pRepr, int iPin, float Slew, float * pLD, float * pPD ) +{ + SC_Cell * pCell; + float LD, PD, ld, pd; + int i, Count = 0; + LD = PD = ld = pd = 0; + SC_RingForEachCell( pRepr, pCell, i ) + { + Abc_SclComputeParametersPin( p, pCell, iPin, Slew, &ld, &pd ); + LD += ld; PD += pd; + Count++; + } + *pLD = LD / Abc_MaxInt(1, Count); + *pPD = PD / Abc_MaxInt(1, Count); +} +float Abc_SclComputeDelayCellPin( SC_Lib * p, SC_Cell * pCell, int iPin, float Slew, float Gain ) +{ + float LD = 0, PD = 0; + Abc_SclComputeParametersPin( p, pCell, iPin, Slew, &LD, &PD ); + return 0.01 * LD * Gain + PD; +} +float Abc_SclComputeDelayClassPin( SC_Lib * p, SC_Cell * pRepr, int iPin, float Slew, float Gain ) +{ + SC_Cell * pCell; + float Delay = 0; + int i, Count = 0; + SC_RingForEachCell( pRepr, pCell, i ) + { + if ( pCell->fSkip ) + continue; +// if ( pRepr == pCell ) // skip the first gate +// continue; + Delay += Abc_SclComputeDelayCellPin( p, pCell, iPin, Slew, Gain ); + Count++; + } + return Delay / Abc_MaxInt(1, Count); +} +float Abc_SclComputeAreaClass( SC_Cell * pRepr ) +{ + SC_Cell * pCell; + float Area = 0; + int i, Count = 0; + SC_RingForEachCell( pRepr, pCell, i ) + { + if ( pCell->fSkip ) + continue; + Area += pCell->area; + Count++; + } + return Area / Abc_MaxInt(1, Count); +} + +/**Function************************************************************* + + Synopsis [Print cells] + + Description [] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ +void Abc_SclMarkSkippedCells( SC_Lib * p ) +{ + char FileName[1000]; + char Buffer[1000], * pName; + SC_Cell * pCell; + FILE * pFile; + int CellId, nSkipped = 0; + sprintf( FileName, "%s.skip", p->pName ); + pFile = fopen( FileName, "rb" ); + if ( pFile == NULL ) + return; + while ( fgets( Buffer, 999, pFile ) != NULL ) + { + pName = strtok( Buffer, "\r\n\t " ); + if ( pName == NULL ) + continue; + CellId = Abc_SclCellFind( p, pName ); + if ( CellId == -1 ) + { + printf( "Cannot find cell \"%s\" in the library \"%s\".\n", pName, p->pName ); + continue; + } + pCell = SC_LibCell( p, CellId ); + pCell->fSkip = 1; + nSkipped++; + } + fclose( pFile ); + printf( "Marked %d cells for skipping in the library \"%s\".\n", nSkipped, p->pName ); +} +void Abc_SclPrintCells( SC_Lib * p, float Slew, float Gain, int fInvOnly, int fShort ) +{ + SC_Cell * pCell, * pRepr; + SC_Pin * pPin; + int i, j, k, nLength = 0; + float LD = 0, PD = 0; + assert( Vec_PtrSize(p->vCellClasses) > 0 ); + printf( "Library \"%s\" ", p->pName ); + printf( "has %d cells in %d classes. ", + Vec_PtrSize(p->vCells), Vec_PtrSize(p->vCellClasses) ); + if ( !fShort ) + printf( "Delay estimate is based on slew %.2f and gain %.2f.", Slew, Gain ); + printf( "\n" ); + Abc_SclMarkSkippedCells( p ); + // find the longest name + SC_LibForEachCellClass( p, pRepr, k ) + SC_RingForEachCell( pRepr, pCell, i ) + nLength = Abc_MaxInt( nLength, strlen(pRepr->pName) ); + // print cells + SC_LibForEachCellClass( p, pRepr, k ) + { + if ( fInvOnly && pRepr->n_inputs != 1 ) + continue; + SC_CellForEachPinOut( pRepr, pPin, i ) + { + if ( i == pRepr->n_inputs ) + { + printf( "Class%4d : ", k ); + printf( "Cells =%3d ", Abc_SclClassCellNum(pRepr) ); + printf( "Ins =%2d ", pRepr->n_inputs ); + printf( "Outs =%2d ", pRepr->n_outputs ); + } + else + printf( " " ); + if ( pPin->func_text ) + printf( "%-30s", pPin->func_text ); + printf( " " ); + Kit_DsdPrintFromTruth( (unsigned *)Vec_WrdArray(pPin->vFunc), pRepr->n_inputs ); + printf( "\n" ); + if ( fShort ) + continue; + SC_RingForEachCell( pRepr, pCell, j ) + { + Abc_SclComputeParametersCell( p, pCell, Slew, &LD, &PD ); + printf( " %3d ", j+1 ); + printf( "%s", pCell->fSkip ? "s" : " " ); + printf( " : " ); + printf( "%-*s ", nLength, pCell->pName ); + printf( "%2d ", pCell->drive_strength ); + printf( "A =%8.2f ", pCell->area ); + printf( "D =%6.1f ps ", 0.01 * Gain * LD + PD ); + printf( "LD =%6.1f ps ", LD ); + printf( "PD =%6.1f ps ", PD ); + printf( "C =%5.1f ff ", SC_LibCapFf(p, SC_CellPinCapAve(pCell)) ); + printf( "Cm =%5.0f ff ", SC_LibCapFf(p, SC_CellPin(pCell, pCell->n_inputs)->max_out_cap) ); + printf( "Sm =%5.1f ps ", SC_LibTimePs(p, SC_CellPin(pCell, pCell->n_inputs)->max_out_slew) ); + printf( "\n" ); + } + break; + } + } +} + +/**Function************************************************************* + + Synopsis [Derive GENLIB library.] + + Description [] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ +Vec_Str_t * Abc_SclDeriveGenlibStr( SC_Lib * p, float Slew, float Gain, int nGatesMin, int * pnCellCount ) +{ + char Buffer[200]; + Vec_Str_t * vStr; + SC_Cell * pRepr; + SC_Pin * pPin; + int i, k, Count = 2, nClassMax = 0; + // find the largest number of cells in a class + SC_LibForEachCellClass( p, pRepr, i ) + if ( pRepr->n_outputs == 1 ) + nClassMax = Abc_MaxInt( nClassMax, Abc_SclClassCellNum(pRepr) ); + // update the number + if ( nGatesMin && nGatesMin >= nClassMax ) + nGatesMin = 0; + // mark skipped cells + Abc_SclMarkSkippedCells( p ); + vStr = Vec_StrAlloc( 1000 ); + Vec_StrPrintStr( vStr, "GATE _const0_ 0.00 z=CONST0;\n" ); + Vec_StrPrintStr( vStr, "GATE _const1_ 0.00 z=CONST1;\n" ); + SC_LibForEachCellClass( p, pRepr, i ) + { + if ( pRepr->n_inputs == 0 ) + continue; + if ( pRepr->n_outputs > 1 ) + continue; + if ( nGatesMin && pRepr->n_inputs > 2 && Abc_SclClassCellNum(pRepr) < nGatesMin ) + continue; + assert( strlen(pRepr->pName) < 200 ); + Vec_StrPrintStr( vStr, "GATE " ); + sprintf( Buffer, "%-16s", pRepr->pName ); + Vec_StrPrintStr( vStr, Buffer ); + Vec_StrPrintStr( vStr, " " ); +// sprintf( Buffer, "%7.2f", Abc_SclComputeAreaClass(pRepr) ); + sprintf( Buffer, "%7.2f", pRepr->area ); + Vec_StrPrintStr( vStr, Buffer ); + Vec_StrPrintStr( vStr, " " ); + Vec_StrPrintStr( vStr, SC_CellPinName(pRepr, pRepr->n_inputs) ); + Vec_StrPrintStr( vStr, "=" ); + Vec_StrPrintStr( vStr, SC_CellPinOutFunc(pRepr, 0) ? SC_CellPinOutFunc(pRepr, 0) : "?" ); + Vec_StrPrintStr( vStr, ";\n" ); + SC_CellForEachPinIn( pRepr, pPin, k ) + { + float Delay = Abc_SclComputeDelayClassPin( p, pRepr, k, Slew, Gain ); + assert( Delay > 0 ); + Vec_StrPrintStr( vStr, " PIN " ); + sprintf( Buffer, "%-4s", pPin->pName ); + Vec_StrPrintStr( vStr, Buffer ); + sprintf( Buffer, " UNKNOWN 1 999 %7.2f 0.00 %7.2f 0.00\n", Delay, Delay ); + Vec_StrPrintStr( vStr, Buffer ); + } + Count++; + } + Vec_StrPrintStr( vStr, "\n.end\n" ); + Vec_StrPush( vStr, '\0' ); +// printf( "GENLIB library with %d gates is produced:\n", Count ); +// printf( "%s", Vec_StrArray(vStr) ); + if ( pnCellCount ) + *pnCellCount = Count; + return vStr; +} +void Abc_SclDumpGenlib( char * pFileName, SC_Lib * p, float Slew, float Gain, int nGatesMin ) +{ + char FileName[1000]; + int nCellCount = 0; + Vec_Str_t * vStr; + FILE * pFile; + if ( pFileName == NULL ) + sprintf( FileName, "%s_s%03d_g%03d_m%d.genlib", p->pName, (int)Slew, (int)Gain, nGatesMin ); + else + sprintf( FileName, "%s", pFileName ); + pFile = fopen( FileName, "wb" ); + if ( pFile == NULL ) + { + printf( "Cannot open file \"%s\" for writing.\n", FileName ); + return; + } + vStr = Abc_SclDeriveGenlibStr( p, Slew, Gain, nGatesMin, &nCellCount ); + fprintf( pFile, "%s", Vec_StrArray(vStr) ); + Vec_StrFree( vStr ); + fclose( pFile ); + printf( "Written GENLIB library with %d gates into file \"%s\".\n", nCellCount, FileName ); +} +void Abc_SclDeriveGenlib( void * pScl, float Slew, float Gain, int nGatesMin ) +{ + int nGateCount = 0; + Vec_Str_t * vStr = Abc_SclDeriveGenlibStr( (SC_Lib *)pScl, Slew, Gain, nGatesMin, &nGateCount ); + Vec_Str_t * vStr2 = Vec_StrDup( vStr ); + int RetValue = Mio_UpdateGenlib2( vStr, vStr2, ((SC_Lib *)pScl)->pName, 0 ); + Vec_StrFree( vStr ); + Vec_StrFree( vStr2 ); + if ( RetValue ) + printf( "Internally derived GENLIB library \"%s\" with %d gates.\n", ((SC_Lib *)pScl)->pName, nGateCount ); + else + printf( "Reading library has filed.\n" ); +} + +//////////////////////////////////////////////////////////////////////// +/// END OF FILE /// +//////////////////////////////////////////////////////////////////////// + + +ABC_NAMESPACE_IMPL_END + |