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| author | Alan Mishchenko <alanmi@berkeley.edu> | 2013-07-21 01:01:53 -0700 |
|---|---|---|
| committer | Alan Mishchenko <alanmi@berkeley.edu> | 2013-07-21 01:01:53 -0700 |
| commit | 1ed823c67d5ba9681a0d5a52aec576edc9ed2de2 (patch) | |
| tree | 1fd5e7c8de97f0219b7c6db6d10b23fe8dcbeca6 /src/map/scl/sclLoad.c | |
| parent | ab84c73eb022b145faa040575d0e507e410035de (diff) | |
| download | abc-1ed823c67d5ba9681a0d5a52aec576edc9ed2de2.tar.gz abc-1ed823c67d5ba9681a0d5a52aec576edc9ed2de2.tar.bz2 abc-1ed823c67d5ba9681a0d5a52aec576edc9ed2de2.zip | |
Adding support for input slew and output capacitance to timer and gate-sizer.
Diffstat (limited to 'src/map/scl/sclLoad.c')
| -rw-r--r-- | src/map/scl/sclLoad.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/map/scl/sclLoad.c b/src/map/scl/sclLoad.c index fc48aa82..f9768b8f 100644 --- a/src/map/scl/sclLoad.c +++ b/src/map/scl/sclLoad.c @@ -146,7 +146,8 @@ void Abc_SclComputeLoad( SC_Man * p ) Abc_NtkForEachObj( p->pNtk, pObj, i ) { SC_Pair * pLoad = Abc_SclObjLoad( p, pObj ); - pLoad->rise = pLoad->fall = 0.0; + if ( !Abc_ObjIsPo(pObj) ) + pLoad->rise = pLoad->fall = 0.0; } // add cell load Abc_NtkForEachNode1( p->pNtk, pObj, i ) @@ -160,6 +161,14 @@ void Abc_SclComputeLoad( SC_Man * p ) pLoad->fall += pPin->fall_cap; } } + // add PO load + Abc_NtkForEachPo( p->pNtk, pObj, i ) + { + SC_Pair * pLoadPo = Abc_SclObjLoad( p, pObj ); + SC_Pair * pLoad = Abc_SclObjLoad( p, Abc_ObjFanin0(pObj) ); + pLoad->rise += pLoadPo->rise; + pLoad->fall += pLoadPo->fall; + } if ( p->pWLoadUsed == NULL ) return; // add wire load |