summaryrefslogtreecommitdiffstats
path: root/src/map/scl
diff options
context:
space:
mode:
authorAlan Mishchenko <alanmi@berkeley.edu>2015-09-24 12:12:36 -0700
committerAlan Mishchenko <alanmi@berkeley.edu>2015-09-24 12:12:36 -0700
commit78951b4c6f68af1423d29f6eaf96edb24f792ac3 (patch)
treee42c6ace456ccc5585d520c8f651804c3022ce63 /src/map/scl
parent3f77172a7e619a4739bc7acb0ee41a6cd3f6d47e (diff)
downloadabc-78951b4c6f68af1423d29f6eaf96edb24f792ac3.tar.gz
abc-78951b4c6f68af1423d29f6eaf96edb24f792ac3.tar.bz2
abc-78951b4c6f68af1423d29f6eaf96edb24f792ac3.zip
Improvements to Scl_Lib/SC_Cell data-structure.
Diffstat (limited to 'src/map/scl')
-rw-r--r--src/map/scl/sclLib.h198
-rw-r--r--src/map/scl/sclLibScl.c169
-rw-r--r--src/map/scl/sclLibUtil.c60
-rw-r--r--src/map/scl/sclLoad.c6
-rw-r--r--src/map/scl/sclUtil.c6
5 files changed, 210 insertions, 229 deletions
diff --git a/src/map/scl/sclLib.h b/src/map/scl/sclLib.h
index 4dc80758..3fe36e16 100644
--- a/src/map/scl/sclLib.h
+++ b/src/map/scl/sclLib.h
@@ -119,31 +119,31 @@ struct SC_WireLoad_
char * pName;
float cap; // }- multiply estimation in 'fanout_len[].snd' with this value
float slope; // used to extrapolate wireload for large fanout count
- Vec_Int_t * vFanout; // Vec<Pair<uint,float> > -- pairs '(#fanouts, est-wire-len)'
- Vec_Flt_t * vLen;
+ Vec_Int_t vFanout; // Vec<Pair<uint,float> > -- pairs '(#fanouts, est-wire-len)'
+ Vec_Flt_t vLen;
};
struct SC_WireLoadSel_
{
char * pName;
- Vec_Flt_t * vAreaFrom; // Vec<Trip<float,float,Str> > -- triplets '(from-area, upto-area, wire-load-model)'; range is [from, upto[
- Vec_Flt_t * vAreaTo;
- Vec_Ptr_t * vWireLoadModel;
+ Vec_Flt_t vAreaFrom; // Vec<Trip<float,float,Str> > -- triplets '(from-area, upto-area, wire-load-model)'; range is [from, upto[
+ Vec_Flt_t vAreaTo;
+ Vec_Ptr_t vWireLoadModel;
};
struct SC_TableTempl_
{
char * pName;
- Vec_Ptr_t * vVars; // Vec<Str> -- name of variable (numbered from 0, not 1 as in the Liberty file)
- Vec_Ptr_t * vIndex; // Vec<Vec<float> > -- this is the point of measurement in table for the given variable
+ Vec_Ptr_t vVars; // Vec<Str> -- name of variable (numbered from 0, not 1 as in the Liberty file)
+ Vec_Ptr_t vIndex; // Vec<Vec<float> > -- this is the point of measurement in table for the given variable
};
struct SC_Surface_
{
char * pName;
- Vec_Flt_t * vIndex0; // Vec<float> -- correspondes to "index_1" in the liberty file (for timing: slew)
- Vec_Flt_t * vIndex1; // Vec<float> -- correspondes to "index_2" in the liberty file (for timing: load)
- Vec_Ptr_t * vData; // Vec<Vec<float> > -- 'data[i0][i1]' gives value at '(index0[i0], index1[i1])'
+ Vec_Flt_t vIndex0; // Vec<float> -- correspondes to "index_1" in the liberty file (for timing: slew)
+ Vec_Flt_t vIndex1; // Vec<float> -- correspondes to "index_2" in the liberty file (for timing: load)
+ Vec_Ptr_t vData; // Vec<Vec<float> > -- 'data[i0][i1]' gives value at '(index0[i0], index1[i1])'
float approx[3][6];
};
@@ -152,16 +152,16 @@ struct SC_Timing_
char * related_pin; // -- related pin
SC_TSense tsense; // -- timing sense (positive_unate, negative_unate, non_unate)
char * when_text; // -- logic condition on inputs triggering this delay model for the output (currently not used)
- SC_Surface * pCellRise; // -- Used to compute pin-to-pin delay
- SC_Surface * pCellFall;
- SC_Surface * pRiseTrans; // -- Used to compute output slew
- SC_Surface * pFallTrans;
+ SC_Surface pCellRise; // -- Used to compute pin-to-pin delay
+ SC_Surface pCellFall;
+ SC_Surface pRiseTrans; // -- Used to compute output slew
+ SC_Surface pFallTrans;
};
struct SC_Timings_
{
char * pName; // -- the 'related_pin' field
- Vec_Ptr_t * vTimings; // structures of type SC_Timing
+ Vec_Ptr_t vTimings; // structures of type SC_Timing
};
struct SC_Pin_
@@ -174,8 +174,9 @@ struct SC_Pin_
float max_out_cap; // } (not used)
float max_out_slew; // }- used only for output pins (max values must not be exceeded or else mapping is illegal) (not used)
char * func_text; // }
- Vec_Wrd_t * vFunc; // }
- Vec_Ptr_t * vRTimings; // -- for output pins
+ Vec_Wrd_t vFunc; // }
+ Vec_Ptr_t vRTimings; // -- for output pins
+// SC_Timing Timing; // -- for output pins
};
struct SC_Cell_
@@ -188,7 +189,7 @@ struct SC_Cell_
float area;
float leakage;
int drive_strength; // -- some library files provide this field (currently unused, but may be a good hint for sizing) (not used)
- Vec_Ptr_t * vPins; // NamedSet<SC_Pin>
+ Vec_Ptr_t vPins; // NamedSet<SC_Pin>
int n_inputs; // -- 'pins[0 .. n_inputs-1]' are input pins
int n_outputs; // -- 'pins[n_inputs .. n_inputs+n_outputs-1]' are output pins
SC_Cell * pNext; // same-functionality cells linked into a ring by area
@@ -209,11 +210,11 @@ struct SC_Lib_
int unit_time; // -- Valid 9..12. Unit is '10^(-val)' seconds (e.g. 9=1ns, 10=100ps, 11=10ps, 12=1ps)
float unit_cap_fst; // -- First part is a multiplier, second either 12 or 15 for 'pf' or 'ff'.
int unit_cap_snd;
- Vec_Ptr_t * vWireLoads; // NamedSet<SC_WireLoad>
- Vec_Ptr_t * vWireLoadSels; // NamedSet<SC_WireLoadSel>
- Vec_Ptr_t * vTempls; // NamedSet<SC_TableTempl>
- Vec_Ptr_t * vCells; // NamedSet<SC_Cell>
- Vec_Ptr_t * vCellClasses; // NamedSet<SC_Cell>
+ Vec_Ptr_t vWireLoads; // NamedSet<SC_WireLoad>
+ Vec_Ptr_t vWireLoadSels; // NamedSet<SC_WireLoadSel>
+ Vec_Ptr_t vTempls; // NamedSet<SC_TableTempl>
+ Vec_Ptr_t vCells; // NamedSet<SC_Cell>
+ Vec_Ptr_t vCellClasses; // NamedSet<SC_Cell>
int * pBins; // hashing gateName -> gateId
int nBins;
};
@@ -236,26 +237,26 @@ static inline void SC_PairAdd( SC_Pair * d, SC_Pair * s ) { d->rise +=
static inline int SC_PairEqual( SC_Pair * d, SC_Pair * s ) { return d->rise == s->rise && d->fall == s->fall; }
static inline int SC_PairEqualE( SC_Pair * d, SC_Pair * s, float E ) { return d->rise - s->rise < E && s->rise - d->rise < E && d->fall - s->fall < E && s->fall - d->fall < E; }
-static inline int SC_LibCellNum( SC_Lib * p ) { return Vec_PtrSize(p->vCells); }
-static inline SC_Cell * SC_LibCell( SC_Lib * p, int i ) { return (SC_Cell *)Vec_PtrEntry(p->vCells, i); }
-static inline SC_Pin * SC_CellPin( SC_Cell * p, int i ) { return (SC_Pin *)Vec_PtrEntry(p->vPins, i); }
-static inline Vec_Wrd_t * SC_CellFunc( SC_Cell * p ) { return SC_CellPin(p, p->n_inputs)->vFunc; }
+static inline int SC_LibCellNum( SC_Lib * p ) { return Vec_PtrSize(&p->vCells); }
+static inline SC_Cell * SC_LibCell( SC_Lib * p, int i ) { return (SC_Cell *)Vec_PtrEntry(&p->vCells, i); }
+static inline SC_Pin * SC_CellPin( SC_Cell * p, int i ) { return (SC_Pin *)Vec_PtrEntry(&p->vPins, i); }
+static inline Vec_Wrd_t * SC_CellFunc( SC_Cell * p ) { return &SC_CellPin(p, p->n_inputs)->vFunc; }
static inline float SC_CellPinCap( SC_Cell * p, int i ) { return 0.5 * SC_CellPin(p, i)->rise_cap + 0.5 * SC_CellPin(p, i)->fall_cap; }
static inline float SC_CellPinCapAve( SC_Cell * p ) { int i; float c = 0; for (i = 0; i < p->n_inputs; i++) c += SC_CellPinCap(p, i); return c / Abc_MaxInt(1, p->n_inputs); }
static inline char * SC_CellPinOutFunc( SC_Cell * p, int i ) { return SC_CellPin(p, p->n_inputs + i)->func_text; }
static inline char * SC_CellPinName( SC_Cell * p, int i ) { return SC_CellPin(p, i)->pName; }
-#define SC_LibForEachCell( p, pCell, i ) Vec_PtrForEachEntry( SC_Cell *, p->vCells, pCell, i )
-#define SC_LibForEachCellClass( p, pCell, i ) Vec_PtrForEachEntry( SC_Cell *, p->vCellClasses, pCell, i )
-#define SC_LibForEachWireLoad( p, pWL, i ) Vec_PtrForEachEntry( SC_WireLoad *, p->vWireLoads, pWL, i )
-#define SC_LibForEachWireLoadSel( p, pWLS, i ) Vec_PtrForEachEntry( SC_WireLoadSel *, p->vWireLoadSels, pWLS, i )
-#define SC_LibForEachTempl( p, pTempl, i ) Vec_PtrForEachEntry( SC_TableTempl *, p->vTempls, pTempl, i )
-#define SC_CellForEachPin( p, pPin, i ) Vec_PtrForEachEntry( SC_Pin *, p->vPins, pPin, i )
-#define SC_CellForEachPinIn( p, pPin, i ) Vec_PtrForEachEntryStop( SC_Pin *, p->vPins, pPin, i, p->n_inputs )
-#define SC_CellForEachPinOut( p, pPin, i ) Vec_PtrForEachEntryStart( SC_Pin *, p->vPins, pPin, i, p->n_inputs )
+#define SC_LibForEachCell( p, pCell, i ) Vec_PtrForEachEntry( SC_Cell *, &p->vCells, pCell, i )
+#define SC_LibForEachCellClass( p, pCell, i ) Vec_PtrForEachEntry( SC_Cell *, &p->vCellClasses, pCell, i )
+#define SC_LibForEachWireLoad( p, pWL, i ) Vec_PtrForEachEntry( SC_WireLoad *, &p->vWireLoads, pWL, i )
+#define SC_LibForEachWireLoadSel( p, pWLS, i ) Vec_PtrForEachEntry( SC_WireLoadSel *, &p->vWireLoadSels, pWLS, i )
+#define SC_LibForEachTempl( p, pTempl, i ) Vec_PtrForEachEntry( SC_TableTempl *, &p->vTempls, pTempl, i )
+#define SC_CellForEachPin( p, pPin, i ) Vec_PtrForEachEntry( SC_Pin *, &p->vPins, pPin, i )
+#define SC_CellForEachPinIn( p, pPin, i ) Vec_PtrForEachEntryStop( SC_Pin *, &p->vPins, pPin, i, p->n_inputs )
+#define SC_CellForEachPinOut( p, pPin, i ) Vec_PtrForEachEntryStart( SC_Pin *, &p->vPins, pPin, i, p->n_inputs )
#define SC_RingForEachCell( pRing, pCell, i ) for ( i = 0, pCell = pRing; i == 0 || pCell != pRing; pCell = pCell->pNext, i++ )
#define SC_RingForEachCellRev( pRing, pCell, i ) for ( i = 0, pCell = pRing; i == 0 || pCell != pRing; pCell = pCell->pPrev, i++ )
-#define SC_PinForEachRTiming( p, pRTime, i ) Vec_PtrForEachEntry( SC_Timings *, p->vRTimings, pRTime, i )
+#define SC_PinForEachRTiming( p, pRTime, i ) Vec_PtrForEachEntry( SC_Timings *, &p->vRTimings, pRTime, i )
////////////////////////////////////////////////////////////////////////
@@ -277,51 +278,36 @@ static inline SC_WireLoad * Abc_SclWireLoadAlloc()
{
SC_WireLoad * p;
p = ABC_CALLOC( SC_WireLoad, 1 );
- p->vFanout = Vec_IntAlloc( 0 );
- p->vLen = Vec_FltAlloc( 0 );
return p;
}
static inline SC_WireLoadSel * Abc_SclWireLoadSelAlloc()
{
SC_WireLoadSel * p;
p = ABC_CALLOC( SC_WireLoadSel, 1 );
- p->vAreaFrom = Vec_FltAlloc( 0 );
- p->vAreaTo = Vec_FltAlloc( 0 );
- p->vWireLoadModel = Vec_PtrAlloc( 0 );
return p;
}
static inline SC_TableTempl * Abc_SclTableTemplAlloc()
{
SC_TableTempl * p;
p = ABC_CALLOC( SC_TableTempl, 1 );
- p->vVars = Vec_PtrAlloc( 0 );
- p->vIndex = Vec_PtrAlloc( 0 );
return p;
}
static inline SC_Surface * Abc_SclSurfaceAlloc()
{
SC_Surface * p;
p = ABC_CALLOC( SC_Surface, 1 );
- p->vIndex0 = Vec_FltAlloc( 0 );
- p->vIndex1 = Vec_FltAlloc( 0 );
- p->vData = Vec_PtrAlloc( 0 );
return p;
}
static inline SC_Timing * Abc_SclTimingAlloc()
{
SC_Timing * p;
p = ABC_CALLOC( SC_Timing, 1 );
- p->pCellRise = Abc_SclSurfaceAlloc();
- p->pCellFall = Abc_SclSurfaceAlloc();
- p->pRiseTrans = Abc_SclSurfaceAlloc();
- p->pFallTrans = Abc_SclSurfaceAlloc();
return p;
}
static inline SC_Timings * Abc_SclTimingsAlloc()
{
SC_Timings * p;
p = ABC_CALLOC( SC_Timings, 1 );
- p->vTimings = Vec_PtrAlloc( 0 );
return p;
}
static inline SC_Pin * Abc_SclPinAlloc()
@@ -329,15 +315,12 @@ static inline SC_Pin * Abc_SclPinAlloc()
SC_Pin * p;
p = ABC_CALLOC( SC_Pin, 1 );
p->max_out_slew = -1;
- p->vFunc = Vec_WrdAlloc( 0 );
- p->vRTimings = Vec_PtrAlloc( 0 );
return p;
}
static inline SC_Cell * Abc_SclCellAlloc()
{
SC_Cell * p;
p = ABC_CALLOC( SC_Cell, 1 );
- p->vPins = Vec_PtrAlloc( 0 );
return p;
}
static inline SC_Lib * Abc_SclLibAlloc()
@@ -348,11 +331,6 @@ static inline SC_Lib * Abc_SclLibAlloc()
p->unit_time = 9;
p->unit_cap_fst = 1;
p->unit_cap_snd = 12;
- p->vWireLoads = Vec_PtrAlloc( 0 );
- p->vWireLoadSels = Vec_PtrAlloc( 0 );
- p->vTempls = Vec_PtrAlloc( 0 );
- p->vCells = Vec_PtrAlloc( 0 );
- p->vCellClasses = Vec_PtrAlloc( 0 );
return p;
}
@@ -370,40 +348,40 @@ static inline SC_Lib * Abc_SclLibAlloc()
***********************************************************************/
static inline void Abc_SclWireLoadFree( SC_WireLoad * p )
{
- Vec_IntFree( p->vFanout );
- Vec_FltFree( p->vLen );
+ Vec_IntErase( &p->vFanout );
+ Vec_FltErase( &p->vLen );
ABC_FREE( p->pName );
ABC_FREE( p );
}
static inline void Abc_SclWireLoadSelFree( SC_WireLoadSel * p )
{
- Vec_FltFree( p->vAreaFrom );
- Vec_FltFree( p->vAreaTo );
- Vec_PtrFreeFree( p->vWireLoadModel );
+ Vec_FltErase( &p->vAreaFrom );
+ Vec_FltErase( &p->vAreaTo );
+ Vec_PtrFreeData( &p->vWireLoadModel );
ABC_FREE( p->pName );
ABC_FREE( p );
}
static inline void Abc_SclTableTemplFree( SC_TableTempl * p )
{
- Vec_PtrFreeFree( p->vVars );
- Vec_VecFree( (Vec_Vec_t *)p->vIndex );
+ Vec_PtrFreeData( &p->vVars );
+ Vec_VecErase( (Vec_Vec_t *)&p->vIndex );
ABC_FREE( p->pName );
ABC_FREE( p );
}
static inline void Abc_SclSurfaceFree( SC_Surface * p )
{
- Vec_FltFree( p->vIndex0 );
- Vec_FltFree( p->vIndex1 );
- Vec_VecFree( (Vec_Vec_t *)p->vData );
+ Vec_FltErase( &p->vIndex0 );
+ Vec_FltErase( &p->vIndex1 );
+ Vec_VecErase( (Vec_Vec_t *)&p->vData );
ABC_FREE( p->pName );
- ABC_FREE( p );
+// ABC_FREE( p );
}
static inline void Abc_SclTimingFree( SC_Timing * p )
{
- Abc_SclSurfaceFree( p->pCellRise );
- Abc_SclSurfaceFree( p->pCellFall );
- Abc_SclSurfaceFree( p->pRiseTrans );
- Abc_SclSurfaceFree( p->pFallTrans );
+ Abc_SclSurfaceFree( &p->pCellRise );
+ Abc_SclSurfaceFree( &p->pCellFall );
+ Abc_SclSurfaceFree( &p->pRiseTrans );
+ Abc_SclSurfaceFree( &p->pFallTrans );
ABC_FREE( p->related_pin );
ABC_FREE( p->when_text );
ABC_FREE( p );
@@ -412,9 +390,9 @@ static inline void Abc_SclTimingsFree( SC_Timings * p )
{
SC_Timing * pTemp;
int i;
- Vec_PtrForEachEntry( SC_Timing *, p->vTimings, pTemp, i )
+ Vec_PtrForEachEntry( SC_Timing *, &p->vTimings, pTemp, i )
Abc_SclTimingFree( pTemp );
- Vec_PtrFree( p->vTimings );
+ Vec_PtrErase( &p->vTimings );
ABC_FREE( p->pName );
ABC_FREE( p );
}
@@ -424,8 +402,8 @@ static inline void Abc_SclPinFree( SC_Pin * p )
int i;
SC_PinForEachRTiming( p, pTemp, i )
Abc_SclTimingsFree( pTemp );
- Vec_PtrFree( p->vRTimings );
- Vec_WrdFree( p->vFunc );
+ Vec_PtrErase( &p->vRTimings );
+ Vec_WrdErase( &p->vFunc );
ABC_FREE( p->func_text );
ABC_FREE( p->pName );
ABC_FREE( p );
@@ -436,7 +414,7 @@ static inline void Abc_SclCellFree( SC_Cell * p )
int i;
SC_CellForEachPin( p, pTemp, i )
Abc_SclPinFree( pTemp );
- Vec_PtrFree( p->vPins );
+ Vec_PtrErase( &p->vPins );
ABC_FREE( p->pName );
ABC_FREE( p );
}
@@ -449,17 +427,17 @@ static inline void Abc_SclLibFree( SC_Lib * p )
int i;
SC_LibForEachWireLoad( p, pWL, i )
Abc_SclWireLoadFree( pWL );
- Vec_PtrFree( p->vWireLoads );
+ Vec_PtrErase( &p->vWireLoads );
SC_LibForEachWireLoadSel( p, pWLS, i )
Abc_SclWireLoadSelFree( pWLS );
- Vec_PtrFree( p->vWireLoadSels );
+ Vec_PtrErase( &p->vWireLoadSels );
SC_LibForEachTempl( p, pTempl, i )
Abc_SclTableTemplFree( pTempl );
- Vec_PtrFree( p->vTempls );
+ Vec_PtrErase( &p->vTempls );
SC_LibForEachCell( p, pCell, i )
Abc_SclCellFree( pCell );
- Vec_PtrFree( p->vCells );
- Vec_PtrFree( p->vCellClasses );
+ Vec_PtrErase( &p->vCells );
+ Vec_PtrErase( &p->vCellClasses );
ABC_FREE( p->pName );
ABC_FREE( p->pFileName );
ABC_FREE( p->default_wire_load );
@@ -487,23 +465,23 @@ static inline float Scl_LibLookup( SC_Surface * p, float slew, float load )
int s, l;
// handle constant table
- if ( Vec_FltSize(p->vIndex0) == 1 && Vec_FltSize(p->vIndex1) == 1 )
+ if ( Vec_FltSize(&p->vIndex0) == 1 && Vec_FltSize(&p->vIndex1) == 1 )
{
- Vec_Flt_t * vTemp = (Vec_Flt_t *)Vec_PtrEntry(p->vData, 0);
- assert( Vec_PtrSize(p->vData) == 1 );
+ Vec_Flt_t * vTemp = (Vec_Flt_t *)Vec_PtrEntry(&p->vData, 0);
+ assert( Vec_PtrSize(&p->vData) == 1 );
assert( Vec_FltSize(vTemp) == 1 );
return Vec_FltEntry(vTemp, 0);
}
// Find closest sample points in surface:
- pIndex0 = Vec_FltArray(p->vIndex0);
- for ( s = 1; s < Vec_FltSize(p->vIndex0)-1; s++ )
+ pIndex0 = Vec_FltArray(&p->vIndex0);
+ for ( s = 1; s < Vec_FltSize(&p->vIndex0)-1; s++ )
if ( pIndex0[s] > slew )
break;
s--;
- pIndex1 = Vec_FltArray(p->vIndex1);
- for ( l = 1; l < Vec_FltSize(p->vIndex1)-1; l++ )
+ pIndex1 = Vec_FltArray(&p->vIndex1);
+ for ( l = 1; l < Vec_FltSize(&p->vIndex1)-1; l++ )
if ( pIndex1[l] > load )
break;
l--;
@@ -512,8 +490,8 @@ static inline float Scl_LibLookup( SC_Surface * p, float slew, float load )
sfrac = (slew - pIndex0[s]) / (pIndex0[s+1] - pIndex0[s]);
lfrac = (load - pIndex1[l]) / (pIndex1[l+1] - pIndex1[l]);
- pDataS = Vec_FltArray( (Vec_Flt_t *)Vec_PtrEntry(p->vData, s) );
- pDataS1 = Vec_FltArray( (Vec_Flt_t *)Vec_PtrEntry(p->vData, s+1) );
+ pDataS = Vec_FltArray( (Vec_Flt_t *)Vec_PtrEntry(&p->vData, s) );
+ pDataS1 = Vec_FltArray( (Vec_Flt_t *)Vec_PtrEntry(&p->vData, s+1) );
p0 = pDataS [l] + lfrac * (pDataS [l+1] - pDataS [l]);
p1 = pDataS1[l] + lfrac * (pDataS1[l+1] - pDataS1[l]);
@@ -524,30 +502,30 @@ static inline void Scl_LibPinArrival( SC_Timing * pTime, SC_Pair * pArrIn, SC_Pa
{
if (pTime->tsense == sc_ts_Pos || pTime->tsense == sc_ts_Non)
{
- pArrOut->rise = Abc_MaxFloat( pArrOut->rise, pArrIn->rise + Scl_LibLookup(pTime->pCellRise, pSlewIn->rise, pLoad->rise) );
- pArrOut->fall = Abc_MaxFloat( pArrOut->fall, pArrIn->fall + Scl_LibLookup(pTime->pCellFall, pSlewIn->fall, pLoad->fall) );
- pSlewOut->rise = Abc_MaxFloat( pSlewOut->rise, Scl_LibLookup(pTime->pRiseTrans, pSlewIn->rise, pLoad->rise) );
- pSlewOut->fall = Abc_MaxFloat( pSlewOut->fall, Scl_LibLookup(pTime->pFallTrans, pSlewIn->fall, pLoad->fall) );
+ pArrOut->rise = Abc_MaxFloat( pArrOut->rise, pArrIn->rise + Scl_LibLookup(&pTime->pCellRise, pSlewIn->rise, pLoad->rise) );
+ pArrOut->fall = Abc_MaxFloat( pArrOut->fall, pArrIn->fall + Scl_LibLookup(&pTime->pCellFall, pSlewIn->fall, pLoad->fall) );
+ pSlewOut->rise = Abc_MaxFloat( pSlewOut->rise, Scl_LibLookup(&pTime->pRiseTrans, pSlewIn->rise, pLoad->rise) );
+ pSlewOut->fall = Abc_MaxFloat( pSlewOut->fall, Scl_LibLookup(&pTime->pFallTrans, pSlewIn->fall, pLoad->fall) );
}
if (pTime->tsense == sc_ts_Neg || pTime->tsense == sc_ts_Non)
{
- pArrOut->rise = Abc_MaxFloat( pArrOut->rise, pArrIn->fall + Scl_LibLookup(pTime->pCellRise, pSlewIn->fall, pLoad->rise) );
- pArrOut->fall = Abc_MaxFloat( pArrOut->fall, pArrIn->rise + Scl_LibLookup(pTime->pCellFall, pSlewIn->rise, pLoad->fall) );
- pSlewOut->rise = Abc_MaxFloat( pSlewOut->rise, Scl_LibLookup(pTime->pRiseTrans, pSlewIn->fall, pLoad->rise) );
- pSlewOut->fall = Abc_MaxFloat( pSlewOut->fall, Scl_LibLookup(pTime->pFallTrans, pSlewIn->rise, pLoad->fall) );
+ pArrOut->rise = Abc_MaxFloat( pArrOut->rise, pArrIn->fall + Scl_LibLookup(&pTime->pCellRise, pSlewIn->fall, pLoad->rise) );
+ pArrOut->fall = Abc_MaxFloat( pArrOut->fall, pArrIn->rise + Scl_LibLookup(&pTime->pCellFall, pSlewIn->rise, pLoad->fall) );
+ pSlewOut->rise = Abc_MaxFloat( pSlewOut->rise, Scl_LibLookup(&pTime->pRiseTrans, pSlewIn->fall, pLoad->rise) );
+ pSlewOut->fall = Abc_MaxFloat( pSlewOut->fall, Scl_LibLookup(&pTime->pFallTrans, pSlewIn->rise, pLoad->fall) );
}
}
static inline void Scl_LibPinDeparture( SC_Timing * pTime, SC_Pair * pDepIn, SC_Pair * pSlewIn, SC_Pair * pLoad, SC_Pair * pDepOut )
{
if (pTime->tsense == sc_ts_Pos || pTime->tsense == sc_ts_Non)
{
- pDepIn->rise = Abc_MaxFloat( pDepIn->rise, pDepOut->rise + Scl_LibLookup(pTime->pCellRise, pSlewIn->rise, pLoad->rise) );
- pDepIn->fall = Abc_MaxFloat( pDepIn->fall, pDepOut->fall + Scl_LibLookup(pTime->pCellFall, pSlewIn->fall, pLoad->fall) );
+ pDepIn->rise = Abc_MaxFloat( pDepIn->rise, pDepOut->rise + Scl_LibLookup(&pTime->pCellRise, pSlewIn->rise, pLoad->rise) );
+ pDepIn->fall = Abc_MaxFloat( pDepIn->fall, pDepOut->fall + Scl_LibLookup(&pTime->pCellFall, pSlewIn->fall, pLoad->fall) );
}
if (pTime->tsense == sc_ts_Neg || pTime->tsense == sc_ts_Non)
{
- pDepIn->fall = Abc_MaxFloat( pDepIn->fall, pDepOut->rise + Scl_LibLookup(pTime->pCellRise, pSlewIn->fall, pLoad->rise) );
- pDepIn->rise = Abc_MaxFloat( pDepIn->rise, pDepOut->fall + Scl_LibLookup(pTime->pCellFall, pSlewIn->rise, pLoad->fall) );
+ pDepIn->fall = Abc_MaxFloat( pDepIn->fall, pDepOut->rise + Scl_LibLookup(&pTime->pCellRise, pSlewIn->fall, pLoad->rise) );
+ pDepIn->rise = Abc_MaxFloat( pDepIn->rise, pDepOut->fall + Scl_LibLookup(&pTime->pCellFall, pSlewIn->rise, pLoad->fall) );
}
}
@@ -568,12 +546,12 @@ static inline SC_Timing * Scl_CellPinTime( SC_Cell * pCell, int iPin )
SC_Timings * pRTime;
assert( iPin >= 0 && iPin < pCell->n_inputs );
pPin = SC_CellPin( pCell, pCell->n_inputs );
- assert( Vec_PtrSize(pPin->vRTimings) == pCell->n_inputs );
- pRTime = (SC_Timings *)Vec_PtrEntry( pPin->vRTimings, iPin );
- if ( Vec_PtrSize(pRTime->vTimings) == 0 )
+ assert( Vec_PtrSize(&pPin->vRTimings) == pCell->n_inputs );
+ pRTime = (SC_Timings *)Vec_PtrEntry( &pPin->vRTimings, iPin );
+ if ( Vec_PtrSize(&pRTime->vTimings) == 0 )
return NULL;
- assert( Vec_PtrSize(pRTime->vTimings) == 1 );
- return (SC_Timing *)Vec_PtrEntry( pRTime->vTimings, 0 );
+ assert( Vec_PtrSize(&pRTime->vTimings) == 1 );
+ return (SC_Timing *)Vec_PtrEntry( &pRTime->vTimings, 0 );
}
static inline float Scl_LibPinArrivalEstimate( SC_Cell * pCell, int iPin, float Slew, float Load )
{
diff --git a/src/map/scl/sclLibScl.c b/src/map/scl/sclLibScl.c
index 2e4e1deb..d9b14273 100644
--- a/src/map/scl/sclLibScl.c
+++ b/src/map/scl/sclLibScl.c
@@ -52,16 +52,16 @@ static void Abc_SclReadSurface( Vec_Str_t * vOut, int * pPos, SC_Surface * p )
int i, j;
for ( i = Vec_StrGetI(vOut, pPos); i != 0; i-- )
- Vec_FltPush( p->vIndex0, Vec_StrGetF(vOut, pPos) );
+ Vec_FltPush( &p->vIndex0, Vec_StrGetF(vOut, pPos) );
for ( i = Vec_StrGetI(vOut, pPos); i != 0; i-- )
- Vec_FltPush( p->vIndex1, Vec_StrGetF(vOut, pPos) );
+ Vec_FltPush( &p->vIndex1, Vec_StrGetF(vOut, pPos) );
- for ( i = 0; i < Vec_FltSize(p->vIndex0); i++ )
+ for ( i = 0; i < Vec_FltSize(&p->vIndex0); i++ )
{
- vVec = Vec_FltAlloc( Vec_FltSize(p->vIndex1) );
- Vec_PtrPush( p->vData, vVec );
- for ( j = 0; j < Vec_FltSize(p->vIndex1); j++ )
+ vVec = Vec_FltAlloc( Vec_FltSize(&p->vIndex1) );
+ Vec_PtrPush( &p->vData, vVec );
+ for ( j = 0; j < Vec_FltSize(&p->vIndex1); j++ )
Vec_FltPush( vVec, Vec_StrGetF(vOut, pPos) );
}
@@ -97,7 +97,7 @@ static int Abc_SclReadLibrary( Vec_Str_t * vOut, int * pPos, SC_Lib * p )
for ( i = Vec_StrGetI(vOut, pPos); i != 0; i-- )
{
SC_WireLoad * pWL = Abc_SclWireLoadAlloc();
- Vec_PtrPush( p->vWireLoads, pWL );
+ Vec_PtrPush( &p->vWireLoads, pWL );
pWL->pName = Vec_StrGetS(vOut, pPos);
pWL->cap = Vec_StrGetF(vOut, pPos);
@@ -105,8 +105,8 @@ static int Abc_SclReadLibrary( Vec_Str_t * vOut, int * pPos, SC_Lib * p )
for ( j = Vec_StrGetI(vOut, pPos); j != 0; j-- )
{
- Vec_IntPush( pWL->vFanout, Vec_StrGetI(vOut, pPos) );
- Vec_FltPush( pWL->vLen, Vec_StrGetF(vOut, pPos) );
+ Vec_IntPush( &pWL->vFanout, Vec_StrGetI(vOut, pPos) );
+ Vec_FltPush( &pWL->vLen, Vec_StrGetF(vOut, pPos) );
}
}
@@ -114,14 +114,14 @@ static int Abc_SclReadLibrary( Vec_Str_t * vOut, int * pPos, SC_Lib * p )
for ( i = Vec_StrGetI(vOut, pPos); i != 0; i-- )
{
SC_WireLoadSel * pWLS = Abc_SclWireLoadSelAlloc();
- Vec_PtrPush( p->vWireLoadSels, pWLS );
+ Vec_PtrPush( &p->vWireLoadSels, pWLS );
pWLS->pName = Vec_StrGetS(vOut, pPos);
for ( j = Vec_StrGetI(vOut, pPos); j != 0; j-- )
{
- Vec_FltPush( pWLS->vAreaFrom, Vec_StrGetF(vOut, pPos) );
- Vec_FltPush( pWLS->vAreaTo, Vec_StrGetF(vOut, pPos) );
- Vec_PtrPush( pWLS->vWireLoadModel, Vec_StrGetS(vOut, pPos) );
+ Vec_FltPush( &pWLS->vAreaFrom, Vec_StrGetF(vOut, pPos) );
+ Vec_FltPush( &pWLS->vAreaTo, Vec_StrGetF(vOut, pPos) );
+ Vec_PtrPush( &pWLS->vWireLoadModel, Vec_StrGetS(vOut, pPos) );
}
}
@@ -129,9 +129,9 @@ static int Abc_SclReadLibrary( Vec_Str_t * vOut, int * pPos, SC_Lib * p )
{
SC_Cell * pCell = Abc_SclCellAlloc();
pCell->Id = SC_LibCellNum(p);
- Vec_PtrPush( p->vCells, pCell );
+ Vec_PtrPush( &p->vCells, pCell );
- pCell->pName = Vec_StrGetS(vOut, pPos);
+ pCell->pName = Vec_StrGetS(vOut, pPos);
pCell->area = Vec_StrGetF(vOut, pPos);
pCell->leakage = Vec_StrGetF(vOut, pPos);
pCell->drive_strength = Vec_StrGetI(vOut, pPos);
@@ -148,7 +148,7 @@ static int Abc_SclReadLibrary( Vec_Str_t * vOut, int * pPos, SC_Lib * p )
for ( j = 0; j < pCell->n_inputs; j++ )
{
SC_Pin * pPin = Abc_SclPinAlloc();
- Vec_PtrPush( pCell->vPins, pPin );
+ Vec_PtrPush( &pCell->vPins, pPin );
pPin->dir = sc_dir_Input;
pPin->pName = Vec_StrGetS(vOut, pPos);
@@ -159,7 +159,7 @@ static int Abc_SclReadLibrary( Vec_Str_t * vOut, int * pPos, SC_Lib * p )
for ( j = 0; j < pCell->n_outputs; j++ )
{
SC_Pin * pPin = Abc_SclPinAlloc();
- Vec_PtrPush( pCell->vPins, pPin );
+ Vec_PtrPush( &pCell->vPins, pPin );
pPin->dir = sc_dir_Output;
pPin->pName = Vec_StrGetS(vOut, pPos);
@@ -178,31 +178,34 @@ static int Abc_SclReadLibrary( Vec_Str_t * vOut, int * pPos, SC_Lib * p )
{
// formula is not given - read truth table
ABC_FREE( pPin->func_text );
- assert( Vec_WrdSize(pPin->vFunc) == 0 );
- Vec_WrdGrow( pPin->vFunc, Abc_Truth6WordNum(pCell->n_inputs) );
- for ( k = 0; k < Vec_WrdCap(pPin->vFunc); k++ )
- Vec_WrdPush( pPin->vFunc, Vec_StrGetW(vOut, pPos) );
+ assert( Vec_WrdSize(&pPin->vFunc) == 0 );
+ Vec_WrdGrow( &pPin->vFunc, Abc_Truth6WordNum(pCell->n_inputs) );
+ for ( k = 0; k < Vec_WrdCap(&pPin->vFunc); k++ )
+ Vec_WrdPush( &pPin->vFunc, Vec_StrGetW(vOut, pPos) );
}
else
{
// formula is given - derive truth table
SC_Pin * pPin2;
Vec_Ptr_t * vNames;
+ Vec_Wrd_t * vFunc;
// collect input names
vNames = Vec_PtrAlloc( pCell->n_inputs );
SC_CellForEachPinIn( pCell, pPin2, n )
Vec_PtrPush( vNames, pPin2->pName );
// derive truth table
- assert( Vec_WrdSize(pPin->vFunc) == 0 );
- Vec_WrdFree( pPin->vFunc );
- pPin->vFunc = Mio_ParseFormulaTruth( pPin->func_text, (char **)Vec_PtrArray(vNames), pCell->n_inputs );
+ assert( Vec_WrdSize(&pPin->vFunc) == 0 );
+ Vec_WrdErase( &pPin->vFunc );
+ vFunc = Mio_ParseFormulaTruth( pPin->func_text, (char **)Vec_PtrArray(vNames), pCell->n_inputs );
+ pPin->vFunc = *vFunc;
+ ABC_FREE( vFunc );
Vec_PtrFree( vNames );
// skip truth table
- assert( Vec_WrdSize(pPin->vFunc) == Abc_Truth6WordNum(pCell->n_inputs) );
- for ( k = 0; k < Vec_WrdSize(pPin->vFunc); k++ )
+ assert( Vec_WrdSize(&pPin->vFunc) == Abc_Truth6WordNum(pCell->n_inputs) );
+ for ( k = 0; k < Vec_WrdSize(&pPin->vFunc); k++ )
{
word Value = Vec_StrGetW(vOut, pPos);
- assert( Value == Vec_WrdEntry(pPin->vFunc, k) );
+ assert( Value == Vec_WrdEntry(&pPin->vFunc, k) );
}
}
@@ -210,23 +213,23 @@ static int Abc_SclReadLibrary( Vec_Str_t * vOut, int * pPos, SC_Lib * p )
for ( k = 0; k < pCell->n_inputs; k++ )
{
SC_Timings * pRTime = Abc_SclTimingsAlloc();
- Vec_PtrPush( pPin->vRTimings, pRTime );
+ Vec_PtrPush( &pPin->vRTimings, pRTime );
pRTime->pName = Vec_StrGetS(vOut, pPos);
n = Vec_StrGetI(vOut, pPos); assert( n <= 1 );
if ( n == 1 )
{
SC_Timing * pTime = Abc_SclTimingAlloc();
- Vec_PtrPush( pRTime->vTimings, pTime );
+ Vec_PtrPush( &pRTime->vTimings, pTime );
pTime->tsense = (SC_TSense)Vec_StrGetI(vOut, pPos);
- Abc_SclReadSurface( vOut, pPos, pTime->pCellRise );
- Abc_SclReadSurface( vOut, pPos, pTime->pCellFall );
- Abc_SclReadSurface( vOut, pPos, pTime->pRiseTrans );
- Abc_SclReadSurface( vOut, pPos, pTime->pFallTrans );
+ Abc_SclReadSurface( vOut, pPos, &pTime->pCellRise );
+ Abc_SclReadSurface( vOut, pPos, &pTime->pCellFall );
+ Abc_SclReadSurface( vOut, pPos, &pTime->pRiseTrans );
+ Abc_SclReadSurface( vOut, pPos, &pTime->pFallTrans );
}
else
- assert( Vec_PtrSize(pRTime->vTimings) == 0 );
+ assert( Vec_PtrSize(&pRTime->vTimings) == 0 );
}
}
}
@@ -296,15 +299,15 @@ static void Abc_SclWriteSurface( Vec_Str_t * vOut, SC_Surface * p )
float Entry;
int i, k;
- Vec_StrPutI( vOut, Vec_FltSize(p->vIndex0) );
- Vec_FltForEachEntry( p->vIndex0, Entry, i )
+ Vec_StrPutI( vOut, Vec_FltSize(&p->vIndex0) );
+ Vec_FltForEachEntry( &p->vIndex0, Entry, i )
Vec_StrPutF( vOut, Entry );
- Vec_StrPutI( vOut, Vec_FltSize(p->vIndex1) );
- Vec_FltForEachEntry( p->vIndex1, Entry, i )
+ Vec_StrPutI( vOut, Vec_FltSize(&p->vIndex1) );
+ Vec_FltForEachEntry( &p->vIndex1, Entry, i )
Vec_StrPutF( vOut, Entry );
- Vec_PtrForEachEntry( Vec_Flt_t *, p->vData, vVec, i )
+ Vec_PtrForEachEntry( Vec_Flt_t *, &p->vData, vVec, i )
Vec_FltForEachEntry( vVec, Entry, k )
Vec_StrPutF( vOut, Entry );
@@ -339,32 +342,32 @@ static void Abc_SclWriteLibrary( Vec_Str_t * vOut, SC_Lib * p )
Vec_StrPutI( vOut, p->unit_cap_snd );
// Write 'wire_load' vector:
- Vec_StrPutI( vOut, Vec_PtrSize(p->vWireLoads) );
+ Vec_StrPutI( vOut, Vec_PtrSize(&p->vWireLoads) );
SC_LibForEachWireLoad( p, pWL, i )
{
Vec_StrPutS( vOut, pWL->pName );
Vec_StrPutF( vOut, pWL->cap );
Vec_StrPutF( vOut, pWL->slope );
- Vec_StrPutI( vOut, Vec_IntSize(pWL->vFanout) );
- for ( j = 0; j < Vec_IntSize(pWL->vFanout); j++ )
+ Vec_StrPutI( vOut, Vec_IntSize(&pWL->vFanout) );
+ for ( j = 0; j < Vec_IntSize(&pWL->vFanout); j++ )
{
- Vec_StrPutI( vOut, Vec_IntEntry(pWL->vFanout, j) );
- Vec_StrPutF( vOut, Vec_FltEntry(pWL->vLen, j) );
+ Vec_StrPutI( vOut, Vec_IntEntry(&pWL->vFanout, j) );
+ Vec_StrPutF( vOut, Vec_FltEntry(&pWL->vLen, j) );
}
}
// Write 'wire_load_sel' vector:
- Vec_StrPutI( vOut, Vec_PtrSize(p->vWireLoadSels) );
+ Vec_StrPutI( vOut, Vec_PtrSize(&p->vWireLoadSels) );
SC_LibForEachWireLoadSel( p, pWLS, i )
{
Vec_StrPutS( vOut, pWLS->pName );
- Vec_StrPutI( vOut, Vec_FltSize(pWLS->vAreaFrom) );
- for ( j = 0; j < Vec_FltSize(pWLS->vAreaFrom); j++)
+ Vec_StrPutI( vOut, Vec_FltSize(&pWLS->vAreaFrom) );
+ for ( j = 0; j < Vec_FltSize(&pWLS->vAreaFrom); j++)
{
- Vec_StrPutF( vOut, Vec_FltEntry(pWLS->vAreaFrom, j) );
- Vec_StrPutF( vOut, Vec_FltEntry(pWLS->vAreaTo, j) );
- Vec_StrPutS( vOut, (char *)Vec_PtrEntry(pWLS->vWireLoadModel, j) );
+ Vec_StrPutF( vOut, Vec_FltEntry(&pWLS->vAreaFrom, j) );
+ Vec_StrPutF( vOut, Vec_FltEntry(&pWLS->vAreaTo, j) );
+ Vec_StrPutS( vOut, (char *)Vec_PtrEntry(&pWLS->vWireLoadModel, j) );
}
}
@@ -412,32 +415,32 @@ static void Abc_SclWriteLibrary( Vec_Str_t * vOut, SC_Lib * p )
Vec_StrPutS( vOut, pPin->func_text ? pPin->func_text : (char *)"" );
// write truth table
- assert( Vec_WrdSize(pPin->vFunc) == Abc_Truth6WordNum(pCell->n_inputs) );
- Vec_WrdForEachEntry( pPin->vFunc, uWord, k ) // -- 'size = 1u << (n_vars - 6)'
+ assert( Vec_WrdSize(&pPin->vFunc) == Abc_Truth6WordNum(pCell->n_inputs) );
+ Vec_WrdForEachEntry( &pPin->vFunc, uWord, k ) // -- 'size = 1u << (n_vars - 6)'
Vec_StrPutW( vOut, uWord ); // -- 64-bit number, written uncompressed (low-byte first)
// Write 'rtiming': (pin-to-pin timing tables for this particular output)
- assert( Vec_PtrSize(pPin->vRTimings) == pCell->n_inputs );
+ assert( Vec_PtrSize(&pPin->vRTimings) == pCell->n_inputs );
SC_PinForEachRTiming( pPin, pRTime, k )
{
Vec_StrPutS( vOut, pRTime->pName );
- Vec_StrPutI( vOut, Vec_PtrSize(pRTime->vTimings) );
+ Vec_StrPutI( vOut, Vec_PtrSize(&pRTime->vTimings) );
// -- NOTE! After post-processing, the size of the 'rtiming[k]' vector is either
// 0 or 1 (in static timing, we have merged all tables to get the worst case).
// The case with size 0 should only occur for multi-output gates.
- if ( Vec_PtrSize(pRTime->vTimings) == 1 )
+ if ( Vec_PtrSize(&pRTime->vTimings) == 1 )
{
- SC_Timing * pTime = (SC_Timing *)Vec_PtrEntry( pRTime->vTimings, 0 );
+ SC_Timing * pTime = (SC_Timing *)Vec_PtrEntry( &pRTime->vTimings, 0 );
// -- NOTE! We don't need to save 'related_pin' string because we have sorted
// the elements on input pins.
Vec_StrPutI( vOut, (int)pTime->tsense);
- Abc_SclWriteSurface( vOut, pTime->pCellRise );
- Abc_SclWriteSurface( vOut, pTime->pCellFall );
- Abc_SclWriteSurface( vOut, pTime->pRiseTrans );
- Abc_SclWriteSurface( vOut, pTime->pFallTrans );
+ Abc_SclWriteSurface( vOut, &pTime->pCellRise );
+ Abc_SclWriteSurface( vOut, &pTime->pCellFall );
+ Abc_SclWriteSurface( vOut, &pTime->pRiseTrans );
+ Abc_SclWriteSurface( vOut, &pTime->pFallTrans );
}
else
- assert( Vec_PtrSize(pRTime->vTimings) == 0 );
+ assert( Vec_PtrSize(&pRTime->vTimings) == 0 );
}
}
}
@@ -480,21 +483,21 @@ static void Abc_SclWriteSurfaceText( FILE * s, SC_Surface * p )
int i, k;
fprintf( s, " index_1(\"" );
- Vec_FltForEachEntry( p->vIndex0, Entry, i )
- fprintf( s, "%f%s", Entry, i == Vec_FltSize(p->vIndex0)-1 ? "":", " );
+ Vec_FltForEachEntry( &p->vIndex0, Entry, i )
+ fprintf( s, "%f%s", Entry, i == Vec_FltSize(&p->vIndex0)-1 ? "":", " );
fprintf( s, "\");\n" );
fprintf( s, " index_2(\"" );
- Vec_FltForEachEntry( p->vIndex1, Entry, i )
- fprintf( s, "%f%s", Entry, i == Vec_FltSize(p->vIndex1)-1 ? "":", " );
+ Vec_FltForEachEntry( &p->vIndex1, Entry, i )
+ fprintf( s, "%f%s", Entry, i == Vec_FltSize(&p->vIndex1)-1 ? "":", " );
fprintf( s, "\");\n" );
fprintf( s, " values (\"" );
- Vec_PtrForEachEntry( Vec_Flt_t *, p->vData, vVec, i )
+ Vec_PtrForEachEntry( Vec_Flt_t *, &p->vData, vVec, i )
{
Vec_FltForEachEntry( vVec, Entry, k )
- fprintf( s, "%f%s", Entry, i == Vec_PtrSize(p->vData)-1 && k == Vec_FltSize(vVec)-1 ? "\");":", " );
- if ( i == Vec_PtrSize(p->vData)-1 )
+ fprintf( s, "%f%s", Entry, i == Vec_PtrSize(&p->vData)-1 && k == Vec_FltSize(vVec)-1 ? "\");":", " );
+ if ( i == Vec_PtrSize(&p->vData)-1 )
fprintf( s, "\n" );
else
{
@@ -556,8 +559,8 @@ static void Abc_SclWriteLibraryText( FILE * s, SC_Lib * p )
fprintf( s, " wire_load(\"%s\") {\n", pWL->pName );
fprintf( s, " capacitance : %f;\n", pWL->cap );
fprintf( s, " slope : %f;\n", pWL->slope );
- for ( j = 0; j < Vec_IntSize(pWL->vFanout); j++ )
- fprintf( s, " fanout_length( %d, %f );\n", Vec_IntEntry(pWL->vFanout, j), Vec_FltEntry(pWL->vLen, j) );
+ for ( j = 0; j < Vec_IntSize(&pWL->vFanout); j++ )
+ fprintf( s, " fanout_length( %d, %f );\n", Vec_IntEntry(&pWL->vFanout, j), Vec_FltEntry(&pWL->vLen, j) );
fprintf( s, " }\n\n" );
}
@@ -565,11 +568,11 @@ static void Abc_SclWriteLibraryText( FILE * s, SC_Lib * p )
SC_LibForEachWireLoadSel( p, pWLS, i )
{
fprintf( s, " wire_load_selection(\"%s\") {\n", pWLS->pName );
- for ( j = 0; j < Vec_FltSize(pWLS->vAreaFrom); j++)
+ for ( j = 0; j < Vec_FltSize(&pWLS->vAreaFrom); j++)
fprintf( s, " wire_load_from_area( %f, %f, %s );\n",
- Vec_FltEntry(pWLS->vAreaFrom, j),
- Vec_FltEntry(pWLS->vAreaTo, j),
- (char *)Vec_PtrEntry(pWLS->vWireLoadModel, j) );
+ Vec_FltEntry(&pWLS->vAreaFrom, j),
+ Vec_FltEntry(&pWLS->vAreaTo, j),
+ (char *)Vec_PtrEntry(&pWLS->vWireLoadModel, j) );
fprintf( s, " }\n\n" );
}
@@ -612,16 +615,16 @@ static void Abc_SclWriteLibraryText( FILE * s, SC_Lib * p )
fprintf( s, " max_transition : %f;\n", pPin->max_out_slew );
fprintf( s, " function : \"%s\";\n", pPin->func_text ? pPin->func_text : "?" );
fprintf( s, " /* truth table = " );
- Extra_PrintHex( s, (unsigned *)Vec_WrdArray(pPin->vFunc), pCell->n_inputs );
+ Extra_PrintHex( s, (unsigned *)Vec_WrdArray(&pPin->vFunc), pCell->n_inputs );
fprintf( s, " */\n" );
// Write 'rtiming': (pin-to-pin timing tables for this particular output)
- assert( Vec_PtrSize(pPin->vRTimings) == pCell->n_inputs );
+ assert( Vec_PtrSize(&pPin->vRTimings) == pCell->n_inputs );
SC_PinForEachRTiming( pPin, pRTime, k )
{
- if ( Vec_PtrSize(pRTime->vTimings) == 1 )
+ if ( Vec_PtrSize(&pRTime->vTimings) == 1 )
{
- SC_Timing * pTime = (SC_Timing *)Vec_PtrEntry( pRTime->vTimings, 0 );
+ SC_Timing * pTime = (SC_Timing *)Vec_PtrEntry( &pRTime->vTimings, 0 );
fprintf( s, " timing() {\n" );
fprintf( s, " related_pin : \"%s\"\n", pRTime->pName );
if ( pTime->tsense == sc_ts_Pos )
@@ -633,24 +636,24 @@ static void Abc_SclWriteLibraryText( FILE * s, SC_Lib * p )
else assert( 0 );
fprintf( s, " cell_rise() {\n" );
- Abc_SclWriteSurfaceText( s, pTime->pCellRise );
+ Abc_SclWriteSurfaceText( s, &pTime->pCellRise );
fprintf( s, " }\n" );
fprintf( s, " cell_fall() {\n" );
- Abc_SclWriteSurfaceText( s, pTime->pCellFall );
+ Abc_SclWriteSurfaceText( s, &pTime->pCellFall );
fprintf( s, " }\n" );
fprintf( s, " rise_transition() {\n" );
- Abc_SclWriteSurfaceText( s, pTime->pRiseTrans );
+ Abc_SclWriteSurfaceText( s, &pTime->pRiseTrans );
fprintf( s, " }\n" );
fprintf( s, " fall_transition() {\n" );
- Abc_SclWriteSurfaceText( s, pTime->pFallTrans );
+ Abc_SclWriteSurfaceText( s, &pTime->pFallTrans );
fprintf( s, " }\n" );
fprintf( s, " }\n" );
}
else
- assert( Vec_PtrSize(pRTime->vTimings) == 0 );
+ assert( Vec_PtrSize(&pRTime->vTimings) == 0 );
}
fprintf( s, " }\n" );
}
diff --git a/src/map/scl/sclLibUtil.c b/src/map/scl/sclLibUtil.c
index 986ea434..cb1655f6 100644
--- a/src/map/scl/sclLibUtil.c
+++ b/src/map/scl/sclLibUtil.c
@@ -166,7 +166,7 @@ static inline void Abc_SclTimingUpdate( SC_Cell * pCell, SC_Timing * p, char * B
static inline void Abc_SclTimingsUpdate( SC_Cell * pCell, SC_Timings * p, char * Buffer )
{
SC_Timing * pTemp; int i;
- Vec_PtrForEachEntry( SC_Timing *, p->vTimings, pTemp, i )
+ Vec_PtrForEachEntry( SC_Timing *, &p->vTimings, pTemp, i )
Abc_SclTimingUpdate( pCell, pTemp, Buffer );
}
static inline void Abc_SclPinUpdate( SC_Cell * pCell, SC_Pin * p, char * Buffer )
@@ -264,7 +264,7 @@ void Abc_SclLinkCells( SC_Lib * p )
Vec_Ptr_t * vList;
SC_Cell * pCell, * pRepr = NULL;
int i, k;
- assert( Vec_PtrSize(p->vCellClasses) == 0 );
+ assert( Vec_PtrSize(&p->vCellClasses) == 0 );
SC_LibForEachCell( p, pCell, i )
{
// find gate with the same function
@@ -273,9 +273,9 @@ void Abc_SclLinkCells( SC_Lib * p )
pCell->n_outputs == pRepr->n_outputs &&
Vec_WrdEqual(SC_CellFunc(pCell), SC_CellFunc(pRepr)) )
break;
- if ( k == Vec_PtrSize(p->vCellClasses) )
+ if ( k == Vec_PtrSize(&p->vCellClasses) )
{
- Vec_PtrPush( p->vCellClasses, pCell );
+ Vec_PtrPush( &p->vCellClasses, pCell );
pCell->pNext = pCell->pPrev = pCell;
continue;
}
@@ -284,7 +284,7 @@ void Abc_SclLinkCells( SC_Lib * p )
pCell->pPrev = pRepr->pPrev; pRepr->pPrev = pCell;
}
// sort cells by size then by name
- qsort( (void *)Vec_PtrArray(p->vCellClasses), Vec_PtrSize(p->vCellClasses), sizeof(void *), (int(*)(const void *,const void *))Abc_SclCompareCells );
+ qsort( (void *)Vec_PtrArray(&p->vCellClasses), Vec_PtrSize(&p->vCellClasses), sizeof(void *), (int(*)(const void *,const void *))Abc_SclCompareCells );
// sort cell lists
vList = Vec_PtrAlloc( 100 );
SC_LibForEachCellClass( p, pRepr, k )
@@ -311,7 +311,7 @@ void Abc_SclLinkCells( SC_Lib * p )
pCell->nGates = Vec_PtrSize(vList);
}
// update list
- Vec_PtrWriteEntry( p->vCellClasses, k, pRepr );
+ Vec_PtrWriteEntry( &p->vCellClasses, k, pRepr );
}
Vec_PtrFree( vList );
}
@@ -333,7 +333,7 @@ SC_Cell * Abc_SclFindInvertor( SC_Lib * p, int fFindBuff )
word Truth = fFindBuff ? ABC_CONST(0xAAAAAAAAAAAAAAAA) : ABC_CONST(0x5555555555555555);
int k;
SC_LibForEachCellClass( p, pCell, k )
- if ( pCell->n_inputs == 1 && Vec_WrdEntry(SC_CellPin(pCell, 1)->vFunc, 0) == Truth )
+ if ( pCell->n_inputs == 1 && Vec_WrdEntry(&SC_CellPin(pCell, 1)->vFunc, 0) == Truth )
break;
// take representative
return pCell ? pCell->pRepr : NULL;
@@ -369,7 +369,7 @@ SC_WireLoad * Abc_SclFetchWireLoadModel( SC_Lib * p, char * pWLoadUsed )
SC_LibForEachWireLoad( p, pWL, i )
if ( !strcmp(pWL->pName, pWLoadUsed) )
break;
- if ( i == Vec_PtrSize(p->vWireLoads) )
+ if ( i == Vec_PtrSize(&p->vWireLoads) )
{
Abc_Print( -1, "Cannot find wire load model \"%s\".\n", pWLoadUsed );
exit(1);
@@ -387,19 +387,19 @@ SC_WireLoad * Abc_SclFindWireLoadModel( SC_Lib * p, float Area )
SC_LibForEachWireLoadSel( p, pWLS, i )
if ( !strcmp(pWLS->pName, p->default_wire_load_sel) )
break;
- if ( i == Vec_PtrSize(p->vWireLoadSels) )
+ if ( i == Vec_PtrSize(&p->vWireLoadSels) )
{
Abc_Print( -1, "Cannot find wire load selection model \"%s\".\n", p->default_wire_load_sel );
exit(1);
}
- for ( i = 0; i < Vec_FltSize(pWLS->vAreaFrom); i++)
- if ( Area >= Vec_FltEntry(pWLS->vAreaFrom, i) && Area < Vec_FltEntry(pWLS->vAreaTo, i) )
+ for ( i = 0; i < Vec_FltSize(&pWLS->vAreaFrom); i++)
+ if ( Area >= Vec_FltEntry(&pWLS->vAreaFrom, i) && Area < Vec_FltEntry(&pWLS->vAreaTo, i) )
{
- pWLoadUsed = (char *)Vec_PtrEntry(pWLS->vWireLoadModel, i);
+ pWLoadUsed = (char *)Vec_PtrEntry(&pWLS->vWireLoadModel, i);
break;
}
- if ( i == Vec_FltSize(pWLS->vAreaFrom) )
- pWLoadUsed = (char *)Vec_PtrEntryLast(pWLS->vWireLoadModel);
+ if ( i == Vec_FltSize(&pWLS->vAreaFrom) )
+ pWLoadUsed = (char *)Vec_PtrEntryLast(&pWLS->vWireLoadModel);
}
else if ( p->default_wire_load && strlen(p->default_wire_load) )
pWLoadUsed = p->default_wire_load;
@@ -458,7 +458,7 @@ float Abc_SclComputeAverageSlew( SC_Lib * p )
pTime = Scl_CellPinTime( pCell, 0 );
if ( pTime == NULL )
return 0;
- vIndex = pTime->pCellRise->vIndex0; // slew
+ vIndex = &pTime->pCellRise.vIndex0; // slew
return Vec_FltEntry( vIndex, Vec_FltSize(vIndex)/3 );
}
@@ -483,14 +483,14 @@ int Abc_SclComputeParametersPin( SC_Lib * p, SC_Cell * pCell, int iPin, float Sl
SC_Pair ArrOut2 = { 0.0, 0.0 };
SC_Pair SlewOut = { 0.0, 0.0 };
SC_Timing * pTime = Scl_CellPinTime( pCell, iPin );
- Vec_Flt_t * vIndex = pTime ? pTime->pCellRise->vIndex1 : NULL; // capacitance
+ Vec_Flt_t * vIndex = pTime ? &pTime->pCellRise.vIndex1 : NULL; // capacitance
if ( vIndex == NULL )
return 0;
// handle constant table
if ( Vec_FltSize(vIndex) == 1 )
{
*pLD = 0;
- *pPD = Vec_FltEntry( (Vec_Flt_t *)Vec_PtrEntry(pTime->pCellRise->vData, 0), 0 );
+ *pPD = Vec_FltEntry( (Vec_Flt_t *)Vec_PtrEntry(&pTime->pCellRise.vData, 0), 0 );
return 1;
}
// get load points
@@ -640,10 +640,10 @@ void Abc_SclPrintCells( SC_Lib * p, float SlewInit, float Gain, int fInvOnly, in
int i, j, k, nLength = 0;
float Slew = (SlewInit == 0) ? Abc_SclComputeAverageSlew(p) : SlewInit;
float LD = 0, PD = 0;
- assert( Vec_PtrSize(p->vCellClasses) > 0 );
+ assert( Vec_PtrSize(&p->vCellClasses) > 0 );
printf( "Library \"%s\" ", p->pName );
printf( "has %d cells in %d classes. ",
- Vec_PtrSize(p->vCells), Vec_PtrSize(p->vCellClasses) );
+ Vec_PtrSize(&p->vCells), Vec_PtrSize(&p->vCellClasses) );
if ( !fShort )
printf( "Delay estimate is based on slew %.2f ps and gain %.2f.", Slew, Gain );
printf( "\n" );
@@ -671,7 +671,7 @@ void Abc_SclPrintCells( SC_Lib * p, float SlewInit, float Gain, int fInvOnly, in
if ( pPin->func_text )
printf( "%-30s", pPin->func_text );
printf( " " );
- Kit_DsdPrintFromTruth( (unsigned *)Vec_WrdArray(pPin->vFunc), pRepr->n_inputs );
+ Kit_DsdPrintFromTruth( (unsigned *)Vec_WrdArray(&pPin->vFunc), pRepr->n_inputs );
printf( "\n" );
if ( fShort )
continue;
@@ -737,11 +737,11 @@ void Abc_SclLibNormalizeSurface( SC_Surface * p, float Time, float Load )
{
Vec_Flt_t * vArray;
int i, k; float Entry;
- Vec_FltForEachEntry( p->vIndex0, Entry, i ) // slew
- Vec_FltWriteEntry( p->vIndex0, i, Time * Entry );
- Vec_FltForEachEntry( p->vIndex1, Entry, i ) // load
- Vec_FltWriteEntry( p->vIndex1, i, Load * Entry );
- Vec_PtrForEachEntry( Vec_Flt_t *, p->vData, vArray, k )
+ Vec_FltForEachEntry( &p->vIndex0, Entry, i ) // slew
+ Vec_FltWriteEntry( &p->vIndex0, i, Time * Entry );
+ Vec_FltForEachEntry( &p->vIndex1, Entry, i ) // load
+ Vec_FltWriteEntry( &p->vIndex1, i, Load * Entry );
+ Vec_PtrForEachEntry( Vec_Flt_t *, &p->vData, vArray, k )
Vec_FltForEachEntry( vArray, Entry, i ) // delay/slew
Vec_FltWriteEntry( vArray, i, Time * Entry );
}
@@ -772,12 +772,12 @@ void Abc_SclLibNormalize( SC_Lib * p )
pPin->max_out_cap *= Load;
pPin->max_out_slew *= Time;
SC_PinForEachRTiming( pPin, pTimings, m )
- Vec_PtrForEachEntry( SC_Timing *, pTimings->vTimings, pTiming, n )
+ Vec_PtrForEachEntry( SC_Timing *, &pTimings->vTimings, pTiming, n )
{
- Abc_SclLibNormalizeSurface( pTiming->pCellRise, Time, Load );
- Abc_SclLibNormalizeSurface( pTiming->pCellFall, Time, Load );
- Abc_SclLibNormalizeSurface( pTiming->pRiseTrans, Time, Load );
- Abc_SclLibNormalizeSurface( pTiming->pFallTrans, Time, Load );
+ Abc_SclLibNormalizeSurface( &pTiming->pCellRise, Time, Load );
+ Abc_SclLibNormalizeSurface( &pTiming->pCellFall, Time, Load );
+ Abc_SclLibNormalizeSurface( &pTiming->pRiseTrans, Time, Load );
+ Abc_SclLibNormalizeSurface( &pTiming->pFallTrans, Time, Load );
}
}
}
diff --git a/src/map/scl/sclLoad.c b/src/map/scl/sclLoad.c
index 0032ed33..f44d4df8 100644
--- a/src/map/scl/sclLoad.c
+++ b/src/map/scl/sclLoad.c
@@ -50,12 +50,12 @@ Vec_Flt_t * Abc_SclFindWireCaps( SC_WireLoad * pWL, int nFanoutMax )
assert( pWL != NULL );
// find the biggest fanout count
EntryMax = 0;
- Vec_IntForEachEntry( pWL->vFanout, Entry, i )
+ Vec_IntForEachEntry( &pWL->vFanout, Entry, i )
EntryMax = Abc_MaxInt( EntryMax, Entry );
// create the array
vCaps = Vec_FltStart( Abc_MaxInt(nFanoutMax, EntryMax) + 1 );
- Vec_IntForEachEntry( pWL->vFanout, Entry, i )
- Vec_FltWriteEntry( vCaps, Entry, Vec_FltEntry(pWL->vLen, i) * pWL->cap );
+ Vec_IntForEachEntry( &pWL->vFanout, Entry, i )
+ Vec_FltWriteEntry( vCaps, Entry, Vec_FltEntry(&pWL->vLen, i) * pWL->cap );
if ( Vec_FltEntry(vCaps, 1) == 0 )
return vCaps;
// interpolate between the values
diff --git a/src/map/scl/sclUtil.c b/src/map/scl/sclUtil.c
index 40d7c638..70140044 100644
--- a/src/map/scl/sclUtil.c
+++ b/src/map/scl/sclUtil.c
@@ -192,7 +192,7 @@ Vec_Int_t * Abc_SclFindMinAreas( SC_Lib * pLib, int fUseMax )
SC_Cell * pCell, * pRepr = NULL, * pBest = NULL;
int i, k;
// map each gate in the library into its min/max-size prototype
- vMinCells = Vec_IntStartFull( Vec_PtrSize(pLib->vCells) );
+ vMinCells = Vec_IntStartFull( Vec_PtrSize(&pLib->vCells) );
SC_LibForEachCellClass( pLib, pRepr, i )
{
pBest = fUseMax ? Abc_SclFindMaxAreaCell(pRepr) : pRepr;
@@ -211,9 +211,9 @@ void Abc_SclMinsizePerform( SC_Lib * pLib, Abc_Ntk_t * p, int fUseMax, int fVerb
Abc_NtkForEachNodeNotBarBuf1( p, pObj, i )
{
gateId = Vec_IntEntry( p->vGates, i );
- assert( gateId >= 0 && gateId < Vec_PtrSize(pLib->vCells) );
+ assert( gateId >= 0 && gateId < Vec_PtrSize(&pLib->vCells) );
gateId = Vec_IntEntry( vMinCells, gateId );
- assert( gateId >= 0 && gateId < Vec_PtrSize(pLib->vCells) );
+ assert( gateId >= 0 && gateId < Vec_PtrSize(&pLib->vCells) );
Vec_IntWriteEntry( p->vGates, i, gateId );
}
Abc_SclSclGates2MioGates( pLib, p );