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| author | Alan Mishchenko <alanmi@berkeley.edu> | 2019-04-16 21:37:45 -0700 |
|---|---|---|
| committer | Alan Mishchenko <alanmi@berkeley.edu> | 2019-04-16 21:37:45 -0700 |
| commit | d1b6413d1cafdd302ad6f45eb366320f758fa716 (patch) | |
| tree | e48107e24a7666e960b833aef16bd74aa8190151 /src/misc/tim | |
| parent | f5320744fa986eb08495f079717c483f1871cfc8 (diff) | |
| download | abc-d1b6413d1cafdd302ad6f45eb366320f758fa716.tar.gz abc-d1b6413d1cafdd302ad6f45eb366320f758fa716.tar.bz2 abc-d1b6413d1cafdd302ad6f45eb366320f758fa716.zip | |
Fix index of delay tables created by %blast.
Diffstat (limited to 'src/misc/tim')
| -rw-r--r-- | src/misc/tim/tim.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/misc/tim/tim.h b/src/misc/tim/tim.h index 266688dd..06019f56 100644 --- a/src/misc/tim/tim.h +++ b/src/misc/tim/tim.h @@ -55,7 +55,7 @@ Finally, the TFO cone of the POs is traversed and all new logic nodes encountered added to the AIG. In the end, the POs of the AIG is constructed in 1-to-1 correspondence with - the PIs of the original combinational logic network. + the POs of the original combinational logic network. Delay tables representing input-to-output delays of each type of white box should be computed in advance and given to the timing manager in one array |