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author | Alan Mishchenko <alanmi@berkeley.edu> | 2016-05-07 19:47:02 -0700 |
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committer | Alan Mishchenko <alanmi@berkeley.edu> | 2016-05-07 19:47:02 -0700 |
commit | 236d412255e5007adac97c05e759bfd5069bc1c1 (patch) | |
tree | 8b43abfb5798f47586e6f5dcd0acf8a07f61a722 /src/proof/acec/acecCore.c | |
parent | 40d90ae69c4bb84e20e98aab127788a8b1755faa (diff) | |
download | abc-236d412255e5007adac97c05e759bfd5069bc1c1.tar.gz abc-236d412255e5007adac97c05e759bfd5069bc1c1.tar.bz2 abc-236d412255e5007adac97c05e759bfd5069bc1c1.zip |
Experiments with CEC for arithmetic circuits.
Diffstat (limited to 'src/proof/acec/acecCore.c')
-rw-r--r-- | src/proof/acec/acecCore.c | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/src/proof/acec/acecCore.c b/src/proof/acec/acecCore.c new file mode 100644 index 00000000..bfece8dc --- /dev/null +++ b/src/proof/acec/acecCore.c @@ -0,0 +1,60 @@ +/**CFile**************************************************************** + + FileName [acecCore.c] + + SystemName [ABC: Logic synthesis and verification system.] + + PackageName [CEC for arithmetic circuits.] + + Synopsis [Core procedures.] + + Author [Alan Mishchenko] + + Affiliation [UC Berkeley] + + Date [Ver. 1.0. Started - June 20, 2005.] + + Revision [$Id: acecCore.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $] + +***********************************************************************/ + +#include "acecInt.h" + +ABC_NAMESPACE_IMPL_START + + +//////////////////////////////////////////////////////////////////////// +/// DECLARATIONS /// +//////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////// +/// FUNCTION DEFINITIONS /// +//////////////////////////////////////////////////////////////////////// + +/**Function************************************************************* + + Synopsis [] + + Description [] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ +int Gia_PolynCec( Gia_Man_t * pGia0, Gia_Man_t * pGia1, Cec_ParCec_t * pPars ) +{ + Vec_Int_t * vOrder0 = Gia_PolynReorder( pGia0, pPars->fVerbose ); + Vec_Int_t * vOrder1 = Gia_PolynReorder( pGia1, pPars->fVerbose ); + Gia_PolynBuild( pGia0, vOrder0, pPars->fVerbose ); + Gia_PolynBuild( pGia1, vOrder1, pPars->fVerbose ); + return 1; +} + +//////////////////////////////////////////////////////////////////////// +/// END OF FILE /// +//////////////////////////////////////////////////////////////////////// + + +ABC_NAMESPACE_IMPL_END + |