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| author | Alan Mishchenko <alanmi@berkeley.edu> | 2016-02-01 15:56:53 -0800 |
|---|---|---|
| committer | Alan Mishchenko <alanmi@berkeley.edu> | 2016-02-01 15:56:53 -0800 |
| commit | 02725c9eca9512572013d54286cd63cd52bed9ea (patch) | |
| tree | 9fdd41d65c0218204e7a130e42bd745dad5b9f4e /src | |
| parent | 81dade194e30b6fa5f98352a76459c062d27e66f (diff) | |
| download | abc-02725c9eca9512572013d54286cd63cd52bed9ea.tar.gz abc-02725c9eca9512572013d54286cd63cd52bed9ea.tar.bz2 abc-02725c9eca9512572013d54286cd63cd52bed9ea.zip | |
An add-on to write Verilog for circuits mapped into simple gates.
Diffstat (limited to 'src')
| -rw-r--r-- | src/base/io/ioWriteVerilog.c | 31 |
1 files changed, 22 insertions, 9 deletions
diff --git a/src/base/io/ioWriteVerilog.c b/src/base/io/ioWriteVerilog.c index 5ba8258c..c909e846 100644 --- a/src/base/io/ioWriteVerilog.c +++ b/src/base/io/ioWriteVerilog.c @@ -485,6 +485,7 @@ void Io_WriteVerilogLatches( FILE * pFile, Abc_Ntk_t * pNtk ) ***********************************************************************/ void Io_WriteVerilogObjects( FILE * pFile, Abc_Ntk_t * pNtk ) { + int fUseSimpleGateNames = 0; Vec_Vec_t * vLevels; Abc_Ntk_t * pNtkBox; Abc_Obj_t * pObj, * pTerm, * pFanin; @@ -529,17 +530,29 @@ void Io_WriteVerilogObjects( FILE * pFile, Abc_Ntk_t * pNtk ) continue; } // write the node - fprintf( pFile, " %-*s g%0*d", Length, Mio_GateReadName(pGate), nDigits, Counter++ ); - fprintf( pFile, "(" ); - for ( pGatePin = Mio_GateReadPins(pGate), i = 0; pGatePin; pGatePin = Mio_PinReadNext(pGatePin), i++ ) + if ( fUseSimpleGateNames ) { - fprintf( pFile, ".%s", Io_WriteVerilogGetName(Mio_PinReadName(pGatePin)) ); - fprintf( pFile, "(%s), ", Io_WriteVerilogGetName(Abc_ObjName( Abc_ObjFanin(pObj,i) )) ); + fprintf( pFile, "%-*s ", Length, Mio_GateReadName(pGate) ); + fprintf( pFile, "( %s", Io_WriteVerilogGetName(Abc_ObjName( Abc_ObjFanout0(pObj) )) ); + for ( pGatePin = Mio_GateReadPins(pGate), i = 0; pGatePin; pGatePin = Mio_PinReadNext(pGatePin), i++ ) + fprintf( pFile, ", %s", Io_WriteVerilogGetName(Abc_ObjName( Abc_ObjFanin(pObj,i) )) ); + assert ( i == Abc_ObjFaninNum(pObj) ); + fprintf( pFile, " );\n" ); + } + else + { + fprintf( pFile, " %-*s g%0*d", Length, Mio_GateReadName(pGate), nDigits, Counter++ ); + fprintf( pFile, "(" ); + for ( pGatePin = Mio_GateReadPins(pGate), i = 0; pGatePin; pGatePin = Mio_PinReadNext(pGatePin), i++ ) + { + fprintf( pFile, ".%s", Io_WriteVerilogGetName(Mio_PinReadName(pGatePin)) ); + fprintf( pFile, "(%s), ", Io_WriteVerilogGetName(Abc_ObjName( Abc_ObjFanin(pObj,i) )) ); + } + assert ( i == Abc_ObjFaninNum(pObj) ); + fprintf( pFile, ".%s", Io_WriteVerilogGetName(Mio_GateReadOutName(pGate)) ); + fprintf( pFile, "(%s)", Io_WriteVerilogGetName(Abc_ObjName( Abc_ObjFanout0(pObj) )) ); + fprintf( pFile, ");\n" ); } - assert ( i == Abc_ObjFaninNum(pObj) ); - fprintf( pFile, ".%s", Io_WriteVerilogGetName(Mio_GateReadOutName(pGate)) ); - fprintf( pFile, "(%s)", Io_WriteVerilogGetName(Abc_ObjName( Abc_ObjFanout0(pObj) )) ); - fprintf( pFile, ");\n" ); } } else |