diff options
author | Alan Mishchenko <alanmi@berkeley.edu> | 2007-09-30 08:01:00 -0700 |
---|---|---|
committer | Alan Mishchenko <alanmi@berkeley.edu> | 2007-09-30 08:01:00 -0700 |
commit | e54d9691616b9a0326e2fdb3156bb4eeb8abfcd7 (patch) | |
tree | de3ffe87c3e17950351e3b7d97fa18318bd5ea9a /todo.txt | |
parent | 7d7e60f2dc84393cd4c5db22d2eaf7b1fb1a79b2 (diff) | |
download | abc-e54d9691616b9a0326e2fdb3156bb4eeb8abfcd7.tar.gz abc-e54d9691616b9a0326e2fdb3156bb4eeb8abfcd7.tar.bz2 abc-e54d9691616b9a0326e2fdb3156bb4eeb8abfcd7.zip |
Version abc70930
Diffstat (limited to 'todo.txt')
-rw-r--r-- | todo.txt | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/todo.txt b/todo.txt deleted file mode 100644 index 3ab59b8c..00000000 --- a/todo.txt +++ /dev/null @@ -1,26 +0,0 @@ -- required time support -- printing ABC version/platform in the output files -- fix gcc compiler warnings -- port "mfs" from MVSIS -- improve AIG rewriting package -- unify functional representation of local functions -- additional rewriting options for delay optimization -- experiment with yield-aware standard-cell mapping -- improving area recovery in integrated sequential synthesis -- high-effort logic synthesis for hard miters (cofactoring, Boolean division) -- mapping into MV cells -- SAT solver with linear constraints -- specialized synthesis for EXORs and large MUXes -- sequential AIG rewriting initial state computation -- placement-aware mapping -- sequential equivalence checking -- parser for Verilog netlists -- hierarchy manager (hierarchical BLIF/BLIF-MV parser) - -- required time based on all cuts -- comparing tts of differently derived the same cut -- area flow based AIG rewriting -- cut frontier adjustment - - - |