diff options
| -rw-r--r-- | src/base/abci/abc.c | 6 | ||||
| -rw-r--r-- | src/map/scl/scl.c | 15 | ||||
| -rw-r--r-- | src/proof/cec/cecSim.c | 2 |
3 files changed, 18 insertions, 5 deletions
diff --git a/src/base/abci/abc.c b/src/base/abci/abc.c index 417c7909..4297c81d 100644 --- a/src/base/abci/abc.c +++ b/src/base/abci/abc.c @@ -29886,8 +29886,10 @@ static inline int Abc_NtkCompareWithBest( Abc_Ntk_t * pBest, Abc_Ntk_t * p, Abc_NtkPoNum(pBest) != Abc_NtkPoNum(p) || Abc_NtkLatchNum(pBest) != Abc_NtkLatchNum(p) || strcmp(Abc_NtkName(pBest), Abc_NtkName(p)) || - (!fArea && (*pnBestNtkLevels > nNtkLevels || (*pnBestNtkLevels == nNtkLevels && *pnBestNtkDelay > nNtkDelay ))) || - ( fArea && (*pnBestNtkNodes > nNtkNodes || (*pnBestNtkNodes == nNtkNodes && *pnBestNtkArea > nNtkArea ))) +// (!fArea && (*pnBestNtkLevels > nNtkLevels || (*pnBestNtkLevels == nNtkLevels && *pnBestNtkDelay > nNtkDelay ))) || +// ( fArea && (*pnBestNtkNodes > nNtkNodes || (*pnBestNtkNodes == nNtkNodes && *pnBestNtkArea > nNtkArea ))) + (!fArea && (*pnBestNtkDelay > nNtkDelay || (*pnBestNtkDelay == nNtkDelay && *pnBestNtkArea > nNtkArea ))) || + ( fArea && (*pnBestNtkArea > nNtkArea || (*pnBestNtkArea == nNtkArea && *pnBestNtkDelay > nNtkDelay ))) ) { *pnBestNtkArea = nNtkArea; diff --git a/src/map/scl/scl.c b/src/map/scl/scl.c index 27342458..635ec19e 100644 --- a/src/map/scl/scl.c +++ b/src/map/scl/scl.c @@ -153,11 +153,12 @@ int Scl_CommandReadLib( Abc_Frame_t * pAbc, int argc, char ** argv ) float Gain = 0; int nGatesMin = 0; int fShortNames = 0; + int fUnit = 0; int fVerbose = 1; int fVeryVerbose = 0; Extra_UtilGetoptReset(); - while ( ( c = Extra_UtilGetopt( argc, argv, "SGMdnvwh" ) ) != EOF ) + while ( ( c = Extra_UtilGetopt( argc, argv, "SGMdnuvwh" ) ) != EOF ) { switch ( c ) { @@ -200,6 +201,9 @@ int Scl_CommandReadLib( Abc_Frame_t * pAbc, int argc, char ** argv ) case 'n': fShortNames ^= 1; break; + case 'u': + fUnit ^= 1; + break; case 'v': fVerbose ^= 1; break; @@ -242,6 +246,12 @@ int Scl_CommandReadLib( Abc_Frame_t * pAbc, int argc, char ** argv ) // dump the resulting library if ( fDump && pAbc->pLibScl ) Abc_SclWriteLiberty( Extra_FileNameGenericAppend(pFileName, "_temp.lib"), (SC_Lib *)pAbc->pLibScl ); + if ( fUnit ) + { + SC_Cell * pCell; int i; + SC_LibForEachCell( pLib, pCell, i ) + pCell->area = 1; + } // extract genlib library if ( pAbc->pLibScl ) { @@ -251,13 +261,14 @@ int Scl_CommandReadLib( Abc_Frame_t * pAbc, int argc, char ** argv ) return 0; usage: - fprintf( pAbc->Err, "usage: read_lib [-SG float] [-M num] [-dnvwh] <file>\n" ); + fprintf( pAbc->Err, "usage: read_lib [-SG float] [-M num] [-dnuvwh] <file>\n" ); fprintf( pAbc->Err, "\t reads Liberty library from file\n" ); fprintf( pAbc->Err, "\t-S float : the slew parameter used to generate the library [default = %.2f]\n", Slew ); fprintf( pAbc->Err, "\t-G float : the gain parameter used to generate the library [default = %.2f]\n", Gain ); fprintf( pAbc->Err, "\t-M num : skip gate classes whose size is less than this [default = %d]\n", nGatesMin ); fprintf( pAbc->Err, "\t-d : toggle dumping the parsed library into file \"*_temp.lib\" [default = %s]\n", fDump? "yes": "no" ); fprintf( pAbc->Err, "\t-n : toggle replacing gate/pin names by short strings [default = %s]\n", fShortNames? "yes": "no" ); + fprintf( pAbc->Err, "\t-u : toggle setting unit area for all cells [default = %s]\n", fUnit? "yes": "no" ); fprintf( pAbc->Err, "\t-v : toggle writing verbose information [default = %s]\n", fVerbose? "yes": "no" ); fprintf( pAbc->Err, "\t-w : toggle writing information about skipped gates [default = %s]\n", fVeryVerbose? "yes": "no" ); fprintf( pAbc->Err, "\t-h : prints the command summary\n" ); diff --git a/src/proof/cec/cecSim.c b/src/proof/cec/cecSim.c index 33bc11f5..48a789f3 100644 --- a/src/proof/cec/cecSim.c +++ b/src/proof/cec/cecSim.c @@ -328,7 +328,7 @@ int Cec_ManSRunSim( Cec_ManS_t * p, int iNode0, int iNode1 ) { abctime clk = Abc_Clock(); //Vec_Int_t * vLevel; - int pNodes[2] = { iNode0, iNode1 }; + //int pNodes[2] = { iNode0, iNode1 }; int i, iNode, Status, fDiff = Gia_ObjPhaseDiff( p->pAig, iNode0, iNode1 ); word * pSim00 = Cec_ManSSim( p, iNode0, 0 ); word * pSim01 = Cec_ManSSim( p, iNode0, 1 ); |