1 files changed, 44 insertions, 0 deletions
diff --git a/abc.dsp b/abc.dsp
index e25f44c8..e68fe877 100644
--- a/abc.dsp
+++ b/abc.dsp
@@ -293,6 +293,10 @@ SOURCE=.\src\base\io\ioReadBlif.c
 # End Source File
 # Begin Source File
 
+SOURCE=.\src\base\io\ioReadPla.c
+# End Source File
+# Begin Source File
+
 SOURCE=.\src\base\io\ioReadVerilog.c
 # End Source File
 # Begin Source File
@@ -315,6 +319,10 @@ SOURCE=.\src\base\io\ioWriteCnf.c
 
 SOURCE=.\src\base\io\ioWriteGate.c
 # End Source File
+# Begin Source File
+
+SOURCE=.\src\base\io\ioWritePla.c
+# End Source File
 # End Group
 # Begin Group "main"
 
@@ -972,6 +980,38 @@ SOURCE=.\src\sat\fraig\fraigUtil.c
 SOURCE=.\src\sat\fraig\fraigVec.c
 # End Source File
 # End Group
+# Begin Group "sim"
+
+# PROP Default_Filter ""
+# Begin Source File
+
+SOURCE=.\src\sat\sim\sim.h
+# End Source File
+# Begin Source File
+
+SOURCE=.\src\sat\sim\simMan.c
+# End Source File
+# Begin Source File
+
+SOURCE=.\src\sat\sim\simSat.c
+# End Source File
+# Begin Source File
+
+SOURCE=.\src\sat\sim\simSupp.c
+# End Source File
+# Begin Source File
+
+SOURCE=.\src\sat\sim\simSym.c
+# End Source File
+# Begin Source File
+
+SOURCE=.\src\sat\sim\simUnate.c
+# End Source File
+# Begin Source File
+
+SOURCE=.\src\sat\sim\simUtils.c
+# End Source File
+# End Group
 # End Group
 # Begin Group "opt"
 
@@ -1265,6 +1305,10 @@ SOURCE=.\src\misc\extra\extraUtilBdd.c
 # End Source File
 # Begin Source File
 
+SOURCE=.\src\misc\extra\extraUtilBitMatrix.c
+# End Source File
+# Begin Source File
+
 SOURCE=.\src\misc\extra\extraUtilFile.c
 # End Source File
 # Begin Source File