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-rw-r--r--src/base/abci/abc.c5
-rw-r--r--src/base/abci/abcDar.c70
-rw-r--r--src/base/abci/abcPrint.c4
-rw-r--r--src/base/abci/abcStrash.c9
-rw-r--r--src/base/abci/abcTiming.c7
5 files changed, 84 insertions, 11 deletions
diff --git a/src/base/abci/abc.c b/src/base/abci/abc.c
index ab83c9af..9939a54e 100644
--- a/src/base/abci/abc.c
+++ b/src/base/abci/abc.c
@@ -26396,6 +26396,11 @@ int Abc_CommandAbc9Show( Abc_Frame_t * pAbc, int argc, char ** argv )
Abc_Print( -1, "Abc_CommandAbc9Show(): There is no AIG.\n" );
return 1;
}
+ if ( Gia_ManBufNum(pAbc->pGia) )
+ {
+ Abc_Print( -1, "Abc_CommandAbc9Show(): Cannot show GIA with barrier buffers.\n" );
+ return 1;
+ }
pMan = Gia_ManToAigSimple( pAbc->pGia );
Aig_ManShow( pMan, 0, NULL );
Aig_ManStop( pMan );
diff --git a/src/base/abci/abcDar.c b/src/base/abci/abcDar.c
index d2b74beb..e00dcb9e 100644
--- a/src/base/abci/abcDar.c
+++ b/src/base/abci/abcDar.c
@@ -820,6 +820,8 @@ static inline Abc_Obj_t * Abc_NtkFromCellRead( Abc_Ntk_t * p, Vec_Int_t * vCopyL
int iObjNew = Vec_IntEntry( vCopyLits, Abc_Var2Lit(i, c) );
if ( iObjNew >= 0 )
return Abc_NtkObj(p, iObjNew);
+ // opposite phase should be already constructed
+ assert( 0 );
if ( i == 0 )
pObjNew = c ? Abc_NtkCreateNodeConst1(p) : Abc_NtkCreateNodeConst0(p);
else
@@ -838,7 +840,7 @@ Abc_Ntk_t * Abc_NtkFromCellMappedGia( Gia_Man_t * p )
Vec_Int_t * vCopyLits;
Abc_Obj_t * pObjNew, * pObjNewLi, * pObjNewLo;
Gia_Obj_t * pObj, * pObjLi, * pObjLo;
- int i, k, iLit, iFanLit, nDupGates, nCells;
+ int i, k, iLit, iFanLit, nDupGates, nCells, fNeedConst[2] = {0};
Mio_Cell_t * pCells = Mio_CollectRootsNewDefault( 6, &nCells, 0 );
assert( Gia_ManHasCellMapping(p) );
// start network
@@ -867,16 +869,74 @@ Abc_Ntk_t * Abc_NtkFromCellMappedGia( Gia_Man_t * p )
Abc_NtkFromCellWrite( vCopyLits, Gia_ObjId(p, pObjLo), 0, Abc_ObjId( pObjNewLo ) );
Abc_LatchSetInit0( pObjNew );
}
+
+ // create constants
+ Gia_ManForEachCo( p, pObj, i )
+ if ( Gia_ObjFaninId0p(p, pObj) == 0 )
+ fNeedConst[Gia_ObjFaninC0(pObj)] = 1;
+ if ( Gia_ManBufNum(p) )
+ Gia_ManForEachBuf( p, pObj, i )
+ if ( Gia_ObjFaninId0p(p, pObj) == 0 )
+ fNeedConst[Gia_ObjFaninC0(pObj)] = 1;
+ if ( fNeedConst[0] )
+ Abc_NtkFromCellWrite( vCopyLits, 0, 0, Abc_ObjId(Abc_NtkCreateNodeConst0(pNtkNew)) );
+ if ( fNeedConst[1] )
+ Abc_NtkFromCellWrite( vCopyLits, 0, 1, Abc_ObjId(Abc_NtkCreateNodeConst1(pNtkNew)) );
+
// rebuild the AIG
Gia_ManForEachCell( p, iLit )
{
- assert( Vec_IntEntry(vCopyLits, iLit) == -1 );
- pObjNew = Abc_NtkCreateNode( pNtkNew );
- Gia_CellForEachFanin( p, iLit, iFanLit, k )
+ int fSkip = 0;
+ if ( Gia_ObjIsCellBuf(p, iLit) )
+ {
+ assert( !Abc_LitIsCompl(iLit) );
+ // build buffer
+ pObjNew = Abc_NtkCreateNode( pNtkNew );
+ iFanLit = Gia_ObjFaninLit0p( p, Gia_ManObj(p, Abc_Lit2Var(iLit)) );
Abc_ObjAddFanin( pObjNew, Abc_NtkFromCellRead(pNtkNew, vCopyLits, Abc_Lit2Var(iFanLit), Abc_LitIsCompl(iFanLit)) );
- pObjNew->pData = Mio_LibraryReadGateByName( (Mio_Library_t *)pNtkNew->pManFunc, pCells[Gia_ObjCellId(p, iLit)].pName, NULL );
+ pObjNew->pData = NULL; // barrier buffer
+ assert( Abc_ObjIsBarBuf(pObjNew) );
+ pNtkNew->nBarBufs2++;
+ }
+ else if ( Gia_ObjIsCellInv(p, iLit) )
+ {
+ int iLitNot = Abc_LitNot(iLit);
+ if ( !Abc_LitIsCompl(iLit) ) // positive phase
+ {
+ // build negative phase
+ assert( Vec_IntEntry(vCopyLits, iLitNot) == -1 );
+ assert( Gia_ObjCellId(p, iLitNot) > 0 );
+ pObjNew = Abc_NtkCreateNode( pNtkNew );
+ Gia_CellForEachFanin( p, iLitNot, iFanLit, k )
+ Abc_ObjAddFanin( pObjNew, Abc_NtkFromCellRead(pNtkNew, vCopyLits, Abc_Lit2Var(iFanLit), Abc_LitIsCompl(iFanLit)) );
+ pObjNew->pData = Mio_LibraryReadGateByName( (Mio_Library_t *)pNtkNew->pManFunc, pCells[Gia_ObjCellId(p, iLitNot)].pName, NULL );
+ Abc_NtkFromCellWrite( vCopyLits, Abc_Lit2Var(iLitNot), Abc_LitIsCompl(iLitNot), Abc_ObjId(pObjNew) );
+ fSkip = 1;
+ }
+ else // negative phase
+ {
+ // positive phase is available
+ assert( Vec_IntEntry(vCopyLits, iLitNot) != -1 );
+ }
+ // build inverter
+ pObjNew = Abc_NtkCreateNode( pNtkNew );
+ Abc_ObjAddFanin( pObjNew, Abc_NtkFromCellRead(pNtkNew, vCopyLits, Abc_Lit2Var(iLit), Abc_LitIsCompl(iLitNot)) );
+ pObjNew->pData = Mio_LibraryReadGateByName( (Mio_Library_t *)pNtkNew->pManFunc, pCells[3].pName, NULL );
+ }
+ else
+ {
+ assert( Gia_ObjCellId(p, iLit) > 0 );
+ pObjNew = Abc_NtkCreateNode( pNtkNew );
+ Gia_CellForEachFanin( p, iLit, iFanLit, k )
+ Abc_ObjAddFanin( pObjNew, Abc_NtkFromCellRead(pNtkNew, vCopyLits, Abc_Lit2Var(iFanLit), Abc_LitIsCompl(iFanLit)) );
+ pObjNew->pData = Mio_LibraryReadGateByName( (Mio_Library_t *)pNtkNew->pManFunc, pCells[Gia_ObjCellId(p, iLit)].pName, NULL );
+ }
+ assert( Vec_IntEntry(vCopyLits, iLit) == -1 );
Abc_NtkFromCellWrite( vCopyLits, Abc_Lit2Var(iLit), Abc_LitIsCompl(iLit), Abc_ObjId(pObjNew) );
+ // skip next
+ iLit += fSkip;
}
+
// connect the PO nodes
Gia_ManForEachCo( p, pObj, i )
{
diff --git a/src/base/abci/abcPrint.c b/src/base/abci/abcPrint.c
index 27b9513e..02c06e65 100644
--- a/src/base/abci/abcPrint.c
+++ b/src/base/abci/abcPrint.c
@@ -306,7 +306,9 @@ void Abc_NtkPrintStats( Abc_Ntk_t * pNtk, int fFactored, int fSaveBest, int fDum
// Abc_Print( 1," var = %5d", Abc_NtkCiNum(pNtk) + Abc_NtkCoNum(pNtk)+Abc_NtkGetMultiRefNum(pNtk) );
}
else
- Abc_Print( 1," lev =%3d", Abc_NtkLevel(pNtk) );
+ Abc_Print( 1," lev = %d", Abc_NtkLevel(pNtk) );
+ if ( pNtk->nBarBufs2 )
+ Abc_Print( 1," buf = %d", pNtk->nBarBufs2 );
if ( fUseLutLib && Abc_FrameReadLibLut() )
Abc_Print( 1," delay =%5.2f", Abc_NtkDelayTraceLut(pNtk, 1) );
if ( fUseLutLib && Abc_FrameReadLibLut() )
diff --git a/src/base/abci/abcStrash.c b/src/base/abci/abcStrash.c
index 4dd6bf50..e4868d7e 100644
--- a/src/base/abci/abcStrash.c
+++ b/src/base/abci/abcStrash.c
@@ -412,7 +412,6 @@ int Abc_NtkAppend( Abc_Ntk_t * pNtk1, Abc_Ntk_t * pNtk2, int fAddPos )
***********************************************************************/
void Abc_NtkStrashPerform( Abc_Ntk_t * pNtkOld, Abc_Ntk_t * pNtkNew, int fAllNodes, int fRecord )
{
-// ProgressBar * pProgress;
Vec_Ptr_t * vNodes;
Abc_Obj_t * pNodeOld;
int i; //, clk = Abc_Clock();
@@ -422,13 +421,13 @@ void Abc_NtkStrashPerform( Abc_Ntk_t * pNtkOld, Abc_Ntk_t * pNtkNew, int fAllNod
vNodes = Abc_NtkDfsIter( pNtkOld, fAllNodes );
//printf( "Nodes = %d. ", Vec_PtrSize(vNodes) );
//ABC_PRT( "Time", Abc_Clock() - clk );
-// pProgress = Extra_ProgressBarStart( stdout, vNodes->nSize );
Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pNodeOld, i )
{
-// Extra_ProgressBarUpdate( pProgress, i, NULL );
- pNodeOld->pCopy = Abc_NodeStrash( pNtkNew, pNodeOld, fRecord );
+ if ( Abc_ObjIsBarBuf(pNodeOld) )
+ pNodeOld->pCopy = Abc_ObjChild0Copy(pNodeOld);
+ else
+ pNodeOld->pCopy = Abc_NodeStrash( pNtkNew, pNodeOld, fRecord );
}
-// Extra_ProgressBarStop( pProgress );
Vec_PtrFree( vNodes );
}
diff --git a/src/base/abci/abcTiming.c b/src/base/abci/abcTiming.c
index 2b378cf7..5484696a 100644
--- a/src/base/abci/abcTiming.c
+++ b/src/base/abci/abcTiming.c
@@ -828,6 +828,13 @@ void Abc_NodeDelayTraceArrival( Abc_Obj_t * pNode, Vec_Int_t * vSlacks )
// start the arrival time of the node
pTimeOut = Abc_NodeArrival(pNode);
pTimeOut->Rise = pTimeOut->Fall = -ABC_INFINITY;
+ // consider the buffer
+ if ( Abc_ObjIsBarBuf(pNode) )
+ {
+ pTimeIn = Abc_NodeArrival(Abc_ObjFanin0(pNode));
+ *pTimeOut = *pTimeIn;
+ return;
+ }
// go through the pins of the gate
pPin = Mio_GateReadPins((Mio_Gate_t *)pNode->pData);
Abc_ObjForEachFanin( pNode, pFanin, i )
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-07 20:46:37 +0000