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-rw-r--r--src/base/abcs/abcFpgaDelay.c327
-rw-r--r--src/base/abcs/abcFpgaSeq.c201
-rw-r--r--src/base/abcs/abcRetCore.c145
-rw-r--r--src/base/abcs/abcRetDelay.c504
-rw-r--r--src/base/abcs/abcRetImpl.c450
-rw-r--r--src/base/abcs/abcRetUtil.c244
-rw-r--r--src/base/abcs/abcSeq.c365
-rw-r--r--src/base/abcs/abcSeqMan.c218
-rw-r--r--src/base/abcs/abcShare.c160
-rw-r--r--src/base/abcs/abcUtils.c172
-rw-r--r--src/base/abcs/abcs.h355
-rw-r--r--src/base/abcs/module.make9
12 files changed, 0 insertions, 3150 deletions
diff --git a/src/base/abcs/abcFpgaDelay.c b/src/base/abcs/abcFpgaDelay.c
deleted file mode 100644
index 65ea4789..00000000
--- a/src/base/abcs/abcFpgaDelay.c
+++ /dev/null
@@ -1,327 +0,0 @@
-/**CFile****************************************************************
-
- FileName [abcFpgaDelay.c]
-
- SystemName [ABC: Logic synthesis and verification system.]
-
- PackageName [Network and node package.]
-
- Synopsis [Utilities working sequential AIGs.]
-
- Author [Alan Mishchenko]
-
- Affiliation [UC Berkeley]
-
- Date [Ver. 1.0. Started - June 20, 2005.]
-
- Revision [$Id: abcFpgaDelay.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "abcs.h"
-#include "cut.h"
-
-////////////////////////////////////////////////////////////////////////
-/// DECLARATIONS ///
-////////////////////////////////////////////////////////////////////////
-
-// the internal procedures
-static int Abc_NtkFpgaRetimeSearch_rec( Seq_FpgaMan_t * p, Abc_Ntk_t * pNtk, int FiMin, int FiMax, int fVerbose );
-static int Abc_NtkFpgaRetimeForPeriod( Seq_FpgaMan_t * p, Abc_Ntk_t * pNtk, int Fi, int fVerbose );
-static int Abc_NodeFpgaUpdateLValue( Seq_FpgaMan_t * p, Abc_Obj_t * pObj, int Fi );
-static void Abc_NtkFpgaCollect( Seq_FpgaMan_t * p );
-
-// node status after updating its arrival time
-enum { ABC_FPGA_UPDATE_FAIL, ABC_FPGA_UPDATE_NO, ABC_FPGA_UPDATE_YES };
-
-////////////////////////////////////////////////////////////////////////
-/// FUNCTION DEFINITIONS ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
- Synopsis [Retimes AIG for optimal delay.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Abc_NtkFpgaSeqRetimeDelayLags( Seq_FpgaMan_t * p )
-{
- Abc_Ntk_t * pNtk = p->pNtk;
- int fVerbose = p->fVerbose;
- Abc_Obj_t * pNode;
- int i, FiMax, FiBest, RetValue;
-
- // start storage for sequential arrival times
- assert( pNtk->pData == NULL );
- pNtk->pData = p->vArrivals;
-
- // get the upper bound on the clock period
-// FiMax = Abc_NtkNodeNum(pNtk);
- FiMax = 0;
- Abc_AigForEachAnd( pNtk, pNode, i )
- if ( FiMax < (int)pNode->Level )
- FiMax = pNode->Level;
- FiMax += 2;
-
- // make sure this clock period is feasible
- assert( Abc_NtkFpgaRetimeForPeriod( p, pNtk, FiMax, fVerbose ) );
-
- // search for the optimal clock period between 0 and nLevelMax
- FiBest = Abc_NtkFpgaRetimeSearch_rec( p, pNtk, 0, FiMax, fVerbose );
-
- // recompute the best LValues
- RetValue = Abc_NtkFpgaRetimeForPeriod( p, pNtk, FiBest, fVerbose );
- assert( RetValue );
-
- // print the result
- if ( fVerbose )
- printf( "The best clock period is %3d.\n", FiBest );
-
- // convert to lags
- Abc_AigForEachAnd( pNtk, pNode, i )
- Vec_StrWriteEntry( p->vLagsMap, i, (char)Abc_NodeGetLag(Abc_NodeReadLValue(pNode), FiBest) );
-/*
- printf( "LValues : " );
- Abc_AigForEachAnd( pNtk, pNode, i )
- printf( "%d=%d ", i, Abc_NodeReadLValue(pNode) );
- printf( "\n" );
- printf( "Lags : " );
- Abc_AigForEachAnd( pNtk, pNode, i )
- if ( Vec_StrEntry(vLags,i) != 0 )
- printf( "%d=%d(%d)(%d) ", i, Vec_StrEntry(vLags,i), Abc_NodeReadLValue(pNode), Abc_NodeReadLValue(pNode) - FiBest * Vec_StrEntry(vLags,i) );
- printf( "\n" );
-*/
- Abc_NtkFpgaCollect( p );
-
- pNtk->pData = NULL;
-
- Cut_ManStop( p->pMan );
- p->pMan = NULL;
-}
-
-/**Function*************************************************************
-
- Synopsis [Performs binary search for the optimal clock period.]
-
- Description [Assumes that FiMin is infeasible while FiMax is feasible.]
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-int Abc_NtkFpgaRetimeSearch_rec( Seq_FpgaMan_t * p, Abc_Ntk_t * pNtk, int FiMin, int FiMax, int fVerbose )
-{
- int Median;
- assert( FiMin < FiMax );
- if ( FiMin + 1 == FiMax )
- return FiMax;
- Median = FiMin + (FiMax - FiMin)/2;
- if ( Abc_NtkFpgaRetimeForPeriod( p, pNtk, Median, fVerbose ) )
- return Abc_NtkFpgaRetimeSearch_rec( p, pNtk, FiMin, Median, fVerbose ); // Median is feasible
- else
- return Abc_NtkFpgaRetimeSearch_rec( p, pNtk, Median, FiMax, fVerbose ); // Median is infeasible
-}
-
-/**Function*************************************************************
-
- Synopsis [Returns 1 if retiming with this clock period is feasible.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-int Abc_NtkFpgaRetimeForPeriod( Seq_FpgaMan_t * p, Abc_Ntk_t * pNtk, int Fi, int fVerbose )
-{
- Abc_Obj_t * pObj;
- int i, c, RetValue, fChange, Counter;
- char * pReason = "";
-
- // set l-values of all nodes to be minus infinity
- Vec_IntFill( p->vArrivals, Abc_NtkObjNumMax(pNtk), -ABC_INFINITY );
- Vec_PtrFill( p->vBestCuts, Abc_NtkObjNumMax(pNtk), NULL );
-
- // set l-values for the constant and PIs
- pObj = Abc_NtkObj( pNtk, 0 );
- Abc_NodeSetLValue( pObj, 0 );
- Abc_NtkForEachPi( pNtk, pObj, i )
- Abc_NodeSetLValue( pObj, 0 );
-
- // update all values iteratively
- Counter = 0;
- for ( c = 0; c < 20; c++ )
- {
- fChange = 0;
- Abc_NtkForEachObj( pNtk, pObj, i )
- {
- if ( Abc_ObjIsPi(pObj) )
- continue;
- if ( Abc_ObjFaninNum(pObj) == 0 )
- continue;
- RetValue = Abc_NodeFpgaUpdateLValue( p, pObj, Fi );
- Counter++;
- if ( RetValue == ABC_FPGA_UPDATE_FAIL )
- break;
- if ( RetValue == ABC_FPGA_UPDATE_NO )
- continue;
- fChange = 1;
- }
- if ( RetValue == ABC_FPGA_UPDATE_FAIL )
- break;
- if ( fChange == 0 )
- break;
- }
- if ( c == 20 )
- {
- RetValue = ABC_FPGA_UPDATE_FAIL;
- pReason = "(timeout)";
- }
-
- // report the results
- if ( fVerbose )
- {
- if ( RetValue == ABC_FPGA_UPDATE_FAIL )
- printf( "Period = %3d. Iterations = %3d. Updates = %6d. Infeasible %s\n", Fi, c, Counter, pReason );
- else
- printf( "Period = %3d. Iterations = %3d. Updates = %6d. Feasible\n", Fi, c, Counter );
- }
- return RetValue != ABC_FPGA_UPDATE_FAIL;
-}
-
-/**Function*************************************************************
-
- Synopsis [Computes the l-value of the node.]
-
- Description [The node can be internal or a PO.]
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-int Abc_NodeFpgaUpdateLValue( Seq_FpgaMan_t * p, Abc_Obj_t * pObj, int Fi )
-{
- Abc_Obj_t * pFanin;
- Cut_Cut_t * pList, * pCut, * pCutBest;
- int lValueNew, lValueOld, lValueCur, lValueFan;
- int i;
-
- assert( !Abc_ObjIsPi(pObj) );
- assert( Abc_ObjFaninNum(pObj) > 0 );
-
- if ( Abc_ObjIsPo(pObj) )
- {
- lValueOld = Abc_NodeReadLValue(Abc_ObjFanin0(pObj));
- lValueNew = lValueOld - Fi * Abc_ObjFaninL0(pObj);
- return (lValueNew > Fi)? ABC_FPGA_UPDATE_FAIL : ABC_FPGA_UPDATE_NO;
- }
-
- pCutBest = NULL;
- lValueNew = ABC_INFINITY;
- pList = Abc_NodeReadCuts( p->pMan, pObj );
- for ( pCut = pList; pCut; pCut = pCut->pNext )
- {
- if ( pCut->nLeaves < 2 )
- continue;
- lValueCur = -ABC_INFINITY;
- for ( i = 0; i < (int)pCut->nLeaves; i++ )
- {
- pFanin = Abc_NtkObj( pObj->pNtk, (pCut->pLeaves[i] >> CUT_SHIFT) );
- lValueFan = Abc_NodeReadLValue(pFanin) - Fi * (pCut->pLeaves[i] & CUT_MASK);
- lValueCur = ABC_MAX( lValueCur, lValueFan );
- }
- lValueCur += 1;
- lValueNew = ABC_MIN( lValueNew, lValueCur );
- if ( lValueNew == lValueCur )
- pCutBest = pCut;
- }
-
- lValueOld = Abc_NodeReadLValue(pObj);
-// if ( lValueNew == lValueOld )
- if ( lValueNew <= lValueOld )
- return ABC_FPGA_UPDATE_NO;
-
- Abc_NodeSetLValue( pObj, lValueNew );
- Vec_PtrWriteEntry( p->vBestCuts, pObj->Id, pCutBest );
- return ABC_FPGA_UPDATE_YES;
-}
-
-
-
-/**Function*************************************************************
-
- Synopsis [Select nodes visible in the mapping.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Abc_NodeFpgaCollect_rec( Seq_FpgaMan_t * p, Abc_Obj_t * pNode )
-{
- Cut_Cut_t * pCutBest;
- Abc_Obj_t * pFanin;
- Vec_Int_t * vLeaves;
- int i;
- // skip the CI
- if ( Abc_ObjIsCi(pNode) )
- return;
- // if this node is already visited, skip
- if ( Abc_NodeIsTravIdCurrent( pNode ) )
- return;
- // mark the node as visited
- Abc_NodeSetTravIdCurrent( pNode );
- // get the best cut of the node
- pCutBest = Vec_PtrEntry( p->vBestCuts, pNode->Id );
- for ( i = 0; i < (int)pCutBest->nLeaves; i++ )
- {
- pFanin = Abc_NtkObj( pNode->pNtk, (pCutBest->pLeaves[i] >> CUT_SHIFT) );
- Abc_NodeFpgaCollect_rec( p, pFanin );
- }
- // collect the node and its cut
- vLeaves = Vec_IntAlloc( pCutBest->nLeaves );
- for ( i = 0; i < (int)pCutBest->nLeaves; i++ )
- Vec_IntPush( vLeaves, pCutBest->pLeaves[i] );
- Vec_PtrPush( p->vMapCuts, vLeaves );
- Vec_PtrPush( p->vMapping, pNode );
-}
-
-/**Function*************************************************************
-
- Synopsis [Select nodes visible in the mapping.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Abc_NtkFpgaCollect( Seq_FpgaMan_t * p )
-{
- Abc_Ntk_t * pNtk = p->pNtk;
- Abc_Obj_t * pObj;
- int i;
- Vec_PtrClear( p->vMapping );
- Vec_PtrClear( p->vMapCuts );
- Abc_NtkIncrementTravId( pNtk );
- Abc_NtkForEachPo( pNtk, pObj, i )
- Abc_NodeFpgaCollect_rec( p, Abc_ObjFanin0(pObj) );
-}
-
-
-////////////////////////////////////////////////////////////////////////
-/// END OF FILE ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/src/base/abcs/abcFpgaSeq.c b/src/base/abcs/abcFpgaSeq.c
deleted file mode 100644
index 2fff1b14..00000000
--- a/src/base/abcs/abcFpgaSeq.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/**CFile****************************************************************
-
- FileName [abcFpgaSeq.c]
-
- SystemName [ABC: Logic synthesis and verification system.]
-
- PackageName [Network and node package.]
-
- Synopsis [Mapping for FPGAs using sequential cuts.]
-
- Author [Alan Mishchenko]
-
- Affiliation [UC Berkeley]
-
- Date [Ver. 1.0. Started - June 20, 2005.]
-
- Revision [$Id: abcFpgaSeq.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "abcs.h"
-
-////////////////////////////////////////////////////////////////////////
-/// DECLARATIONS ///
-////////////////////////////////////////////////////////////////////////
-
-Abc_Ntk_t * Abc_NtkMapSeq( Abc_Ntk_t * pNtk, int fVerbose ) { return 0; }
-
-extern Cut_Man_t * Abc_NtkSeqCuts( Abc_Ntk_t * pNtk, Cut_Params_t * pParams );
-extern void Abc_NtkFpgaSeqRetimeDelayLags( Seq_FpgaMan_t * p );
-
-static Seq_FpgaMan_t * Abc_NtkFpgaSeqStart( Abc_Ntk_t * pNtk, int fVerbose );
-static void Abc_NtkFpgaSeqStop( Seq_FpgaMan_t * p );
-
-static Abc_Ntk_t * Abc_NtkFpgaSeqConstruct( Seq_FpgaMan_t * p );
-static void Abc_NtkFpgaSeqRetime( Seq_FpgaMan_t * p, Abc_Ntk_t * pNtkNew );
-
-////////////////////////////////////////////////////////////////////////
-/// FUNCTION DEFINITIONS ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
- Synopsis [Retimes AIG for optimal delay.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-Abc_Ntk_t * Abc_NtkFpgaSeq( Abc_Ntk_t * pNtk, int fVerbose )
-{
- Abc_Ntk_t * pNtkNew;
- Seq_FpgaMan_t * p;
- Cut_Params_t Params, * pParams = &Params;
- int clk;
-
- assert( Abc_NtkIsSeq( pNtk ) );
-
- // get the sequential FPGA manager
- p = Abc_NtkFpgaSeqStart( pNtk, fVerbose );
-
- // create the cuts
- memset( pParams, 0, sizeof(Cut_Params_t) );
- pParams->nVarsMax = 5; // the max cut size ("k" of the k-feasible cuts)
- pParams->nKeepMax = 1000; // the max number of cuts kept at a node
- pParams->fTruth = 0; // compute truth tables
- pParams->fFilter = 1; // filter dominated cuts
- pParams->fSeq = 1; // compute sequential cuts
- pParams->fVerbose = 0; // the verbosiness flag
-
-clk = clock();
- p->pMan = Abc_NtkSeqCuts( pNtk, pParams );
-p->timeCuts += clock() - clk;
-
- // find best arrival times (p->vArrivals) and free the cuts
- // select mapping (p->vMapping) and remember best cuts (p->vMapCuts)
-clk = clock();
- Abc_NtkFpgaSeqRetimeDelayLags( p );
-p->timeDelay += clock() - clk;
-
-return NULL;
-
- // construct the network
-clk = clock();
- pNtkNew = Abc_NtkFpgaSeqConstruct( p );
-p->timeNtk += clock() - clk;
-
- // retime the network
-clk = clock();
- Abc_NtkFpgaSeqRetime( p, pNtkNew );
-p->timeRet += clock() - clk;
-
- // remove temporaries
- Abc_NtkFpgaSeqStop( p );
-
- // check the resulting network
- if ( !Abc_NtkCheck( pNtkNew ) )
- fprintf( stdout, "Abc_NtkFpgaSeq(): Network check has failed.\n" );
- return pNtkNew;
-}
-
-/**Function*************************************************************
-
- Synopsis [Starts sequential FPGA mapper.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-Seq_FpgaMan_t * Abc_NtkFpgaSeqStart( Abc_Ntk_t * pNtk, int fVerbose )
-{
- Seq_FpgaMan_t * p;
- // create the FPGA mapping manager
- p = ALLOC( Seq_FpgaMan_t, 1 );
- memset( p, 0, sizeof(Seq_FpgaMan_t) );
- p->pNtk = pNtk;
- p->pMan = NULL;
- p->vArrivals = Vec_IntAlloc( 0 );
- p->vBestCuts = Vec_PtrAlloc( 0 );
- p->vMapping = Vec_PtrAlloc( 0 );
- p->vMapCuts = Vec_PtrAlloc( 0 );
- p->vLagsMap = Vec_StrStart( Abc_NtkObjNumMax(pNtk) );
- p->fVerbose = fVerbose;
- return p;
-}
-
-/**Function*************************************************************
-
- Synopsis [Stops sequential FPGA mapper.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Abc_NtkFpgaSeqStop( Seq_FpgaMan_t * p )
-{
- if ( p->fVerbose )
- {
- printf( "Sequential FPGA mapping stats:\n" );
-// printf( "Total allocated = %8d.\n", p->nCutsAlloc );
-// printf( "Cuts per node = %8.1f\n", ((float)(p->nCutsCur-p->nCutsTriv))/p->nNodes );
- PRT( "Cuts ", p->timeCuts );
- PRT( "Arrival", p->timeDelay );
- PRT( "Network", p->timeNtk );
- PRT( "Retime ", p->timeRet );
- }
- Vec_IntFree( p->vArrivals );
- Vec_PtrFree( p->vBestCuts );
- Vec_PtrFree( p->vMapping );
- Vec_VecFree( (Vec_Vec_t *)p->vMapCuts );
- Vec_StrFree( p->vLagsMap );
- free( p );
-}
-
-
-/**Function*************************************************************
-
- Synopsis [Construct the final network after mapping.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-Abc_Ntk_t * Abc_NtkFpgaSeqConstruct( Seq_FpgaMan_t * p )
-{
- Abc_Ntk_t * pNtk = NULL;
- return pNtk;
-}
-
-/**Function*************************************************************
-
- Synopsis [Retimes the final network after mapping.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Abc_NtkFpgaSeqRetime( Seq_FpgaMan_t * p, Abc_Ntk_t * pNtkNew )
-{
-}
-
-////////////////////////////////////////////////////////////////////////
-/// END OF FILE ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/src/base/abcs/abcRetCore.c b/src/base/abcs/abcRetCore.c
deleted file mode 100644
index f6d26e0d..00000000
--- a/src/base/abcs/abcRetCore.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/**CFile****************************************************************
-
- FileName [abcForBack.c]
-
- SystemName [ABC: Logic synthesis and verification system.]
-
- PackageName [Network and node package.]
-
- Synopsis [Simple forward/backward retiming procedures.]
-
- Author [Alan Mishchenko]
-
- Affiliation [UC Berkeley]
-
- Date [Ver. 1.0. Started - June 20, 2005.]
-
- Revision [$Id: abcForBack.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "abcs.h"
-
-////////////////////////////////////////////////////////////////////////
-/// DECLARATIONS ///
-////////////////////////////////////////////////////////////////////////
-
-/*
- Retiming can be represented in three equivalent forms:
- - as a set of integer lags for each node (array of chars by node ID)
- - as a set of node numbers with lag for each, fwd and bwd (two arrays of Abc_RetStep_t_)
- - as a set of node moves, fwd and bwd (two arrays arrays of Abc_Obj_t *)
-*/
-
-////////////////////////////////////////////////////////////////////////
-/// FUNCTION DEFINITIONS ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
- Synopsis [Performs most forward retiming.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Abc_NtkSeqRetimeForward( Abc_Ntk_t * pNtk, int fVerbose )
-{
- Vec_Ptr_t * vMoves;
- Abc_Obj_t * pNode;
- int i;
- // get the forward moves
- vMoves = Abc_NtkUtilRetimingTry( pNtk, 1 );
- // undo the forward moves
- Vec_PtrForEachEntryReverse( vMoves, pNode, i )
- Abc_ObjRetimeBackwardTry( pNode, 1 );
- // implement this forward retiming
- Abc_NtkImplementRetimingForward( pNtk, vMoves );
- Vec_PtrFree( vMoves );
-}
-
-/**Function*************************************************************
-
- Synopsis [Performs most backward retiming.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Abc_NtkSeqRetimeBackward( Abc_Ntk_t * pNtk, int fVerbose )
-{
- Vec_Ptr_t * vMoves;
- Abc_Obj_t * pNode;
- int i, RetValue;
- // get the backward moves
- vMoves = Abc_NtkUtilRetimingTry( pNtk, 0 );
- // undo the backward moves
- Vec_PtrForEachEntryReverse( vMoves, pNode, i )
- Abc_ObjRetimeForwardTry( pNode, 1 );
- // implement this backward retiming
- RetValue = Abc_NtkImplementRetimingBackward( pNtk, vMoves, fVerbose );
- Vec_PtrFree( vMoves );
- if ( RetValue == 0 )
- printf( "Retiming completed but initial state computation has failed.\n" );
-}
-
-/**Function*************************************************************
-
- Synopsis [Performs performs optimal delay retiming.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Abc_NtkSeqRetimeDelay( Abc_Ntk_t * pNtk, int fVerbose )
-{
- Vec_Str_t * vLags;
- int RetValue;
- // get the retiming vector
- vLags = Abc_NtkSeqRetimeDelayLags( pNtk, fVerbose );
- // implement this retiming
- RetValue = Abc_NtkImplementRetiming( pNtk, vLags, fVerbose );
- Vec_StrFree( vLags );
- if ( RetValue == 0 )
- printf( "Retiming completed but initial state computation has failed.\n" );
-}
-
-/**Function*************************************************************
-
- Synopsis [Performs retiming for initial state computation.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Abc_NtkSeqRetimeInitial( Abc_Ntk_t * pNtk, int fVerbose )
-{
- Vec_Str_t * vLags;
- int RetValue;
- // get the retiming vector
- vLags = Abc_NtkSeqRetimeDelayLags( pNtk, fVerbose );
- // implement this retiming
- RetValue = Abc_NtkImplementRetiming( pNtk, vLags, fVerbose );
- Vec_StrFree( vLags );
- if ( RetValue == 0 )
- printf( "Retiming completed but initial state computation has failed.\n" );
-}
-
-
-////////////////////////////////////////////////////////////////////////
-/// END OF FILE ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/src/base/abcs/abcRetDelay.c b/src/base/abcs/abcRetDelay.c
deleted file mode 100644
index 15138510..00000000
--- a/src/base/abcs/abcRetDelay.c
+++ /dev/null
@@ -1,504 +0,0 @@
-/**CFile****************************************************************
-
- FileName [abcSeqRetime.c]
-
- SystemName [ABC: Logic synthesis and verification system.]
-
- PackageName [Network and node package.]
-
- Synopsis [Peforms retiming for optimal clock cycle.]
-
- Author [Alan Mishchenko]
-
- Affiliation [UC Berkeley]
-
- Date [Ver. 1.0. Started - June 20, 2005.]
-
- Revision [$Id: abcSeqRetime.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "abcs.h"
-
-////////////////////////////////////////////////////////////////////////
-/// DECLARATIONS ///
-////////////////////////////////////////////////////////////////////////
-
-// the internal procedures
-static int Abc_NtkRetimeSearch_rec( Abc_Ntk_t * pNtk, int FiMin, int FiMax, int fVerbose );
-static int Abc_NtkRetimeForPeriod( Abc_Ntk_t * pNtk, int Fi, int fVerbose );
-static int Abc_NodeUpdateLValue( Abc_Obj_t * pObj, int Fi );
-
-// node status after updating its arrival time
-enum { ABC_UPDATE_FAIL, ABC_UPDATE_NO, ABC_UPDATE_YES };
-
-static void Abc_RetimingExperiment( Abc_Ntk_t * pNtk, Vec_Str_t * vLags );
-
-////////////////////////////////////////////////////////////////////////
-/// FUNCTION DEFINITIONS ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
- Synopsis [Retimes AIG for optimal delay.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-Vec_Str_t * Abc_NtkSeqRetimeDelayLags( Abc_Ntk_t * pNtk, int fVerbose )
-{
- Vec_Str_t * vLags;
- Abc_Obj_t * pNode;
- int i, FiMax, FiBest, RetValue;
- assert( Abc_NtkIsSeq( pNtk ) );
-
- // start storage for sequential arrival times
- assert( pNtk->pData == NULL );
- pNtk->pData = Vec_IntAlloc( 0 );
-
- // get the upper bound on the clock period
-// FiMax = Abc_NtkNodeNum(pNtk);
- FiMax = 0;
- Abc_AigForEachAnd( pNtk, pNode, i )
- if ( FiMax < (int)pNode->Level )
- FiMax = pNode->Level;
- FiMax += 2;
-
- // make sure this clock period is feasible
- assert( Abc_NtkRetimeForPeriod( pNtk, FiMax, fVerbose ) );
-
- // search for the optimal clock period between 0 and nLevelMax
- FiBest = Abc_NtkRetimeSearch_rec( pNtk, 0, FiMax, fVerbose );
-
- // recompute the best LValues
- RetValue = Abc_NtkRetimeForPeriod( pNtk, FiBest, fVerbose );
- assert( RetValue );
-
- // print the result
- if ( fVerbose )
- printf( "The best clock period is %3d.\n", FiBest );
-
- // convert to lags
- vLags = Vec_StrStart( Abc_NtkObjNumMax(pNtk) );
- Abc_AigForEachAnd( pNtk, pNode, i )
- Vec_StrWriteEntry( vLags, i, (char)Abc_NodeGetLag(Abc_NodeReadLValue(pNode), FiBest) );
-/*
- printf( "LValues : " );
- Abc_AigForEachAnd( pNtk, pNode, i )
- printf( "%d=%d ", i, Abc_NodeReadLValue(pNode) );
- printf( "\n" );
- printf( "Lags : " );
- Abc_AigForEachAnd( pNtk, pNode, i )
- if ( Vec_StrEntry(vLags,i) != 0 )
- printf( "%d=%d(%d)(%d) ", i, Vec_StrEntry(vLags,i), Abc_NodeReadLValue(pNode), Abc_NodeReadLValue(pNode) - FiBest * Vec_StrEntry(vLags,i) );
- printf( "\n" );
-*/
-
- // free storage
- Vec_IntFree( pNtk->pData );
- pNtk->pData = NULL;
- return vLags;
-}
-
-/**Function*************************************************************
-
- Synopsis [Performs binary search for the optimal clock period.]
-
- Description [Assumes that FiMin is infeasible while FiMax is feasible.]
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-int Abc_NtkRetimeSearch_rec( Abc_Ntk_t * pNtk, int FiMin, int FiMax, int fVerbose )
-{
- int Median;
- assert( FiMin < FiMax );
- if ( FiMin + 1 == FiMax )
- return FiMax;
- Median = FiMin + (FiMax - FiMin)/2;
- if ( Abc_NtkRetimeForPeriod( pNtk, Median, fVerbose ) )
- return Abc_NtkRetimeSearch_rec( pNtk, FiMin, Median, fVerbose ); // Median is feasible
- else
- return Abc_NtkRetimeSearch_rec( pNtk, Median, FiMax, fVerbose ); // Median is infeasible
-}
-
-/**Function*************************************************************
-
- Synopsis [Returns 1 if retiming with this clock period is feasible.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-int Abc_NtkRetimeForPeriod2( Abc_Ntk_t * pNtk, int Fi )
-{
- Vec_Ptr_t * vFrontier;
- Abc_Obj_t * pObj, * pFanout;
- char * pReason = "";
- int RetValue, i, k;
- int Limit;
-
- // set l-values of all nodes to be minus infinity
- Vec_IntFill( pNtk->pData, Abc_NtkObjNumMax(pNtk), -ABC_INFINITY );
-
- // start the frontier by setting PI l-values to 0 and including PI fanouts
- vFrontier = Vec_PtrAlloc( 100 );
- pObj = Abc_NtkObj( pNtk, 0 );
- if ( Abc_ObjFanoutNum(pObj) > 0 )
- {
- Abc_NodeSetLValue( pObj, 0 );
- Abc_ObjForEachFanout( pObj, pFanout, k )
- if ( pFanout->fMarkA == 0 )
- {
- Vec_PtrPush( vFrontier, pFanout );
- pFanout->fMarkA = 1;
- }
- }
- Abc_NtkForEachPi( pNtk, pObj, i )
- {
- Abc_NodeSetLValue( pObj, 0 );
- Abc_ObjForEachFanout( pObj, pFanout, k )
- if ( pFanout->fMarkA == 0 )
- {
- Vec_PtrPush( vFrontier, pFanout );
- pFanout->fMarkA = 1;
- }
- }
-
- // iterate until convergence
- Limit = Abc_NtkObjNumMax(pNtk) * 20;
- Vec_PtrForEachEntry( vFrontier, pObj, i )
- {
- pObj->fMarkA = 0;
- RetValue = Abc_NodeUpdateLValue( pObj, Fi );
- if ( RetValue == ABC_UPDATE_FAIL )
- break;
- if ( i == Limit )
- {
- RetValue = ABC_UPDATE_FAIL;
- pReason = "(timeout)";
- break;
- }
- if ( RetValue == ABC_UPDATE_NO )
- continue;
- assert( RetValue == ABC_UPDATE_YES );
- // arrival times have changed - add fanouts to the frontier
- Abc_ObjForEachFanout( pObj, pFanout, k )
- if ( pFanout->fMarkA == 0 && pFanout != pObj )
- {
- Vec_PtrPush( vFrontier, pFanout );
- pFanout->fMarkA = 1;
- }
- }
- // clean the nodes
- Vec_PtrForEachEntryStart( vFrontier, pObj, k, i )
- pObj->fMarkA = 0;
-
- // report the results
- if ( RetValue == ABC_UPDATE_FAIL )
- printf( "Period = %3d. Updated nodes = %6d. Infeasible %s\n", Fi, vFrontier->nSize, pReason );
- else
- printf( "Period = %3d. Updated nodes = %6d. Feasible\n", Fi, vFrontier->nSize );
- Vec_PtrFree( vFrontier );
- return RetValue != ABC_UPDATE_FAIL;
-}
-
-/**Function*************************************************************
-
- Synopsis [Returns 1 if retiming with this clock period is feasible.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-int Abc_NtkRetimeForPeriod( Abc_Ntk_t * pNtk, int Fi, int fVerbose )
-{
- Abc_Obj_t * pObj;
- int i, c, RetValue, fChange, Counter;
- char * pReason = "";
-
- // set l-values of all nodes to be minus infinity
- Vec_IntFill( pNtk->pData, Abc_NtkObjNumMax(pNtk), -ABC_INFINITY );
-
- // set l-values for the constant and PIs
- pObj = Abc_NtkObj( pNtk, 0 );
- Abc_NodeSetLValue( pObj, 0 );
- Abc_NtkForEachPi( pNtk, pObj, i )
- Abc_NodeSetLValue( pObj, 0 );
-
- // update all values iteratively
- Counter = 0;
- for ( c = 0; c < 20; c++ )
- {
- fChange = 0;
- Abc_NtkForEachObj( pNtk, pObj, i )
- {
- if ( Abc_ObjIsPi(pObj) )
- continue;
- if ( Abc_ObjFaninNum(pObj) == 0 )
- continue;
- RetValue = Abc_NodeUpdateLValue( pObj, Fi );
- Counter++;
- if ( RetValue == ABC_UPDATE_FAIL )
- break;
- if ( RetValue == ABC_UPDATE_NO )
- continue;
- fChange = 1;
- }
- if ( RetValue == ABC_UPDATE_FAIL )
- break;
- if ( fChange == 0 )
- break;
- }
- if ( c == 20 )
- {
- RetValue = ABC_UPDATE_FAIL;
- pReason = "(timeout)";
- }
-
- // report the results
- if ( fVerbose )
- {
- if ( RetValue == ABC_UPDATE_FAIL )
- printf( "Period = %3d. Iterations = %3d. Updates = %6d. Infeasible %s\n", Fi, c, Counter, pReason );
- else
- printf( "Period = %3d. Iterations = %3d. Updates = %6d. Feasible\n", Fi, c, Counter );
- }
- return RetValue != ABC_UPDATE_FAIL;
-}
-
-/**Function*************************************************************
-
- Synopsis [Computes the l-value of the node.]
-
- Description [The node can be internal or a PO.]
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-int Abc_NodeUpdateLValue( Abc_Obj_t * pObj, int Fi )
-{
- int lValueNew, lValueOld, lValue0, lValue1;
- assert( !Abc_ObjIsPi(pObj) );
- assert( Abc_ObjFaninNum(pObj) > 0 );
- lValue0 = Abc_NodeReadLValue(Abc_ObjFanin0(pObj)) - Fi * Abc_ObjFaninL0(pObj);
- if ( Abc_ObjIsPo(pObj) )
- return (lValue0 > Fi)? ABC_UPDATE_FAIL : ABC_UPDATE_NO;
- if ( Abc_ObjFaninNum(pObj) == 2 )
- lValue1 = Abc_NodeReadLValue(Abc_ObjFanin1(pObj)) - Fi * Abc_ObjFaninL1(pObj);
- else
- lValue1 = -ABC_INFINITY;
- lValueNew = 1 + ABC_MAX( lValue0, lValue1 );
- lValueOld = Abc_NodeReadLValue(pObj);
-// if ( lValueNew == lValueOld )
- if ( lValueNew <= lValueOld )
- return ABC_UPDATE_NO;
- Abc_NodeSetLValue( pObj, lValueNew );
- return ABC_UPDATE_YES;
-}
-
-
-
-
-
-/**Function*************************************************************
-
- Synopsis []
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-int Abc_RetimingPrint_rec( Abc_Obj_t * pObj )
-{
- Abc_Obj_t * pFanin0, * pFanin1;
- int Depth0, Depth1;
-
- if ( Abc_ObjIsPi(pObj) )
- {
- printf( "%d -> ", pObj->Id );
- return 0;
- }
-
- pFanin0 = Abc_ObjFanin0(pObj);
- pFanin1 = Abc_ObjFanin1(pObj);
-
- if ( Abc_ObjFaninL0(pObj) == 0 && Abc_ObjFaninL1(pObj) > 0 )
- Abc_RetimingPrint_rec( pFanin0 );
- else if ( Abc_ObjFaninL1(pObj) == 0 && Abc_ObjFaninL0(pObj) > 0 )
- Abc_RetimingPrint_rec( pFanin1 );
- else if ( Abc_ObjFaninL0(pObj) == 0 && Abc_ObjFaninL1(pObj) == 0 )
- {
- Depth0 = (int)pFanin0->pCopy;
- Depth1 = (int)pFanin1->pCopy;
-
- if ( Depth0 > Depth1 )
- Abc_RetimingPrint_rec( pFanin0 );
- else
- Abc_RetimingPrint_rec( pFanin1 );
- }
-
- printf( "%d (%d) -> ", pObj->Id, (int)pObj->pCopy );
- return 0;
-}
-
-/**Function*************************************************************
-
- Synopsis []
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-int Abc_Retiming_rec( Abc_Obj_t * pObj )
-{
- int Depth0, Depth1, Depth;
- if ( Abc_ObjIsPi(pObj) )
- {
- pObj->pCopy = 0;
- return 0;
- }
- // if this node is already visited, skip
- if ( Abc_NodeIsTravIdCurrent( pObj ) )
- return (int)pObj->pCopy;
- // mark the node as visited
- Abc_NodeSetTravIdCurrent( pObj );
- if ( Abc_ObjFaninL0(pObj) == 0 )
- Depth0 = Abc_Retiming_rec( Abc_ObjFanin0(pObj) );
- else
- Depth0 = 0;
- if ( Abc_ObjFaninL1(pObj) == 0 )
- Depth1 = Abc_Retiming_rec( Abc_ObjFanin1(pObj) );
- else
- Depth1 = 0;
- Depth = 1 + ABC_MAX( Depth0, Depth1 );
- pObj->pCopy = (void *)Depth;
- return Depth;
-}
-
-/**Function*************************************************************
-
- Synopsis []
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-int Abc_NtkRetiming( Abc_Ntk_t * pNtk )
-{
- Abc_Obj_t * pObj;
- int i, Depth;
- Abc_NtkForEachObj( pNtk, pObj, i )
- {
- if ( Abc_ObjFaninNum(pObj) != 2 )
- continue;
- if ( Abc_ObjFaninL0(pObj) > 0 )
- {
- Abc_NtkIncrementTravId(pNtk);
- Depth = Abc_Retiming_rec( Abc_ObjFanin0(pObj) );
- if ( Depth > 30 )
- {
- printf( "Depth is %d. ", Depth );
- Abc_RetimingPrint_rec( Abc_ObjFanin0(pObj) );
- printf( "\n\n" );
- }
- }
- if ( Abc_ObjFaninL1(pObj) > 0 )
- {
- Abc_NtkIncrementTravId(pNtk);
- Depth = Abc_Retiming_rec( Abc_ObjFanin1(pObj) );
- if ( Depth > 30 )
- {
- printf( "Depth is %d. ", Depth );
- Abc_RetimingPrint_rec( Abc_ObjFanin1(pObj) );
- printf( "\n\n" );
- }
- }
- }
- return 0;
-}
-
-/**Function*************************************************************
-
- Synopsis []
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Abc_RetimingExperiment( Abc_Ntk_t * pNtk, Vec_Str_t * vLags )
-{
- Abc_Obj_t * pObj;
- char Lag;
- int i;
-
- Vec_StrForEachEntry( vLags, Lag, i )
- {
- if ( Lag == 0 )
- continue;
- pObj = Abc_NtkObj( pNtk, i );
- if ( Lag < 0 )
- Abc_ObjRetimeForwardTry( pObj, -Lag );
- else
- Abc_ObjRetimeBackwardTry( pObj, Lag );
- }
-
- // make sure there are no negative latches
- Abc_NtkForEachObj( pNtk, pObj, i )
- {
- if ( Abc_ObjFaninNum(pObj) == 0 )
- continue;
- assert( Abc_ObjFaninL0(pObj) >= 0 );
- if ( Abc_ObjFaninNum(pObj) == 1 )
- continue;
- assert( Abc_ObjFaninL1(pObj) >= 0 );
-// printf( "%d=(%d,%d) ", i, Abc_ObjFaninL0(pObj), Abc_ObjFaninL1(pObj) );
- }
-// printf( "\n" );
-
- Abc_NtkRetiming( pNtk );
-
- Vec_StrForEachEntry( vLags, Lag, i )
- {
- if ( Lag == 0 )
- continue;
- pObj = Abc_NtkObj( pNtk, i );
- if ( Lag < 0 )
- Abc_ObjRetimeBackwardTry( pObj, -Lag );
- else
- Abc_ObjRetimeForwardTry( pObj, Lag );
- }
-
-// Abc_NtkSeqRetimeDelayLags( pNtk );
-}
-
-////////////////////////////////////////////////////////////////////////
-/// END OF FILE ///
-////////////////////////////////////////////////////////////////////////
-
diff --git a/src/base/abcs/abcRetImpl.c b/src/base/abcs/abcRetImpl.c
deleted file mode 100644
index 07e6d24e..00000000
--- a/src/base/abcs/abcRetImpl.c
+++ /dev/null
@@ -1,450 +0,0 @@
-/**CFile****************************************************************
-
- FileName [abcRetImpl.c]
-
- SystemName [ABC: Logic synthesis and verification system.]
-
- PackageName [Network and node package.]
-
- Synopsis [Implementation of retiming.]
-
- Author [Alan Mishchenko]
-
- Affiliation [UC Berkeley]
-
- Date [Ver. 1.0. Started - June 20, 2005.]
-
- Revision [$Id: abcRetImpl.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "abcs.h"
-
-////////////////////////////////////////////////////////////////////////
-/// DECLARATIONS ///
-////////////////////////////////////////////////////////////////////////
-
-static void Abc_ObjRetimeForward( Abc_Obj_t * pObj );
-static int Abc_ObjRetimeBackward( Abc_Obj_t * pObj, Abc_Ntk_t * pNtk, stmm_table * tTable, Vec_Int_t * vValues );
-static void Abc_ObjRetimeBackwardUpdateEdge( Abc_Obj_t * pObj, int Edge, stmm_table * tTable );
-static void Abc_NtkRetimeSetInitialValues( Abc_Ntk_t * pNtk, stmm_table * tTable, int * pModel );
-
-////////////////////////////////////////////////////////////////////////
-/// FUNCTION DEFINITIONS ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
- Synopsis [Implements the retiming on the sequential AIG.]
-
- Description [Split the retiming into forward and backward.]
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-int Abc_NtkImplementRetiming( Abc_Ntk_t * pNtk, Vec_Str_t * vLags, int fVerbose )
-{
- Vec_Int_t * vSteps;
- Vec_Ptr_t * vMoves;
- int RetValue;
-
- // forward retiming
- vSteps = Abc_NtkUtilRetimingSplit( vLags, 1 );
- // translate each set of steps into moves
- if ( fVerbose )
- printf( "The number of forward steps = %6d.\n", Vec_IntSize(vSteps) );
- vMoves = Abc_NtkUtilRetimingGetMoves( pNtk, vSteps, 1 );
- if ( fVerbose )
- printf( "The number of forward moves = %6d.\n", Vec_PtrSize(vMoves) );
- // implement this retiming
- Abc_NtkImplementRetimingForward( pNtk, vMoves );
- Vec_IntFree( vSteps );
- Vec_PtrFree( vMoves );
-
- // backward retiming
- vSteps = Abc_NtkUtilRetimingSplit( vLags, 0 );
- // translate each set of steps into moves
- if ( fVerbose )
- printf( "The number of backward steps = %6d.\n", Vec_IntSize(vSteps) );
- vMoves = Abc_NtkUtilRetimingGetMoves( pNtk, vSteps, 0 );
- if ( fVerbose )
- printf( "The number of backward moves = %6d.\n", Vec_PtrSize(vMoves) );
- // implement this retiming
- RetValue = Abc_NtkImplementRetimingBackward( pNtk, vMoves, fVerbose );
- Vec_IntFree( vSteps );
- Vec_PtrFree( vMoves );
- return RetValue;
-}
-
-/**Function*************************************************************
-
- Synopsis [Implements the given retiming on the sequential AIG.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Abc_NtkImplementRetimingForward( Abc_Ntk_t * pNtk, Vec_Ptr_t * vMoves )
-{
- Abc_Obj_t * pNode;
- int i;
- Vec_PtrForEachEntry( vMoves, pNode, i )
- Abc_ObjRetimeForward( pNode );
-}
-
-/**Function*************************************************************
-
- Synopsis [Retimes node forward by one latch.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Abc_ObjRetimeForward( Abc_Obj_t * pObj )
-{
- Abc_Obj_t * pFanout;
- int Init0, Init1, Init, i;
- assert( Abc_ObjFaninNum(pObj) == 2 );
- assert( Abc_ObjFaninL0(pObj) >= 1 );
- assert( Abc_ObjFaninL1(pObj) >= 1 );
- // remove the init values from the fanins
- Init0 = Abc_ObjFaninLDeleteFirst( pObj, 0 );
- Init1 = Abc_ObjFaninLDeleteFirst( pObj, 1 );
- assert( Init0 != ABC_INIT_NONE );
- assert( Init1 != ABC_INIT_NONE );
- // take into account the complements in the node
- if ( Abc_ObjFaninC0(pObj) )
- {
- if ( Init0 == ABC_INIT_ZERO )
- Init0 = ABC_INIT_ONE;
- else if ( Init0 == ABC_INIT_ONE )
- Init0 = ABC_INIT_ZERO;
- }
- if ( Abc_ObjFaninC1(pObj) )
- {
- if ( Init1 == ABC_INIT_ZERO )
- Init1 = ABC_INIT_ONE;
- else if ( Init1 == ABC_INIT_ONE )
- Init1 = ABC_INIT_ZERO;
- }
- // compute the value at the output of the node
- if ( Init0 == ABC_INIT_ZERO || Init1 == ABC_INIT_ZERO )
- Init = ABC_INIT_ZERO;
- else if ( Init0 == ABC_INIT_ONE && Init1 == ABC_INIT_ONE )
- Init = ABC_INIT_ONE;
- else
- Init = ABC_INIT_DC;
- // add the init values to the fanouts
- Abc_ObjForEachFanout( pObj, pFanout, i )
- Abc_ObjFaninLInsertLast( pFanout, Abc_ObjEdgeNum(pObj, pFanout), Init );
-}
-
-
-
-/**Function*************************************************************
-
- Synopsis [Implements the given retiming on the sequential AIG.]
-
- Description [Returns 0 of initial state computation fails.]
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-int Abc_NtkImplementRetimingBackward( Abc_Ntk_t * pNtk, Vec_Ptr_t * vMoves, int fVerbose )
-{
- Abc_RetEdge_t RetEdge;
- stmm_table * tTable;
- stmm_generator * gen;
- Vec_Int_t * vValues;
- Abc_Ntk_t * pNtkProb, * pNtkMiter, * pNtkCnf;
- Abc_Obj_t * pNode, * pNodeNew;
- int * pModel, RetValue, i, clk;
-
- // return if the retiming is trivial
- if ( Vec_PtrSize(vMoves) == 0 )
- return 1;
-
- // create the network for the initial state computation
- // start the table and the array of PO values
- pNtkProb = Abc_NtkAlloc( ABC_NTK_LOGIC, ABC_FUNC_SOP );
- tTable = stmm_init_table( stmm_numcmp, stmm_numhash );
- vValues = Vec_IntAlloc( 100 );
-
- // perform the backward moves and build the network for initial state computation
- RetValue = 0;
- Vec_PtrForEachEntry( vMoves, pNode, i )
- RetValue |= Abc_ObjRetimeBackward( pNode, pNtkProb, tTable, vValues );
-
- // add the PIs corresponding to the white spots
- stmm_foreach_item( tTable, gen, (char **)&RetEdge, (char **)&pNodeNew )
- Abc_ObjAddFanin( pNodeNew, Abc_NtkCreatePi(pNtkProb) );
-
- // add the PI/PO names
- Abc_NtkAddDummyPiNames( pNtkProb );
- Abc_NtkAddDummyPoNames( pNtkProb );
-
- // make sure everything is okay with the network structure
- if ( !Abc_NtkDoCheck( pNtkProb ) )
- {
- printf( "Abc_NtkImplementRetimingBackward: The internal network check has failed.\n" );
- Abc_NtkRetimeSetInitialValues( pNtk, tTable, NULL );
- Abc_NtkDelete( pNtkProb );
- stmm_free_table( tTable );
- Vec_IntFree( vValues );
- return 0;
- }
-
- // check if conflict is found
- if ( RetValue )
- {
- printf( "Abc_NtkImplementRetimingBackward: A top level conflict is detected. DC latch values are used.\n" );
- Abc_NtkRetimeSetInitialValues( pNtk, tTable, NULL );
- Abc_NtkDelete( pNtkProb );
- stmm_free_table( tTable );
- Vec_IntFree( vValues );
- return 0;
- }
-
- // get the miter cone
- pNtkMiter = Abc_NtkCreateCone( pNtkProb, pNtkProb->vCos, vValues );
- Abc_NtkDelete( pNtkProb );
- Vec_IntFree( vValues );
-
- if ( fVerbose )
- printf( "The number of ANDs in the AIG = %5d.\n", Abc_NtkNodeNum(pNtkMiter) );
-
- // transform the miter into a logic network for efficient CNF construction
- pNtkCnf = Abc_NtkRenode( pNtkMiter, 0, 100, 1, 0, 0 );
- Abc_NtkDelete( pNtkMiter );
-
- // solve the miter
-clk = clock();
- RetValue = Abc_NtkMiterSat( pNtkCnf, 30, 0 );
-if ( fVerbose )
-if ( clock() - clk > 500 )
-{
-PRT( "SAT solving time", clock() - clk );
-}
- pModel = pNtkCnf->pModel; pNtkCnf->pModel = NULL;
- Abc_NtkDelete( pNtkCnf );
-
- // analyze the result
- if ( RetValue == -1 || RetValue == 1 )
- {
- Abc_NtkRetimeSetInitialValues( pNtk, tTable, NULL );
- if ( RetValue == 1 )
- printf( "Abc_NtkImplementRetimingBackward: The problem is unsatisfiable. DC latch values are used.\n" );
- else
- printf( "Abc_NtkImplementRetimingBackward: The SAT problem timed out. DC latch values are used.\n" );
- stmm_free_table( tTable );
- return 0;
- }
-
- // set the values of the latches
- Abc_NtkRetimeSetInitialValues( pNtk, tTable, pModel );
- stmm_free_table( tTable );
- free( pModel );
- return 1;
-}
-
-/**Function*************************************************************
-
- Synopsis [Retimes node backward by one latch.]
-
- Description [Constructs the problem for initial state computation.
- Returns 1 if the conflict is found.]
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-int Abc_ObjRetimeBackward( Abc_Obj_t * pObj, Abc_Ntk_t * pNtkNew, stmm_table * tTable, Vec_Int_t * vValues )
-{
- Abc_Obj_t * pFanout;
- Abc_InitType_t Init, Value;
- Abc_RetEdge_t RetEdge;
- Abc_Obj_t * pNodeNew, * pFanoutNew, * pBuffer;
- int i, Edge, fMet0, fMet1, fMetN;
-
- // make sure the node can be retimed
- assert( Abc_ObjFanoutLMin(pObj) > 0 );
- // get the fanout values
- fMet0 = fMet1 = fMetN = 0;
- Abc_ObjForEachFanout( pObj, pFanout, i )
- {
- Init = Abc_ObjFaninLGetInitLast( pFanout, Abc_ObjEdgeNum(pObj, pFanout) );
- if ( Init == ABC_INIT_ZERO )
- fMet0 = 1;
- else if ( Init == ABC_INIT_ONE )
- fMet1 = 1;
- else if ( Init == ABC_INIT_NONE )
- fMetN = 1;
- }
-
- // consider the case when all fanout latchs have don't-care values
- // the new values on the fanin edges will be don't-cares
- if ( !fMet0 && !fMet1 && !fMetN )
- {
- // update the fanout edges
- Abc_ObjForEachFanout( pObj, pFanout, i )
- Abc_ObjFaninLDeleteLast( pFanout, Abc_ObjEdgeNum(pObj, pFanout) );
- // update the fanin edges
- Abc_ObjRetimeBackwardUpdateEdge( pObj, 0, tTable );
- Abc_ObjRetimeBackwardUpdateEdge( pObj, 1, tTable );
- Abc_ObjFaninLInsertFirst( pObj, 0, ABC_INIT_DC );
- Abc_ObjFaninLInsertFirst( pObj, 1, ABC_INIT_DC );
- return 0;
- }
- // the initial values on the fanout edges contain 0, 1, or unknown
- // the new values on the fanin edges will be unknown
-
- // add new AND-gate to the network
- pNodeNew = Abc_NtkCreateNode( pNtkNew );
- pNodeNew->pData = Abc_SopCreateAnd2( pNtkNew->pManFunc, Abc_ObjFaninC0(pObj), Abc_ObjFaninC1(pObj) );
-
- // add PO fanouts if any
- if ( fMet0 )
- {
- Abc_ObjAddFanin( Abc_NtkCreatePo(pNtkNew), pNodeNew );
- Vec_IntPush( vValues, 0 );
- }
- if ( fMet1 )
- {
- Abc_ObjAddFanin( Abc_NtkCreatePo(pNtkNew), pNodeNew );
- Vec_IntPush( vValues, 1 );
- }
-
- // perform the changes
- Abc_ObjForEachFanout( pObj, pFanout, i )
- {
- Edge = Abc_ObjEdgeNum( pObj, pFanout );
- Value = Abc_ObjFaninLDeleteLast( pFanout, Edge );
- if ( Value != ABC_INIT_NONE )
- continue;
- // value is unknown, remove it from the table
- RetEdge.iNode = pFanout->Id;
- RetEdge.iEdge = Edge;
- RetEdge.iLatch = Abc_ObjFaninL( pFanout, Edge ); // after edge is removed
- if ( !stmm_delete( tTable, (char **)&RetEdge, (char **)&pFanoutNew ) )
- assert( 0 );
- // create the fanout of the AND gate
- Abc_ObjAddFanin( pFanoutNew, pNodeNew );
- }
-
- // update the fanin edges
- Abc_ObjRetimeBackwardUpdateEdge( pObj, 0, tTable );
- Abc_ObjRetimeBackwardUpdateEdge( pObj, 1, tTable );
- Abc_ObjFaninLInsertFirst( pObj, 0, ABC_INIT_NONE );
- Abc_ObjFaninLInsertFirst( pObj, 1, ABC_INIT_NONE );
-
- // add the buffer
- pBuffer = Abc_NtkCreateNode( pNtkNew );
- pBuffer->pData = Abc_SopCreateBuf( pNtkNew->pManFunc );
- Abc_ObjAddFanin( pNodeNew, pBuffer );
- // point to it from the table
- RetEdge.iNode = pObj->Id;
- RetEdge.iEdge = 0;
- RetEdge.iLatch = 0;
- if ( stmm_insert( tTable, (char *)Abc_RetEdge2Int(RetEdge), (char *)pBuffer ) )
- assert( 0 );
-
- // add the buffer
- pBuffer = Abc_NtkCreateNode( pNtkNew );
- pBuffer->pData = Abc_SopCreateBuf( pNtkNew->pManFunc );
- Abc_ObjAddFanin( pNodeNew, pBuffer );
- // point to it from the table
- RetEdge.iNode = pObj->Id;
- RetEdge.iEdge = 1;
- RetEdge.iLatch = 0;
- if ( stmm_insert( tTable, (char *)Abc_RetEdge2Int(RetEdge), (char *)pBuffer ) )
- assert( 0 );
-
- // report conflict is found
- return fMet0 && fMet1;
-}
-
-/**Function*************************************************************
-
- Synopsis [Generates the printable edge label with the initial state.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Abc_ObjRetimeBackwardUpdateEdge( Abc_Obj_t * pObj, int Edge, stmm_table * tTable )
-{
- Abc_Obj_t * pFanoutNew;
- Abc_RetEdge_t RetEdge;
- Abc_InitType_t Init;
- int nLatches, i;
-
- // get the number of latches on the edge
- nLatches = Abc_ObjFaninL( pObj, Edge );
- assert( nLatches <= ABC_MAX_EDGE_LATCH );
- for ( i = nLatches - 1; i >= 0; i-- )
- {
- // get the value of this latch
- Init = Abc_ObjFaninLGetInitOne( pObj, Edge, i );
- if ( Init != ABC_INIT_NONE )
- continue;
- // get the retiming edge
- RetEdge.iNode = pObj->Id;
- RetEdge.iEdge = Edge;
- RetEdge.iLatch = i;
- // remove entry from table and add it with a different key
- if ( !stmm_delete( tTable, (char **)&RetEdge, (char **)&pFanoutNew ) )
- assert( 0 );
- RetEdge.iLatch++;
- if ( stmm_insert( tTable, (char *)Abc_RetEdge2Int(RetEdge), (char *)pFanoutNew ) )
- assert( 0 );
- }
-}
-
-/**Function*************************************************************
-
- Synopsis [Sets the initial values.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Abc_NtkRetimeSetInitialValues( Abc_Ntk_t * pNtk, stmm_table * tTable, int * pModel )
-{
- Abc_Obj_t * pNode;
- stmm_generator * gen;
- Abc_RetEdge_t RetEdge;
- Abc_InitType_t Init;
- int i;
-
- i = 0;
- stmm_foreach_item( tTable, gen, (char **)&RetEdge, NULL )
- {
- pNode = Abc_NtkObj( pNtk, RetEdge.iNode );
- Init = pModel? (pModel[i]? ABC_INIT_ONE : ABC_INIT_ZERO) : ABC_INIT_DC;
- Abc_ObjFaninLSetInitOne( pNode, RetEdge.iEdge, RetEdge.iLatch, Init );
- i++;
- }
-}
-
-////////////////////////////////////////////////////////////////////////
-/// END OF FILE ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/src/base/abcs/abcRetUtil.c b/src/base/abcs/abcRetUtil.c
deleted file mode 100644
index 9a283e03..00000000
--- a/src/base/abcs/abcRetUtil.c
+++ /dev/null
@@ -1,244 +0,0 @@
-/**CFile****************************************************************
-
- FileName [abcRetUtil.c]
-
- SystemName [ABC: Logic synthesis and verification system.]
-
- PackageName [Network and node package.]
-
- Synopsis [Retiming utilities.]
-
- Author [Alan Mishchenko]
-
- Affiliation [UC Berkeley]
-
- Date [Ver. 1.0. Started - June 20, 2005.]
-
- Revision [$Id: abcRetUtil.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "abcs.h"
-
-////////////////////////////////////////////////////////////////////////
-/// DECLARATIONS ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-/// FUNCTION DEFINITIONS ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
- Synopsis [Performs forward retiming of the sequential AIG.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-Vec_Ptr_t * Abc_NtkUtilRetimingTry( Abc_Ntk_t * pNtk, bool fForward )
-{
- Vec_Ptr_t * vNodes, * vMoves;
- Abc_Obj_t * pNode, * pFanout, * pFanin;
- int i, k, nLatches;
- assert( Abc_NtkIsSeq( pNtk ) );
- // assume that all nodes can be retimed
- vNodes = Vec_PtrAlloc( 100 );
- Abc_AigForEachAnd( pNtk, pNode, i )
- {
- Vec_PtrPush( vNodes, pNode );
- pNode->fMarkA = 1;
- }
- // process the nodes
- vMoves = Vec_PtrAlloc( 100 );
- Vec_PtrForEachEntry( vNodes, pNode, i )
- {
-// printf( "(%d,%d) ", Abc_ObjFaninL0(pNode), Abc_ObjFaninL0(pNode) );
- // unmark the node as processed
- pNode->fMarkA = 0;
- // get the number of latches to retime
- if ( fForward )
- nLatches = Abc_ObjFaninLMin(pNode);
- else
- nLatches = Abc_ObjFanoutLMin(pNode);
- if ( nLatches == 0 )
- continue;
- assert( nLatches > 0 );
- // retime the latches forward
- if ( fForward )
- Abc_ObjRetimeForwardTry( pNode, nLatches );
- else
- Abc_ObjRetimeBackwardTry( pNode, nLatches );
- // write the moves
- for ( k = 0; k < nLatches; k++ )
- Vec_PtrPush( vMoves, pNode );
- // schedule fanouts for updating
- if ( fForward )
- {
- Abc_ObjForEachFanout( pNode, pFanout, k )
- {
- if ( Abc_ObjFaninNum(pFanout) != 2 || pFanout->fMarkA )
- continue;
- pFanout->fMarkA = 1;
- Vec_PtrPush( vNodes, pFanout );
- }
- }
- else
- {
- Abc_ObjForEachFanin( pNode, pFanin, k )
- {
- if ( Abc_ObjFaninNum(pFanin) != 2 || pFanin->fMarkA )
- continue;
- pFanin->fMarkA = 1;
- Vec_PtrPush( vNodes, pFanin );
- }
- }
- }
- Vec_PtrFree( vNodes );
- // make sure the marks are clean the the retiming is final
- Abc_AigForEachAnd( pNtk, pNode, i )
- {
- assert( pNode->fMarkA == 0 );
- if ( fForward )
- assert( Abc_ObjFaninLMin(pNode) == 0 );
- else
- assert( Abc_ObjFanoutLMin(pNode) == 0 );
- }
- return vMoves;
-}
-
-/**Function*************************************************************
-
- Synopsis [Translates retiming steps into retiming moves.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-Vec_Ptr_t * Abc_NtkUtilRetimingGetMoves( Abc_Ntk_t * pNtk, Vec_Int_t * vSteps, bool fForward )
-{
- Abc_RetStep_t RetStep;
- Vec_Ptr_t * vMoves;
- Abc_Obj_t * pNode;
- int i, k, iNode, nLatches, Number;
- int fChange;
- assert( Abc_NtkIsSeq( pNtk ) );
- // process the nodes
- vMoves = Vec_PtrAlloc( 100 );
- while ( Vec_IntSize(vSteps) > 0 )
- {
- iNode = 0;
- fChange = 0;
- Vec_IntForEachEntry( vSteps, Number, i )
- {
- // get the retiming step
- RetStep = Abc_Int2RetStep( Number );
- // get the node to be retimed
- pNode = Abc_NtkObj( pNtk, RetStep.iNode );
- assert( RetStep.nLatches > 0 );
- // get the number of latches that can be retimed
- if ( fForward )
- nLatches = Abc_ObjFaninLMin(pNode);
- else
- nLatches = Abc_ObjFanoutLMin(pNode);
- if ( nLatches == 0 )
- {
- Vec_IntWriteEntry( vSteps, iNode++, Abc_RetStep2Int(RetStep) );
- continue;
- }
- assert( nLatches > 0 );
- fChange = 1;
- // get the number of latches to be retimed over this node
- nLatches = ABC_MIN( nLatches, (int)RetStep.nLatches );
- // retime the latches forward
- if ( fForward )
- Abc_ObjRetimeForwardTry( pNode, nLatches );
- else
- Abc_ObjRetimeBackwardTry( pNode, nLatches );
- // write the moves
- for ( k = 0; k < nLatches; k++ )
- Vec_PtrPush( vMoves, pNode );
- // subtract the retiming performed
- RetStep.nLatches -= nLatches;
- // store the node if it is not retimed completely
- if ( RetStep.nLatches > 0 )
- Vec_IntWriteEntry( vSteps, iNode++, Abc_RetStep2Int(RetStep) );
- }
- // reduce the array
- Vec_IntShrink( vSteps, iNode );
- if ( !fChange )
- {
- printf( "Warning: %d strange steps.\n", Vec_IntSize(vSteps) );
- /*
- Vec_IntForEachEntry( vSteps, Number, i )
- {
- RetStep = Abc_Int2RetStep( Number );
- printf( "%d(%d) ", RetStep.iNode, RetStep.nLatches );
- }
- printf( "\n" );
- */
- break;
- }
- }
- // undo the tentative retiming
- if ( fForward )
- {
- Vec_PtrForEachEntryReverse( vMoves, pNode, i )
- Abc_ObjRetimeBackwardTry( pNode, 1 );
- }
- else
- {
- Vec_PtrForEachEntryReverse( vMoves, pNode, i )
- Abc_ObjRetimeForwardTry( pNode, 1 );
- }
- return vMoves;
-}
-
-
-/**Function*************************************************************
-
- Synopsis [Splits retiming into forward and backward.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-Vec_Int_t * Abc_NtkUtilRetimingSplit( Vec_Str_t * vLags, int fForward )
-{
- Vec_Int_t * vNodes;
- Abc_RetStep_t RetStep;
- int Value, i;
- vNodes = Vec_IntAlloc( 100 );
- Vec_StrForEachEntry( vLags, Value, i )
- {
-// assert( Value <= ABC_MAX_EDGE_LATCH );
- if ( Value < 0 && fForward )
- {
- RetStep.iNode = i;
- RetStep.nLatches = -Value;
- Vec_IntPush( vNodes, Abc_RetStep2Int(RetStep) );
- }
- else if ( Value > 0 && !fForward )
- {
- RetStep.iNode = i;
- RetStep.nLatches = Value;
- Vec_IntPush( vNodes, Abc_RetStep2Int(RetStep) );
- }
- }
- return vNodes;
-}
-
-////////////////////////////////////////////////////////////////////////
-/// END OF FILE ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/src/base/abcs/abcSeq.c b/src/base/abcs/abcSeq.c
deleted file mode 100644
index 8e701c09..00000000
--- a/src/base/abcs/abcSeq.c
+++ /dev/null
@@ -1,365 +0,0 @@
-/**CFile****************************************************************
-
- FileName [abcSeq.c]
-
- SystemName [ABC: Logic synthesis and verification system.]
-
- PackageName [Network and node package.]
-
- Synopsis [Procedures to derive sequential AIG from combinational AIG with latches.]
-
- Author [Alan Mishchenko]
-
- Affiliation [UC Berkeley]
-
- Date [Ver. 1.0. Started - June 20, 2005.]
-
- Revision [$Id: abcSeq.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "abcs.h"
-
-/*
- A sequential network is similar to AIG in that it contains only
- AND gates. However, the AND-gates are currently not hashed.
-
- When converting AIG into sequential AIG:
- - Const1/PIs/POs remain the same as in the original AIG.
- - Instead of the latches, a new cutset is added, which is currently
- defined as a set of AND gates that have a latch among their fanouts.
- - The edges of a sequential AIG are labeled with latch attributes
- in addition to the complementation attibutes.
- - The attributes contain information about the number of latches
- and their initial states.
- - The number of latches is stored directly on the edges. The initial
- states are stored in a special array associated with the network.
-
- The AIG of sequential network is static in the sense that the
- new AIG nodes are never created.
- The retiming (or retiming/mapping) is performed by moving the
- latches over the static nodes of the AIG.
- The new initial state after forward retiming is computed in a
- straight-forward manner. After backward retiming it is computed
- by setting up a SAT problem.
-*/
-
-////////////////////////////////////////////////////////////////////////
-/// DECLARATIONS ///
-////////////////////////////////////////////////////////////////////////
-
-static Vec_Ptr_t * Abc_NtkAigCutsetCopy( Abc_Ntk_t * pNtk );
-static Abc_Obj_t * Abc_NodeAigToSeq( Abc_Obj_t * pAnd, int Num, int * pnLatches, unsigned * pnInit );
-static Abc_Obj_t * Abc_NodeSeqToLogic( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pFanin, int nLatches, unsigned Init );
-
-////////////////////////////////////////////////////////////////////////
-/// FUNCTION DEFINITIONS ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
- Synopsis [Converts combinational AIG with latches into sequential AIG.]
-
- Description [The const/PI/PO nodes are duplicated. The internal
- nodes are duplicated in the topological order. The dangling nodes
- are not duplicated. The choice nodes are duplicated.]
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-Abc_Ntk_t * Abc_NtkAigToSeq( Abc_Ntk_t * pNtk )
-{
- Abc_Ntk_t * pNtkNew;
- Vec_Ptr_t * vNodes;
- Abc_Obj_t * pObj, * pFaninNew;
- unsigned Init;
- int i, nLatches;
- // make sure it is an AIG without self-feeding latches
- assert( Abc_NtkIsStrash(pNtk) );
- assert( Abc_NtkCountSelfFeedLatches(pNtk) == 0 );
- // start the network
- Abc_NtkCleanCopy( pNtk );
- pNtkNew = Abc_NtkAlloc( ABC_NTK_SEQ, ABC_FUNC_AIG );
- // duplicate the name and the spec
- pNtkNew->pName = util_strsav(pNtk->pName);
- pNtkNew->pSpec = util_strsav(pNtk->pSpec);
- // clone const/PIs/POs
- Abc_NtkDupObj(pNtkNew, Abc_AigConst1(pNtk->pManFunc) );
- pNtkNew->nNodes -= 1;
- Abc_NtkForEachPi( pNtk, pObj, i )
- Abc_NtkDupObj(pNtkNew, pObj);
- Abc_NtkForEachPo( pNtk, pObj, i )
- Abc_NtkDupObj(pNtkNew, pObj);
-// Abc_NtkForEachLatch( pNtk, pObj, i )
-// Vec_PtrPush( pNtkNew->vObjs, NULL );
- // copy the PI/PO names
- Abc_NtkForEachPi( pNtk, pObj, i )
- Abc_NtkLogicStoreName( Abc_NtkPi(pNtkNew,i), Abc_ObjName(pObj) );
- Abc_NtkForEachPo( pNtk, pObj, i )
- Abc_NtkLogicStoreName( Abc_NtkPo(pNtkNew,i), Abc_ObjName(pObj) );
- // copy the internal nodes, including choices, excluding dangling
- vNodes = Abc_AigDfs( pNtk, 0, 0 );
- Vec_PtrForEachEntry( vNodes, pObj, i )
- {
- if ( Abc_ObjFaninNum(pObj) != 2 )
- continue;
- Abc_NtkDupObj(pNtkNew, pObj);
-// assert( pObj->Id == pObj->pCopy->Id );
- pObj->pCopy->fPhase = pObj->fPhase; // needed for choices
- pObj->pCopy->Level = pObj->Level;
- }
- // relink the choice nodes
- Vec_PtrForEachEntry( vNodes, pObj, i )
- if ( pObj->pData )
- pObj->pCopy->pData = ((Abc_Obj_t *)pObj->pData)->pCopy;
- Vec_PtrFree( vNodes );
- // start the storage for initial states
- pNtkNew->vInits = Vec_IntStart( 2 * Abc_NtkObjNumMax(pNtkNew) );
- // reconnect the internal nodes
- Abc_NtkForEachObj( pNtk, pObj, i )
- {
- // skip the constant and the PIs
- if ( Abc_ObjFaninNum(pObj) == 0 )
- continue;
- if ( Abc_ObjIsLatch(pObj) )
- continue;
- // process the first fanin
- pFaninNew = Abc_NodeAigToSeq( pObj, 0, &nLatches, &Init );
- if ( nLatches > ABC_MAX_EDGE_LATCH )
- {
- printf( "The number of latches on an edge (%d) exceeds the limit (%d).\n", nLatches, ABC_MAX_EDGE_LATCH );
- nLatches = ABC_MAX_EDGE_LATCH;
- }
- Abc_ObjAddFanin( pObj->pCopy, pFaninNew );
- Abc_ObjAddFaninL0( pObj->pCopy, nLatches );
- Vec_IntWriteEntry( pNtkNew->vInits, 2 * pObj->pCopy->Id + 0, Init );
- if ( Abc_ObjFaninNum(pObj) == 1 )
- continue;
- // process the second fanin
- pFaninNew = Abc_NodeAigToSeq( pObj, 1, &nLatches, &Init );
- if ( nLatches > ABC_MAX_EDGE_LATCH )
- {
- printf( "The number of latches on an edge (%d) exceeds the limit (%d).\n", nLatches, ABC_MAX_EDGE_LATCH );
- nLatches = ABC_MAX_EDGE_LATCH;
- }
- Abc_ObjAddFanin( pObj->pCopy, pFaninNew );
- Abc_ObjAddFaninL1( pObj->pCopy, nLatches );
- Vec_IntWriteEntry( pNtkNew->vInits, 2 * pObj->pCopy->Id + 1, Init );
- }
- // set the cutset composed of latch drivers
- Vec_PtrFree( pNtkNew->vLats );
- pNtkNew->vLats = Abc_NtkAigCutsetCopy( pNtk );
- // copy EXDC and check correctness
- if ( pNtkNew->pExdc )
- fprintf( stdout, "Warning: EXDC is dropped when converting to sequential AIG.\n" );
- if ( !Abc_NtkCheck( pNtkNew ) )
- fprintf( stdout, "Abc_NtkAigToSeq(): Network check has failed.\n" );
- return pNtkNew;
-}
-
-/**Function*************************************************************
-
- Synopsis [Collects the cut set nodes.]
-
- Description [These are internal AND gates that fanins into latches.]
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-Vec_Ptr_t * Abc_NtkAigCutsetCopy( Abc_Ntk_t * pNtk )
-{
- Vec_Ptr_t * vNodes;
- Abc_Obj_t * pLatch, * pDriver;
- int i;
- vNodes = Vec_PtrAlloc( Abc_NtkLatchNum(pNtk) );
- Abc_NtkIncrementTravId(pNtk);
- Abc_NtkForEachLatch( pNtk, pLatch, i )
- {
- pDriver = Abc_ObjFanin0(pLatch);
- if ( Abc_NodeIsTravIdCurrent(pDriver) || !Abc_NodeIsAigAnd(pDriver) )
- continue;
- Abc_NodeSetTravIdCurrent(pDriver);
- Vec_PtrPush( vNodes, pDriver->pCopy );
- }
- return vNodes;
-}
-
-/**Function*************************************************************
-
- Synopsis [Determines the fanin that is transparent for latches.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-Abc_Obj_t * Abc_NodeAigToSeq( Abc_Obj_t * pObj, int Num, int * pnLatches, unsigned * pnInit )
-{
- Abc_Obj_t * pFanin, * pFaninNew;
- Abc_InitType_t Init;
- // get the given fanin of the node
- pFanin = Abc_ObjFanin( pObj, Num );
- // if fanin is the internal node, return its copy in the corresponding polarity
- if ( !Abc_ObjIsLatch(pFanin) )
- {
- *pnLatches = 0;
- *pnInit = 0;
- return Abc_ObjNotCond( pFanin->pCopy, Abc_ObjFaninC(pObj, Num) );
- }
- // fanin is a latch
- // get the new fanins
- pFaninNew = Abc_NodeAigToSeq( pFanin, 0, pnLatches, pnInit );
- // get the initial state
- Init = Abc_LatchInit(pFanin);
- // complement the initial state if the inv is retimed over the latch
- if ( Abc_ObjIsComplement(pFaninNew) )
- {
- if ( Init == ABC_INIT_ZERO )
- Init = ABC_INIT_ONE;
- else if ( Init == ABC_INIT_ONE )
- Init = ABC_INIT_ZERO;
- else if ( Init != ABC_INIT_DC )
- assert( 0 );
- }
- // update the latch number and initial state
- (*pnLatches)++;
- (*pnInit) = ((*pnInit) << 2) | Init;
- return Abc_ObjNotCond( pFaninNew, Abc_ObjFaninC(pObj, Num) );
-}
-
-
-
-
-/**Function*************************************************************
-
- Synopsis [Converts a sequential AIG into a logic SOP network.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-Abc_Ntk_t * Abc_NtkSeqToLogicSop( Abc_Ntk_t * pNtk )
-{
- Abc_Ntk_t * pNtkNew;
- Abc_Obj_t * pObj, * pObjNew, * pFaninNew, * pConst1;
- int i, nCutNodes;
- unsigned Init;
- int nLatchMax = 0;
-
- assert( Abc_NtkIsSeq(pNtk) );
- // start the network without latches
- nCutNodes = pNtk->vLats->nSize; pNtk->vLats->nSize = 0;
- pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC, ABC_FUNC_SOP );
- pNtk->vLats->nSize = nCutNodes;
- // create the constant node
-// Abc_NtkDupConst1( pNtk, pNtkNew );
- pConst1 = Abc_NtkObj(pNtk,0);
- if ( !Abc_ObjIsNode(pConst1) )
- pConst1 = NULL;
- if ( pConst1 && Abc_ObjFanoutNum(pConst1) > 0 )
- pConst1->pCopy = Abc_NodeCreateConst1( pNtkNew );
-
- // duplicate the nodes, create node functions
- Abc_NtkForEachNode( pNtk, pObj, i )
- {
- // skip the constant
- if ( Abc_ObjFaninNum(pObj) == 0 )
- continue;
- // duplicate the node
- Abc_NtkDupObj(pNtkNew, pObj);
- if ( Abc_ObjFaninNum(pObj) == 1 )
- {
- assert( !Abc_ObjFaninC0(pObj) );
- pObj->pCopy->pData = Abc_SopCreateBuf( pNtkNew->pManFunc );
- continue;
- }
- pObj->pCopy->pData = Abc_SopCreateAnd2( pNtkNew->pManFunc, Abc_ObjFaninC0(pObj), Abc_ObjFaninC1(pObj) );
- }
- // connect the objects
- Abc_NtkForEachObj( pNtk, pObj, i )
- {
- assert( (int)pObj->Id == i );
- // skip PIs and the constant
- if ( Abc_ObjFaninNum(pObj) == 0 )
- continue;
- if ( nLatchMax < Abc_ObjFaninL0(pObj) )
- nLatchMax = Abc_ObjFaninL0(pObj);
- // get the initial states of the latches on the fanin edge of this node
- Init = Vec_IntEntry( pNtk->vInits, 2 * pObj->Id );
- // create the edge
- pFaninNew = Abc_NodeSeqToLogic( pNtkNew, Abc_ObjFanin0(pObj), Abc_ObjFaninL0(pObj), Init );
- Abc_ObjAddFanin( pObj->pCopy, pFaninNew );
- if ( Abc_ObjFaninNum(pObj) == 1 )
- {
- // create the complemented edge
- if ( Abc_ObjFaninC0(pObj) )
- Abc_ObjSetFaninC( pObj->pCopy, 0 );
- continue;
- }
- if ( nLatchMax < Abc_ObjFaninL0(pObj) )
- nLatchMax = Abc_ObjFaninL0(pObj);
- // get the initial states of the latches on the fanin edge of this node
- Init = Vec_IntEntry( pNtk->vInits, 2 * pObj->Id + 1 );
- // create the edge
- pFaninNew = Abc_NodeSeqToLogic( pNtkNew, Abc_ObjFanin1(pObj), Abc_ObjFaninL1(pObj), Init );
- Abc_ObjAddFanin( pObj->pCopy, pFaninNew );
- // the complemented edges are subsumed by the node function
- }
-// printf( "The max edge latch num = %d.\n", nLatchMax );
- // add the latches and their names
- Abc_NtkAddDummyLatchNames( pNtkNew );
- Abc_NtkForEachLatch( pNtkNew, pObjNew, i )
- {
- Vec_PtrPush( pNtkNew->vCis, pObjNew );
- Vec_PtrPush( pNtkNew->vCos, pObjNew );
- }
- // fix the problem with complemented and duplicated CO edges
- Abc_NtkLogicMakeSimpleCos( pNtkNew, 0 );
- if ( !Abc_NtkCheck( pNtkNew ) )
- fprintf( stdout, "Abc_NtkSeqToLogicSop(): Network check has failed.\n" );
- return pNtkNew;
-}
-
-
-/**Function*************************************************************
-
- Synopsis [Creates latches on one edge.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-Abc_Obj_t * Abc_NodeSeqToLogic( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pFanin, int nLatches, unsigned Init )
-{
- Abc_Obj_t * pLatch;
- if ( nLatches == 0 )
- {
- assert( pFanin->pCopy );
- return pFanin->pCopy;
- }
- pFanin = Abc_NodeSeqToLogic( pNtkNew, pFanin, nLatches - 1, Init >> 2 );
- pLatch = Abc_NtkCreateLatch( pNtkNew );
- pLatch->pData = (void *)(Init & 3);
- Abc_ObjAddFanin( pLatch, pFanin );
- return pLatch;
-}
-
-
-
-////////////////////////////////////////////////////////////////////////
-/// END OF FILE ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/src/base/abcs/abcSeqMan.c b/src/base/abcs/abcSeqMan.c
deleted file mode 100644
index 181d8c29..00000000
--- a/src/base/abcs/abcSeqMan.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/**CFile****************************************************************
-
- FileName [abcSeqMan.c]
-
- SystemName [ABC: Logic synthesis and verification system.]
-
- PackageName [Network and node package.]
-
- Synopsis [Manager of sequential AIGs.]
-
- Author [Alan Mishchenko]
-
- Affiliation [UC Berkeley]
-
- Date [Ver. 1.0. Started - June 20, 2005.]
-
- Revision [$Id: abcSeqMan.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "abcs.h"
-
-////////////////////////////////////////////////////////////////////////
-/// DECLARATIONS ///
-////////////////////////////////////////////////////////////////////////
-
-typedef struct Abc_SeqLat_t_ Abc_SeqLat_t;
-struct Abc_SeqLat_t_
-{
- Abc_SeqLat_t * pNext; // the next Lat in the ring
- Abc_SeqLat_t * pPrev; // the prev Lat in the ring
-};
-
-typedef struct Abc_SeqMan_t_ Abc_SeqMan_t;
-struct Abc_SeqMan_t_
-{
- int nSize; // the number of entries in all internal arrays
- Vec_Ptr_t * vInits; // the initial states for each edge in the AIG
- Extra_MmFixed_t * pMmInits; // memory manager for initial states of the Lates
-
-};
-
-// reading the contents of the lat
-static inline Abc_InitType_t Abc_SeqLatInit( Abc_SeqLat_t * pLat ) { return ((unsigned)pLat->pPrev) & 3; }
-static inline Abc_SeqLat_t * Abc_SeqLatNext( Abc_SeqLat_t * pLat ) { return pLat->pNext; }
-static inline Abc_SeqLat_t * Abc_SeqLatPrev( Abc_SeqLat_t * pLat ) { return (void *)(((unsigned)pLat->pPrev) & (ABC_FULL_MASK << 2)); }
-
-// setting the contents of the lat
-static inline void Abc_SeqLatSetInit( Abc_SeqLat_t * pLat, Abc_InitType_t Init ) { pLat->pPrev = (void *)( (3 & Init) | (((unsigned)pLat->pPrev) & (ABC_FULL_MASK << 2)) ); }
-static inline void Abc_SeqLatSetNext( Abc_SeqLat_t * pLat, Abc_SeqLat_t * pNext ) { pLat->pNext = pNext; }
-static inline void Abc_SeqLatSetPrev( Abc_SeqLat_t * pLat, Abc_SeqLat_t * pPrev ) { Abc_InitType_t Init = Abc_SeqLatInit(pLat); pLat->pPrev = pPrev; Abc_SeqLatSetInit(pLat, Init); }
-
-// accessing initial state datastructure
-static inline Vec_Ptr_t * Abc_SeqNodeInits( Abc_Obj_t * pObj ) { return ((Abc_SeqMan_t*)pObj->pNtk->pManFunc)->vInits; }
-static inline Abc_SeqLat_t * Abc_SeqNodeReadInit( Abc_Obj_t * pObj, int Edge ) { return Vec_PtrEntry( Abc_SeqNodeInits(pObj), (pObj->Id<<1)+Edge ); }
-static inline void Abc_SeqNodeSetInit ( Abc_Obj_t * pObj, int Edge, Abc_SeqLat_t * pInit ) { Vec_PtrWriteEntry( Abc_SeqNodeInits(pObj), (pObj->Id<<1)+Edge, pInit ); }
-static inline Abc_SeqLat_t * Abc_SeqNodeCreateLat( Abc_Obj_t * pObj ) { return (Abc_SeqLat_t *)Extra_MmFixedEntryFetch( ((Abc_SeqMan_t*)pObj->pNtk->pManFunc)->pMmInits ); }
-static inline void Abc_SeqNodeRecycleLat( Abc_Obj_t * pObj, Abc_SeqLat_t * pLat ) { Extra_MmFixedEntryRecycle( ((Abc_SeqMan_t*)pObj->pNtk->pManFunc)->pMmInits, (char *)pLat ); }
-
-// getting the Lat with the given number
-static inline Abc_SeqLat_t * Abc_SeqNodeGetLat( Abc_Obj_t * pObj, int Edge, int iLat )
-{
- int Counter;
- Abc_SeqLat_t * pLat = Abc_SeqNodeReadInit(pObj, Edge);
- for ( Counter = 0; Counter != iLat; Counter++ )
- pLat = pLat->pNext;
- return pLat;
-}
-// getting the first Lat
-static inline Abc_SeqLat_t * Abc_SeqNodeGetLatFirst( Abc_Obj_t * pObj, int Edge )
-{
- return Abc_SeqNodeReadInit(pObj, Edge);
-}
-// getting the last Lat
-static inline Abc_SeqLat_t * Abc_SeqNodeGetLatLast( Abc_Obj_t * pObj, int Edge )
-{
- return Abc_SeqLatPrev( Abc_SeqNodeReadInit(pObj, Edge) );
-}
-
-// getting the init value of the given Lat on the edge
-static inline Abc_InitType_t Abc_SeqNodeGetInitOne( Abc_Obj_t * pObj, int Edge, int iLat )
-{
- return Abc_SeqLatInit( Abc_SeqNodeGetLat(pObj, Edge, iLat) );
-}
-// geting the init value of the first Lat on the edge
-static inline Abc_InitType_t Abc_SeqNodeGetInitFirst( Abc_Obj_t * pObj, int Edge )
-{
- return Abc_SeqLatInit( Abc_SeqNodeGetLatFirst(pObj, Edge) );
-}
-// geting the init value of the last Lat on the edge
-static inline Abc_InitType_t Abc_SeqNodeGetInitLast( Abc_Obj_t * pObj, int Edge )
-{
- return Abc_SeqLatInit( Abc_SeqNodeGetLatLast(pObj, Edge) );
-}
-
-
-// setting the init value of the given Lat on the edge
-static inline void Abc_SeqNodeSetInitOne( Abc_Obj_t * pObj, int Edge, int iLat, Abc_InitType_t Init )
-{
- Abc_SeqLatSetInit( Abc_SeqNodeGetLat(pObj, Edge, iLat), Init );
-}
-
-
-// insert the first Lat on the edge
-static inline void Abc_SeqNodeInsertFirst( Abc_Obj_t * pObj, int Edge, Abc_InitType_t Init )
-{
- Abc_SeqLat_t * pLat, * pRing, * pPrev;
- pLat = Abc_SeqNodeCreateLat( pObj );
- pRing = Abc_SeqNodeReadInit( pObj, Edge );
- if ( pRing == NULL )
- {
- pLat->pNext = pLat->pPrev = pLat;
- Abc_SeqNodeSetInit( pObj, Edge, pLat );
- }
- else
- {
- Abc_SeqLatSetPrev( pRing, pLat );
- Abc_SeqLatSetNext( pLat, pRing );
- pPrev = Abc_SeqLatPrev( pRing );
- Abc_SeqLatSetPrev( pLat, pPrev );
- Abc_SeqLatSetNext( pPrev, pLat );
- Abc_SeqNodeSetInit( pObj, Edge, pLat ); // rotate the ring to make pLat the first
- }
- Abc_SeqLatSetInit( pLat, Init );
-}
-
-// insert the last Lat on the edge
-static inline void Abc_SeqNodeInsertLast( Abc_Obj_t * pObj, int Edge, Abc_InitType_t Init )
-{
- Abc_SeqLat_t * pLat, * pRing, * pPrev;
- pLat = Abc_SeqNodeCreateLat( pObj );
- pRing = Abc_SeqNodeReadInit( pObj, Edge );
- if ( pRing == NULL )
- {
- pLat->pNext = pLat->pPrev = pLat;
- Abc_SeqNodeSetInit( pObj, Edge, pLat );
- }
- else
- {
- Abc_SeqLatSetPrev( pRing, pLat );
- Abc_SeqLatSetNext( pLat, pRing );
- pPrev = Abc_SeqLatPrev( pRing );
- Abc_SeqLatSetPrev( pLat, pPrev );
- Abc_SeqLatSetNext( pPrev, pLat );
- }
- Abc_SeqLatSetInit( pLat, Init );
-}
-
-// delete the first Lat on the edge
-static inline Abc_InitType_t Abc_SeqNodeDeleteFirst( Abc_Obj_t * pObj, int Edge )
-{
- Abc_SeqLat_t * pLat, * pRing, * pPrev, * pNext;
- pRing = Abc_SeqNodeReadInit( pObj, Edge );
- pLat = pRing; // consider the first latch
- if ( pLat->pNext == pLat )
- Abc_SeqNodeSetInit( pObj, Edge, NULL );
- else
- {
- pPrev = Abc_SeqLatPrev( pLat );
- pNext = Abc_SeqLatNext( pLat );
- Abc_SeqLatSetPrev( pNext, pPrev );
- Abc_SeqLatSetNext( pPrev, pNext );
- Abc_SeqNodeSetInit( pObj, Edge, pNext ); // rotate the ring
- }
- Abc_SeqNodeRecycleLat( pObj, pLat );
-}
-
-// delete the last Lat on the edge
-static inline Abc_InitType_t Abc_SeqNodeDeleteLast( Abc_Obj_t * pObj, int Edge )
-{
- Abc_SeqLat_t * pLat, * pRing, * pPrev, * pNext;
- pRing = Abc_SeqNodeReadInit( pObj, Edge );
- pLat = Abc_SeqLatPrev( pRing ); // consider the last latch
- if ( pLat->pNext == pLat )
- Abc_SeqNodeSetInit( pObj, Edge, NULL );
- else
- {
- pPrev = Abc_SeqLatPrev( pLat );
- pNext = Abc_SeqLatNext( pLat );
- Abc_SeqLatSetPrev( pNext, pPrev );
- Abc_SeqLatSetNext( pPrev, pNext );
- }
- Abc_SeqNodeRecycleLat( pObj, pLat );
-}
-
-////////////////////////////////////////////////////////////////////////
-/// FUNCTION DEFINITIONS ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
- Synopsis []
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-Abc_SeqMan_t * Abc_SeqCreate( int nMaxId )
-{
- Abc_SeqMan_t * p;
- // start the manager
- p = ALLOC( Abc_SeqMan_t, 1 );
- memset( p, 0, sizeof(Abc_SeqMan_t) );
- p->nSize = nMaxId + 1;
- // create internal data structures
- p->vInits = Vec_PtrStart( 2 * p->nSize );
- p->pMmInits = Extra_MmFixedStart( sizeof(Abc_SeqLat_t) );
- return p;
-}
-
-////////////////////////////////////////////////////////////////////////
-/// END OF FILE ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/src/base/abcs/abcShare.c b/src/base/abcs/abcShare.c
deleted file mode 100644
index 43424705..00000000
--- a/src/base/abcs/abcShare.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/**CFile****************************************************************
-
- FileName [abcShare.c]
-
- SystemName [ABC: Logic synthesis and verification system.]
-
- PackageName [Procedures for latch sharing on the fanout edges.]
-
- Synopsis [Utilities working sequential AIGs.]
-
- Author [Alan Mishchenko]
-
- Affiliation [UC Berkeley]
-
- Date [Ver. 1.0. Started - June 20, 2005.]
-
- Revision [$Id: abcShare.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "abcs.h"
-
-////////////////////////////////////////////////////////////////////////
-/// DECLARATIONS ///
-////////////////////////////////////////////////////////////////////////
-
-static void Abc_NodeSeqShareFanouts( Abc_Obj_t * pNode, Vec_Ptr_t * vNodes );
-static void Abc_NodeSeqShareOne( Abc_Obj_t * pNode, Abc_InitType_t Init, Vec_Ptr_t * vNodes );
-
-////////////////////////////////////////////////////////////////////////
-/// FUNCTION DEFINITIONS ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
- Synopsis [Transforms the sequential AIG to take fanout sharing into account.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Abc_NtkSeqShareFanouts( Abc_Ntk_t * pNtk )
-{
- Vec_Ptr_t * vNodes;
- Abc_Obj_t * pObj;
- int i;
- vNodes = Vec_PtrAlloc( 10 );
- // share the PI latches
- Abc_NtkForEachPi( pNtk, pObj, i )
- Abc_NodeSeqShareFanouts( pObj, vNodes );
- // share the node latches
- Abc_NtkForEachNode( pNtk, pObj, i )
- Abc_NodeSeqShareFanouts( pObj, vNodes );
- Vec_PtrFree( vNodes );
-}
-
-/**Function*************************************************************
-
- Synopsis [Transforms the node to take fanout sharing into account.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Abc_NodeSeqShareFanouts( Abc_Obj_t * pNode, Vec_Ptr_t * vNodes )
-{
- Abc_Obj_t * pFanout;
- Abc_InitType_t Type;
- int nLatches[4], i;
- // skip the node with only one fanout
- if ( Abc_ObjFanoutNum(pNode) < 2 )
- return;
- // clean the the fanout counters
- for ( i = 0; i < 4; i++ )
- nLatches[i] = 0;
- // find the number of fanouts having latches of each type
- Abc_ObjForEachFanout( pNode, pFanout, i )
- {
- if ( Abc_ObjFanoutL(pNode, pFanout) == 0 )
- continue;
- Type = Abc_ObjFaninLGetInitLast( pFanout, Abc_ObjEdgeNum(pNode, pFanout) );
- nLatches[Type]++;
- }
- // decide what to do
- if ( nLatches[ABC_INIT_ZERO] > 1 && nLatches[ABC_INIT_ONE] > 1 ) // 0-group and 1-group
- {
- Abc_NodeSeqShareOne( pNode, ABC_INIT_ZERO, vNodes ); // shares 0 and DC
- Abc_NodeSeqShareOne( pNode, ABC_INIT_ONE, vNodes ); // shares 1 and DC
- }
- else if ( nLatches[ABC_INIT_ZERO] > 1 ) // 0-group
- Abc_NodeSeqShareOne( pNode, ABC_INIT_ZERO, vNodes ); // shares 0 and DC
- else if ( nLatches[ABC_INIT_ONE] > 1 ) // 1-group
- Abc_NodeSeqShareOne( pNode, ABC_INIT_ONE, vNodes ); // shares 1 and DC
- else if ( nLatches[ABC_INIT_DC] > 1 ) // DC-group
- {
- if ( nLatches[ABC_INIT_ZERO] > 0 )
- Abc_NodeSeqShareOne( pNode, ABC_INIT_ZERO, vNodes ); // shares 0 and DC
- else
- Abc_NodeSeqShareOne( pNode, ABC_INIT_ONE, vNodes ); // shares 1 and DC
- }
-}
-
-/**Function*************************************************************
-
- Synopsis [Transforms the node to take fanout sharing into account.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Abc_NodeSeqShareOne( Abc_Obj_t * pNode, Abc_InitType_t Init, Vec_Ptr_t * vNodes )
-{
- Vec_Int_t * vInits = pNode->pNtk->vInits;
- Abc_Obj_t * pFanout, * pBuffer;
- Abc_InitType_t Type, InitNew;
- int i;
- // collect the fanouts that satisfy the property (have initial value Init or DC)
- InitNew = ABC_INIT_DC;
- Vec_PtrClear( vNodes );
- Abc_ObjForEachFanout( pNode, pFanout, i )
- {
- if ( Abc_ObjFanoutL(pNode, pFanout) == 0 )
- continue;
- Type = Abc_ObjFaninLGetInitLast( pFanout, Abc_ObjEdgeNum(pNode, pFanout) );
- if ( Type == Init )
- InitNew = Init;
- if ( Type == Init || Type == ABC_INIT_DC )
- {
- Vec_PtrPush( vNodes, pFanout );
- Abc_ObjFaninLDeleteLast( pFanout, Abc_ObjEdgeNum(pNode, pFanout) );
- }
- }
- // create the new buffer
- pBuffer = Abc_NtkCreateNode( pNode->pNtk );
- Abc_ObjAddFanin( pBuffer, pNode );
- Abc_ObjSetFaninL( pBuffer, 0, 1 );
- // add the initial state
- assert( Vec_IntSize(vInits) == 2 * (int)pBuffer->Id );
- Vec_IntPush( vInits, InitNew );
- Vec_IntPush( vInits, 0 );
- // redirect the fanouts
- Vec_PtrForEachEntry( vNodes, pFanout, i )
- Abc_ObjPatchFanin( pFanout, pNode, pBuffer );
-}
-
-
-////////////////////////////////////////////////////////////////////////
-/// END OF FILE ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/src/base/abcs/abcUtils.c b/src/base/abcs/abcUtils.c
deleted file mode 100644
index 412098b1..00000000
--- a/src/base/abcs/abcUtils.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/**CFile****************************************************************
-
- FileName [abcUtils.c]
-
- SystemName [ABC: Logic synthesis and verification system.]
-
- PackageName [Network and node package.]
-
- Synopsis [Utilities working sequential AIGs.]
-
- Author [Alan Mishchenko]
-
- Affiliation [UC Berkeley]
-
- Date [Ver. 1.0. Started - June 20, 2005.]
-
- Revision [$Id: abcUtils.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#include "abcs.h"
-
-////////////////////////////////////////////////////////////////////////
-/// DECLARATIONS ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-/// FUNCTION DEFINITIONS ///
-////////////////////////////////////////////////////////////////////////
-
-/**Function*************************************************************
-
- Synopsis [Counts the number of latches in the sequential AIG.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-int Abc_NtkSeqLatchNum( Abc_Ntk_t * pNtk )
-{
- Abc_Obj_t * pObj;
- int i, Counter;
- assert( Abc_NtkIsSeq( pNtk ) );
- Counter = 0;
- Abc_NtkForEachNode( pNtk, pObj, i )
- Counter += Abc_ObjFaninLSum( pObj );
- Abc_NtkForEachPo( pNtk, pObj, i )
- Counter += Abc_ObjFaninLSum( pObj );
- return Counter;
-}
-
-/**Function*************************************************************
-
- Synopsis [Counts the number of latches in the sequential AIG.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-int Abc_NtkSeqLatchNumShared( Abc_Ntk_t * pNtk )
-{
- Abc_Obj_t * pObj;
- int i, Counter;
- assert( Abc_NtkIsSeq( pNtk ) );
- Counter = 0;
- Abc_NtkForEachPi( pNtk, pObj, i )
- Counter += Abc_ObjFanoutLMax( pObj );
- Abc_NtkForEachNode( pNtk, pObj, i )
- Counter += Abc_ObjFanoutLMax( pObj );
- return Counter;
-}
-
-/**Function*************************************************************
-
- Synopsis [Counts the number of latches in the sequential AIG.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Abc_ObjLatchGetInitNums( Abc_Obj_t * pObj, int Edge, int * pInits )
-{
- Abc_InitType_t Init;
- int nLatches, i;
- nLatches = Abc_ObjFaninL( pObj, Edge );
- assert( nLatches <= ABC_MAX_EDGE_LATCH );
- for ( i = 0; i < nLatches; i++ )
- {
- Init = Abc_ObjFaninLGetInitOne( pObj, Edge, i );
- pInits[Init]++;
- }
-}
-
-/**Function*************************************************************
-
- Synopsis [Counts the number of latches in the sequential AIG.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-void Abc_NtkSeqLatchGetInitNums( Abc_Ntk_t * pNtk, int * pInits )
-{
- Abc_Obj_t * pObj;
- int i;
- assert( Abc_NtkIsSeq( pNtk ) );
- for ( i = 0; i < 4; i++ )
- pInits[i] = 0;
- Abc_NtkForEachPo( pNtk, pObj, i )
- Abc_ObjLatchGetInitNums( pObj, 0, pInits );
- Abc_NtkForEachNode( pNtk, pObj, i )
- {
- if ( Abc_ObjFaninNum(pObj) > 0 )
- Abc_ObjLatchGetInitNums( pObj, 0, pInits );
- if ( Abc_ObjFaninNum(pObj) > 1 )
- Abc_ObjLatchGetInitNums( pObj, 1, pInits );
- }
-}
-
-/**Function*************************************************************
-
- Synopsis [Generates the printable edge label with the initial state.]
-
- Description []
-
- SideEffects []
-
- SeeAlso []
-
-***********************************************************************/
-char * Abc_ObjFaninGetInitPrintable( Abc_Obj_t * pObj, int Edge )
-{
- static char Buffer[ABC_MAX_EDGE_LATCH + 1];
- Abc_InitType_t Init;
- int nLatches, i;
-
- nLatches = Abc_ObjFaninL( pObj, Edge );
- assert( nLatches <= ABC_MAX_EDGE_LATCH );
- for ( i = 0; i < nLatches; i++ )
- {
- Init = Abc_ObjFaninLGetInitOne( pObj, Edge, i );
- if ( Init == ABC_INIT_NONE )
- Buffer[i] = '_';
- else if ( Init == ABC_INIT_ZERO )
- Buffer[i] = '0';
- else if ( Init == ABC_INIT_ONE )
- Buffer[i] = '1';
- else if ( Init == ABC_INIT_DC )
- Buffer[i] = 'x';
- else assert( 0 );
- }
- Buffer[nLatches] = 0;
- return Buffer;
-}
-
-////////////////////////////////////////////////////////////////////////
-/// END OF FILE ///
-////////////////////////////////////////////////////////////////////////
-
-
diff --git a/src/base/abcs/abcs.h b/src/base/abcs/abcs.h
deleted file mode 100644
index a85556ac..00000000
--- a/src/base/abcs/abcs.h
+++ /dev/null
@@ -1,355 +0,0 @@
-/**CFile****************************************************************
-
- FileName [abcs.h]
-
- SystemName [ABC: Logic synthesis and verification system.]
-
- PackageName [Sequential synthesis package.]
-
- Synopsis [External declarations.]
-
- Author [Alan Mishchenko]
-
- Affiliation [UC Berkeley]
-
- Date [Ver. 1.0. Started - June 20, 2005.]
-
- Revision [$Id: abcs.h,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
-
-***********************************************************************/
-
-#ifndef __ABCS_H__
-#define __ABCS_H__
-
-////////////////////////////////////////////////////////////////////////
-/// INCLUDES ///
-////////////////////////////////////////////////////////////////////////
-
-#include "abc.h"
-#include "cut.h"
-
-////////////////////////////////////////////////////////////////////////
-/// PARAMETERS ///
-////////////////////////////////////////////////////////////////////////
-
-// the maximum number of latches on the edge
-#define ABC_MAX_EDGE_LATCH 16
-#define ABC_FULL_MASK 0xFFFFFFFF
-
-////////////////////////////////////////////////////////////////////////
-/// BASIC TYPES ///
-////////////////////////////////////////////////////////////////////////
-
-typedef struct Seq_FpgaMan_t_ Seq_FpgaMan_t;
-struct Seq_FpgaMan_t_
-{
- Abc_Ntk_t * pNtk; // the network to be mapped
- Cut_Man_t * pMan; // the cut manager
- Vec_Int_t * vArrivals; // the arrival times (L-Values of nodes)
- Vec_Ptr_t * vBestCuts; // the best cuts for nodes
- Vec_Ptr_t * vMapping; // the nodes used in the mapping
- Vec_Ptr_t * vMapCuts; // the info about the cut of each mapped node
- Vec_Str_t * vLagsMap; // the lags of the mapped nodes
- int fVerbose; // the verbose flag
- // runtime stats
- int timeCuts; // runtime to compute the cuts
- int timeDelay; // runtime to compute the L-values
- int timeRet; // runtime to retime the resulting network
- int timeNtk; // runtime to create the final network
-};
-
-
-// representation of latch on the edge
-typedef struct Abc_RetEdge_t_ Abc_RetEdge_t;
-struct Abc_RetEdge_t_ // 1 word
-{
- unsigned iNode : 24; // the ID of the node
- unsigned iEdge : 1; // the edge of the node
- unsigned iLatch : 7; // the latch number counting from the node
-};
-
-// representation of one retiming step
-typedef struct Abc_RetStep_t_ Abc_RetStep_t;
-struct Abc_RetStep_t_ // 1 word
-{
- unsigned iNode : 24; // the ID of the node
- unsigned nLatches : 8; // the number of latches to retime
-};
-
-static inline int Abc_RetEdge2Int( Abc_RetEdge_t Str ) { return *((int *)&Str); }
-static inline Abc_RetEdge_t Abc_Int2RetEdge( int Num ) { return *((Abc_RetEdge_t *)&Num); }
-
-static inline int Abc_RetStep2Int( Abc_RetStep_t Str ) { return *((int *)&Str); }
-static inline Abc_RetStep_t Abc_Int2RetStep( int Num ) { return *((Abc_RetStep_t *)&Num); }
-
-// storing arrival times in the nodes
-static inline int Abc_NodeReadLValue( Abc_Obj_t * pNode ) { return Vec_IntEntry( (pNode)->pNtk->pData, (pNode)->Id ); }
-static inline void Abc_NodeSetLValue( Abc_Obj_t * pNode, int Value ) { Vec_IntWriteEntry( (pNode)->pNtk->pData, (pNode)->Id, (Value) ); }
-//static inline int Abc_NodeGetLag( int LValue, int Fi ) { return LValue/Fi - (int)(LValue % Fi == 0); }
-static inline int Abc_NodeGetLag( int LValue, int Fi ) { return (LValue + 256*Fi)/Fi - 256 - (int)(LValue % Fi == 0); }
-
-////////////////////////////////////////////////////////////////////////
-/// MACRO DEFINITIONS ///
-////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////
-/// FUNCTION DEFINITIONS ///
-////////////////////////////////////////////////////////////////////////
-
-// getting the number of the edge for this fanout
-static inline int Abc_ObjEdgeNum( Abc_Obj_t * pObj, Abc_Obj_t * pFanout )
-{
- assert( Abc_NtkIsSeq(pObj->pNtk) );
- if ( Abc_ObjFaninId0(pFanout) == (int)pObj->Id )
- return 0;
- else if ( Abc_ObjFaninId1(pFanout) == (int)pObj->Id )
- return 1;
- assert( 0 );
- return -1;
-}
-
-// getting the latch number of the fanout
-static inline int Abc_ObjFanoutL( Abc_Obj_t * pObj, Abc_Obj_t * pFanout )
-{
- return Abc_ObjFaninL( pFanout, Abc_ObjEdgeNum(pObj,pFanout) );
-}
-
-// setting the latch number of the fanout
-static inline void Abc_ObjSetFanoutL( Abc_Obj_t * pObj, Abc_Obj_t * pFanout, int nLats )
-{
- Abc_ObjSetFaninL( pFanout, Abc_ObjEdgeNum(pObj,pFanout), nLats );
-}
-
-// adding to the latch number of the fanout
-static inline void Abc_ObjAddFanoutL( Abc_Obj_t * pObj, Abc_Obj_t * pFanout, int nLats )
-{
- Abc_ObjAddFaninL( pFanout, Abc_ObjEdgeNum(pObj,pFanout), nLats );
-}
-
-// returns the latch number of the fanout
-static inline int Abc_ObjFanoutLMax( Abc_Obj_t * pObj )
-{
- Abc_Obj_t * pFanout;
- int i, nLatchCur, nLatchRes;
- if ( Abc_ObjFanoutNum(pObj) == 0 )
- return 0;
- nLatchRes = 0;
- Abc_ObjForEachFanout( pObj, pFanout, i )
- {
- nLatchCur = Abc_ObjFanoutL(pObj, pFanout);
- if ( nLatchRes < nLatchCur )
- nLatchRes = nLatchCur;
- }
- assert( nLatchRes >= 0 );
- return nLatchRes;
-}
-
-// returns the latch number of the fanout
-static inline int Abc_ObjFanoutLMin( Abc_Obj_t * pObj )
-{
- Abc_Obj_t * pFanout;
- int i, nLatchCur, nLatchRes;
- if ( Abc_ObjFanoutNum(pObj) == 0 )
- return 0;
- nLatchRes = ABC_INFINITY;
- Abc_ObjForEachFanout( pObj, pFanout, i )
- {
- nLatchCur = Abc_ObjFanoutL(pObj, pFanout);
- if ( nLatchRes > nLatchCur )
- nLatchRes = nLatchCur;
- }
- assert( nLatchRes < ABC_INFINITY );
- return nLatchRes;
-}
-
-// returns the sum of latches on the fanout edges
-static inline int Abc_ObjFanoutLSum( Abc_Obj_t * pObj )
-{
- Abc_Obj_t * pFanout;
- int i, nSum = 0;
- Abc_ObjForEachFanout( pObj, pFanout, i )
- nSum += Abc_ObjFanoutL(pObj, pFanout);
- return nSum;
-}
-
-// returns the sum of latches on the fanin edges
-static inline int Abc_ObjFaninLSum( Abc_Obj_t * pObj )
-{
- Abc_Obj_t * pFanin;
- int i, nSum = 0;
- Abc_ObjForEachFanin( pObj, pFanin, i )
- nSum += Abc_ObjFaninL(pObj, i);
- return nSum;
-}
-
-
-// getting the bit-string of init values of the edge
-static inline unsigned Abc_ObjFaninLGetInit( Abc_Obj_t * pObj, int Edge )
-{
- return (unsigned)Vec_IntEntry( pObj->pNtk->vInits, 2 * pObj->Id + Edge );
-}
-
-// setting bit-string of init values of the edge
-static inline void Abc_ObjFaninLSetInit( Abc_Obj_t * pObj, int Edge, unsigned Init )
-{
- Vec_IntWriteEntry( pObj->pNtk->vInits, 2 * pObj->Id + Edge, Init );
-}
-
-// getting the init value of the given latch on the edge
-static inline Abc_InitType_t Abc_ObjFaninLGetInitOne( Abc_Obj_t * pObj, int Edge, int iLatch )
-{
- return 0x3 & (Abc_ObjFaninLGetInit(pObj, Edge) >> (2*iLatch));
-}
-
-// setting the init value of the given latch on the edge
-static inline void Abc_ObjFaninLSetInitOne( Abc_Obj_t * pObj, int Edge, int iLatch, Abc_InitType_t Init )
-{
- unsigned EntryCur = Abc_ObjFaninLGetInit(pObj, Edge);
- unsigned EntryNew = (EntryCur & ~(0x3 << (2*iLatch))) | (Init << (2*iLatch));
- assert( iLatch < Abc_ObjFaninL(pObj, Edge) );
- Abc_ObjFaninLSetInit( pObj, Edge, EntryNew );
-}
-
-// geting the init value of the first latch on the edge
-static inline Abc_InitType_t Abc_ObjFaninLGetInitFirst( Abc_Obj_t * pObj, int Edge )
-{
- return 0x3 & Abc_ObjFaninLGetInit( pObj, Edge );
-}
-
-// geting the init value of the last latch on the edge
-static inline Abc_InitType_t Abc_ObjFaninLGetInitLast( Abc_Obj_t * pObj, int Edge )
-{
- assert( Abc_ObjFaninL(pObj, Edge) > 0 );
- return 0x3 & (Abc_ObjFaninLGetInit(pObj, Edge) >> (2 * (Abc_ObjFaninL(pObj, Edge) - 1)));
-}
-
-// insert the first latch on the edge
-static inline void Abc_ObjFaninLInsertFirst( Abc_Obj_t * pObj, int Edge, Abc_InitType_t Init )
-{
- unsigned EntryCur = Abc_ObjFaninLGetInit(pObj, Edge);
- unsigned EntryNew = ((EntryCur << 2) | Init);
- assert( Init >= 0 && Init < 4 );
- assert( Abc_ObjFaninL(pObj, Edge) < ABC_MAX_EDGE_LATCH );
- Abc_ObjFaninLSetInit( pObj, Edge, EntryNew );
- Abc_ObjAddFaninL( pObj, Edge, 1 );
-}
-
-// insert the last latch on the edge
-static inline void Abc_ObjFaninLInsertLast( Abc_Obj_t * pObj, int Edge, Abc_InitType_t Init )
-{
- unsigned EntryCur = Abc_ObjFaninLGetInit(pObj, Edge);
- unsigned EntryNew = EntryCur | (Init << (2 * Abc_ObjFaninL(pObj, Edge)));
- assert( Init >= 0 && Init < 4 );
- assert( Abc_ObjFaninL(pObj, Edge) < ABC_MAX_EDGE_LATCH );
- if ( Abc_ObjFaninL(pObj, Edge) >= ABC_MAX_EDGE_LATCH )
- printf( "The limit on latched on the edge (%d) is exceeded.\n", ABC_MAX_EDGE_LATCH );
- Abc_ObjFaninLSetInit( pObj, Edge, EntryNew );
- Abc_ObjAddFaninL( pObj, Edge, 1 );
-}
-
-// delete the first latch on the edge
-static inline Abc_InitType_t Abc_ObjFaninLDeleteFirst( Abc_Obj_t * pObj, int Edge )
-{
- unsigned EntryCur = Abc_ObjFaninLGetInit(pObj, Edge);
- Abc_InitType_t Init = 0x3 & EntryCur;
- unsigned EntryNew = EntryCur >> 2;
- assert( Abc_ObjFaninL(pObj, Edge) > 0 );
- Abc_ObjFaninLSetInit( pObj, Edge, EntryNew );
- Abc_ObjAddFaninL( pObj, Edge, -1 );
- return Init;
-}
-
-// delete the last latch on the edge
-static inline Abc_InitType_t Abc_ObjFaninLDeleteLast( Abc_Obj_t * pObj, int Edge )
-{
- unsigned EntryCur = Abc_ObjFaninLGetInit(pObj, Edge);
- Abc_InitType_t Init = 0x3 & (EntryCur >> (2 * (Abc_ObjFaninL(pObj, Edge) - 1)));
- unsigned EntryNew = EntryCur & ~(((unsigned)0x3) << (2 * (Abc_ObjFaninL(pObj, Edge)-1)));
- assert( Abc_ObjFaninL(pObj, Edge) > 0 );
- Abc_ObjFaninLSetInit( pObj, Edge, EntryNew );
- Abc_ObjAddFaninL( pObj, Edge, -1 );
- return Init;
-}
-
-// retime node forward without initial states
-static inline void Abc_ObjRetimeForwardTry( Abc_Obj_t * pObj, int nLatches )
-{
- Abc_Obj_t * pFanout;
- int i;
- // make sure it is an AND gate
- assert( Abc_ObjFaninNum(pObj) == 2 );
- // make sure it has enough latches
-// assert( Abc_ObjFaninL0(pObj) >= nLatches );
-// assert( Abc_ObjFaninL1(pObj) >= nLatches );
- // subtract these latches on the fanin side
- Abc_ObjAddFaninL0( pObj, -nLatches );
- Abc_ObjAddFaninL1( pObj, -nLatches );
- // add these latches on the fanout size
- Abc_ObjForEachFanout( pObj, pFanout, i )
- Abc_ObjAddFanoutL( pObj, pFanout, nLatches );
-}
-
-// retime node backward without initial states
-static inline void Abc_ObjRetimeBackwardTry( Abc_Obj_t * pObj, int nLatches )
-{
- Abc_Obj_t * pFanout;
- int i;
- // make sure it is an AND gate
- assert( Abc_ObjFaninNum(pObj) == 2 );
- // subtract these latches on the fanout side
- Abc_ObjForEachFanout( pObj, pFanout, i )
- {
-// assert( Abc_ObjFanoutL(pObj, pFanout) >= nLatches );
- Abc_ObjAddFanoutL( pObj, pFanout, -nLatches );
- }
- // add these latches on the fanin size
- Abc_ObjAddFaninL0( pObj, nLatches );
- Abc_ObjAddFaninL1( pObj, nLatches );
-}
-
-
-////////////////////////////////////////////////////////////////////////
-/// ITERATORS ///
-////////////////////////////////////////////////////////////////////////
-
-// iterating through the initial values of the edge
-#define Abc_ObjFaninLForEachValue( pObj, Edge, Init, i, Value ) \
- for ( i = 0, Init = Abc_ObjFaninLGetInit(pObj, Edge); \
- i < Abc_ObjFaninL(pObj, Edge) && ((Value = ((Init >> (2*i)) & 0x3)), 1); i++ )
-
-////////////////////////////////////////////////////////////////////////
-/// FUNCTION DECLARATIONS ///
-////////////////////////////////////////////////////////////////////////
-
-/*=== abcRetCore.c ===========================================================*/
-extern void Abc_NtkSeqRetimeForward( Abc_Ntk_t * pNtk, int fVerbose );
-extern void Abc_NtkSeqRetimeBackward( Abc_Ntk_t * pNtk, int fVerbose );
-extern void Abc_NtkSeqRetimeInitial( Abc_Ntk_t * pNtk, int fVerbose );
-extern void Abc_NtkSeqRetimeDelay( Abc_Ntk_t * pNtk, int fVerbose );
-/*=== abcRetDelay.c ==========================================================*/
-extern Vec_Str_t * Abc_NtkSeqRetimeDelayLags( Abc_Ntk_t * pNtk, int fVerbose );
-/*=== abcRetImpl.c ===========================================================*/
-extern int Abc_NtkImplementRetiming( Abc_Ntk_t * pNtk, Vec_Str_t * vLags, int fVerbose );
-extern void Abc_NtkImplementRetimingForward( Abc_Ntk_t * pNtk, Vec_Ptr_t * vMoves );
-extern int Abc_NtkImplementRetimingBackward( Abc_Ntk_t * pNtk, Vec_Ptr_t * vMoves, int fVerbose );
-/*=== abcRetUtil.c ===========================================================*/
-extern Vec_Ptr_t * Abc_NtkUtilRetimingTry( Abc_Ntk_t * pNtk, bool fForward );
-extern Vec_Ptr_t * Abc_NtkUtilRetimingGetMoves( Abc_Ntk_t * pNtk, Vec_Int_t * vNodes, bool fForward );
-extern Vec_Int_t * Abc_NtkUtilRetimingSplit( Vec_Str_t * vLags, int fForward );
-/*=== abcSeq.c ===============================================================*/
-extern Abc_Ntk_t * Abc_NtkAigToSeq( Abc_Ntk_t * pNtk );
-extern Abc_Ntk_t * Abc_NtkSeqToLogicSop( Abc_Ntk_t * pNtk );
-/*=== abcShare.c =============================================================*/
-extern void Abc_NtkSeqShareFanouts( Abc_Ntk_t * pNtk );
-/*=== abcUtil.c ==============================================================*/
-extern int Abc_NtkSeqLatchNum( Abc_Ntk_t * pNtk );
-extern int Abc_NtkSeqLatchNumShared( Abc_Ntk_t * pNtk );
-extern void Abc_NtkSeqLatchGetInitNums( Abc_Ntk_t * pNtk, int * pInits );
-extern char * Abc_ObjFaninGetInitPrintable( Abc_Obj_t * pObj, int Edge );
-
-////////////////////////////////////////////////////////////////////////
-/// END OF FILE ///
-////////////////////////////////////////////////////////////////////////
-
-#endif
-
diff --git a/src/base/abcs/module.make b/src/base/abcs/module.make
deleted file mode 100644
index e8d5a8db..00000000
--- a/src/base/abcs/module.make
+++ /dev/null
@@ -1,9 +0,0 @@
-SRC += src/base/abcs/abcFpgaDelay.c \
- src/base/abcs/abcFpgaSeq.c \
- src/base/abcs/abcRetCore.c \
- src/base/abcs/abcRetDelay.c \
- src/base/abcs/abcRetImpl.c \
- src/base/abcs/abcRetUtil.c \
- src/base/abcs/abcSeq.c \
- src/base/abcs/abcShare.c \
- src/base/abcs/abcUtils.c
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