diff options
Diffstat (limited to 'src/base/io/ioReadVerilog.c')
| -rw-r--r-- | src/base/io/ioReadVerilog.c | 35 |
1 files changed, 9 insertions, 26 deletions
diff --git a/src/base/io/ioReadVerilog.c b/src/base/io/ioReadVerilog.c index 090cf254..c64e330c 100644 --- a/src/base/io/ioReadVerilog.c +++ b/src/base/io/ioReadVerilog.c @@ -45,14 +45,21 @@ Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck ) { Abc_Ntk_t * pNtk; Abc_Lib_t * pDesign; + int RetValue; // parse the verilog file pDesign = Ver_ParseFile( pFileName, NULL, fCheck, 1 ); if ( pDesign == NULL ) return NULL; -/* + + // detect top-level model + RetValue = Abc_LibFindTopLevelModels( pDesign ); + pNtk = Vec_PtrEntry( pDesign->vTops, 0 ); + if ( RetValue > 1 ) + printf( "Warning: The design has %d root-level modules. The first one (%s) will be used.\n", + Vec_PtrSize(pDesign->vTops), pNtk->pName ); + // extract the master network - pNtk = Vec_PtrEntryLast( pDesign->vModules ); pNtk->pDesign = pDesign; pDesign->pManFunc = NULL; @@ -67,35 +74,11 @@ Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck ) } else { - // bring the root model to the beginning - for ( i = Vec_PtrSize(pDesign->vModules) - 2; i >= 0; i-- ) - Vec_PtrWriteEntry(pDesign->vModules, i+1, Vec_PtrEntry(pDesign->vModules, i) ); - Vec_PtrWriteEntry(pDesign->vModules, 0, pNtk ); // check that there is no cyclic dependency Abc_NtkIsAcyclicHierarchy( pNtk ); } -*/ - // extract the master network - pNtk = Vec_PtrEntry( pDesign->vModules, 0 ); - pNtk->pDesign = pDesign; - pDesign->pManFunc = NULL; //Io_WriteVerilog( pNtk, "_temp.v" ); - - // verify the design for cyclic dependence - assert( Vec_PtrSize(pDesign->vModules) > 0 ); - if ( Vec_PtrSize(pDesign->vModules) == 1 ) - { -// printf( "Warning: The design is not hierarchical.\n" ); - Abc_LibFree( pDesign, pNtk ); - pNtk->pDesign = NULL; - pNtk->pSpec = Extra_UtilStrsav( pFileName ); - } - else - { - // check that there is no cyclic dependency - Abc_NtkIsAcyclicHierarchy( pNtk ); - } return pNtk; } |