8 files changed, 13 insertions, 12 deletions
diff --git a/src/base/io/io.c b/src/base/io/io.c
index 1fe73690..9ffbc3cf 100644
--- a/src/base/io/io.c
+++ b/src/base/io/io.c
@@ -604,7 +604,7 @@ int IoCommandWriteBlif( Abc_Frame_t * pAbc, int argc, char **argv )
     FileName = argv[util_optind];
 
     // check the network type
-    if ( !Abc_NtkIsLogic(pNtk) && !Abc_NtkIsAig(pNtk) && !Abc_NtkIsSeq(pNtk) )
+    if ( !Abc_NtkIsLogic(pNtk) && !Abc_NtkIsStrash(pNtk) && !Abc_NtkIsSeq(pNtk) )
     {
         fprintf( pAbc->Out, "Currently can only write logic networks, AIGs, and seq AIGs.\n" );
         return 0;
@@ -670,7 +670,7 @@ int IoCommandWriteBench( Abc_Frame_t * pAbc, int argc, char **argv )
     // get the input file name
     FileName = argv[util_optind];
 
-    if ( !Abc_NtkIsAig(pNtk) )
+    if ( !Abc_NtkIsStrash(pNtk) )
     {
         fprintf( pAbc->Out, "The network should be an AIG.\n" );
         return 0;
diff --git a/src/base/io/ioReadBlif.c b/src/base/io/ioReadBlif.c
index f598c4e5..b5dc2fa8 100644
--- a/src/base/io/ioReadBlif.c
+++ b/src/base/io/ioReadBlif.c
@@ -292,12 +292,12 @@ Abc_Ntk_t * Io_ReadBlifNetwork( Io_ReadBlif_t * p )
         }
         pModelName = vTokens->pArray[1];
         // allocate the empty network
-        p->pNtk = Abc_NtkAlloc( ABC_NTK_NETLIST_SOP );
+        p->pNtk = Abc_NtkAlloc( ABC_TYPE_NETLIST, ABC_FUNC_SOP );
         p->pNtk->pName = util_strsav( pModelName );
         p->pNtk->pSpec = util_strsav( p->pFileName );
     }
     else
-        p->pNtk = Abc_NtkAlloc( ABC_NTK_NETLIST_SOP );
+        p->pNtk = Abc_NtkAlloc( ABC_TYPE_NETLIST, ABC_FUNC_SOP );
 
     // read the inputs/outputs
     pProgress = Extra_ProgressBarStart( stdout, Extra_FileReaderGetFileSize(p->pReader) );
@@ -581,8 +581,8 @@ int Io_ReadBlifNetworkGate( Io_ReadBlif_t * p, Vec_Ptr_t * vTokens )
     // if this is the first line with gate, update the network type
     if ( Abc_NtkNodeNum(p->pNtk) == 0 )
     {
-        assert( p->pNtk->Type = ABC_NTK_NETLIST_SOP );
-        p->pNtk->Type = ABC_NTK_NETLIST_MAP;
+        assert( p->pNtk->ntkFunc == ABC_FUNC_SOP );
+        p->pNtk->ntkFunc = ABC_FUNC_MAP;
         Extra_MmFlexStop( p->pNtk->pManFunc, 0 );
         p->pNtk->pManFunc = pGenlib;
     }
diff --git a/src/base/io/ioReadVerilog.c b/src/base/io/ioReadVerilog.c
index 936a1c0c..53299a0c 100644
--- a/src/base/io/ioReadVerilog.c
+++ b/src/base/io/ioReadVerilog.c
@@ -271,7 +271,7 @@ Abc_Ntk_t * Io_ReadVerNetwork( Io_ReadVer_t * p )
     pModelName = vTokens->pArray[1];
 
     // allocate the empty network
-    pNtk = Abc_NtkAlloc( ABC_NTK_NETLIST_SOP );
+    pNtk = Abc_NtkAlloc( ABC_TYPE_NETLIST, ABC_FUNC_SOP );
     pNtk->pName = util_strsav( pModelName );
     pNtk->pSpec = util_strsav( p->pFileName );
 
diff --git a/src/base/io/ioWriteBench.c b/src/base/io/ioWriteBench.c
index 7c4a4ab1..df79227d 100644
--- a/src/base/io/ioWriteBench.c
+++ b/src/base/io/ioWriteBench.c
@@ -46,7 +46,7 @@ int Io_WriteBench( Abc_Ntk_t * pNtk, char * pFileName )
 {
     Abc_Ntk_t * pExdc;
     FILE * pFile;
-    assert( Abc_NtkIsNetlistSop(pNtk) );
+    assert( Abc_NtkIsSopNetlist(pNtk) );
     pFile = fopen( pFileName, "w" );
     if ( pFile == NULL )
     {
diff --git a/src/base/io/ioWriteBlif.c b/src/base/io/ioWriteBlif.c
index 5c83aad2..5135105f 100644
--- a/src/base/io/ioWriteBlif.c
+++ b/src/base/io/ioWriteBlif.c
@@ -320,7 +320,7 @@ void Io_NtkWriteLatch( FILE * pFile, Abc_Obj_t * pLatch )
 ***********************************************************************/
 void Io_NtkWriteNode( FILE * pFile, Abc_Obj_t * pNode )
 {
-    if ( Abc_NtkIsNetlistMap(pNode->pNtk) )
+    if ( Abc_NtkHasMapping(pNode->pNtk) )
     {
         // write the .gate line
         fprintf( pFile, ".gate" );
diff --git a/src/base/io/ioWriteCnf.c b/src/base/io/ioWriteCnf.c
index 144ff167..bb216bb6 100644
--- a/src/base/io/ioWriteCnf.c
+++ b/src/base/io/ioWriteCnf.c
@@ -44,9 +44,9 @@ static void Io_WriteCnfInt( FILE * pFile, Abc_Ntk_t * pNtk );
 int Io_WriteCnf( Abc_Ntk_t * pNtk, char * pFileName )
 {
     solver * pSat;
-    if ( !Abc_NtkIsLogicBdd(pNtk) )
+    if ( !Abc_NtkIsBddLogic(pNtk) )
     {
-        fprintf( stdout, "Io_WriteCnf(): Currently can process logic networks with BDDs.\n" );
+        fprintf( stdout, "Io_WriteCnf(): Currently can only process logic networks with BDDs.\n" );
         return 0;
     }
     if ( Abc_NtkPoNum(pNtk) != 1 )
diff --git a/src/base/io/ioWritePla.c b/src/base/io/ioWritePla.c
index 9c78b149..25a68978 100644
--- a/src/base/io/ioWritePla.c
+++ b/src/base/io/ioWritePla.c
@@ -46,7 +46,7 @@ int Io_WritePla( Abc_Ntk_t * pNtk, char * pFileName )
     Abc_Ntk_t * pExdc;
     FILE * pFile;
 
-    assert( Abc_NtkIsNetlistSop(pNtk) );
+    assert( Abc_NtkIsSopNetlist(pNtk) );
     assert( Abc_NtkGetLevelNum(pNtk) == 1 );
 
     pFile = fopen( pFileName, "w" );
diff --git a/src/base/io/module.make b/src/base/io/module.make
index 899f8166..cb39c481 100644
--- a/src/base/io/module.make
+++ b/src/base/io/module.make
@@ -2,6 +2,7 @@ SRC +=  src/base/io/io.c \
     src/base/io/ioRead.c \
     src/base/io/ioReadBench.c \
     src/base/io/ioReadBlif.c \
+    src/base/io/ioReadEdif.c \
     src/base/io/ioReadPla.c \
     src/base/io/ioReadVerilog.c \
     src/base/io/ioUtil.c \