diff options
Diffstat (limited to 'src/base/io')
| -rw-r--r-- | src/base/io/io.h | 3 | ||||
| -rw-r--r-- | src/base/io/ioReadBlifMv.c | 209 | ||||
| -rw-r--r-- | src/base/io/ioReadVerilog.c | 35 | ||||
| -rw-r--r-- | src/base/io/ioUtil.c | 194 | ||||
| -rw-r--r-- | src/base/io/ioWriteAiger.c | 4 | ||||
| -rw-r--r-- | src/base/io/ioWriteBlif.c | 16 | ||||
| -rw-r--r-- | src/base/io/ioWriteBlifMv.c | 81 | ||||
| -rw-r--r-- | src/base/io/ioWriteDot.c | 4 |
8 files changed, 278 insertions, 268 deletions
diff --git a/src/base/io/io.h b/src/base/io/io.h index 472e7b2d..7e23b6e4 100644 --- a/src/base/io/io.h +++ b/src/base/io/io.h @@ -95,8 +95,7 @@ extern void Io_WriteBlifLogic( Abc_Ntk_t * pNtk, char * pFileName, extern void Io_WriteBlif( Abc_Ntk_t * pNtk, char * pFileName, int fWriteLatches ); extern void Io_WriteTimingInfo( FILE * pFile, Abc_Ntk_t * pNtk ); /*=== abcWriteBlifMv.c ==========================================================*/ -extern void Io_WriteBlifMvDesign( Abc_Lib_t * pLib, char * FileName ); -extern void Io_WriteBlifMvNetlist( Abc_Ntk_t * pNtk, char * FileName ); +extern void Io_WriteBlifMv( Abc_Ntk_t * pNtk, char * FileName ); /*=== abcWriteBench.c =========================================================*/ extern int Io_WriteBench( Abc_Ntk_t * pNtk, char * FileName ); /*=== abcWriteCnf.c ===========================================================*/ diff --git a/src/base/io/ioReadBlifMv.c b/src/base/io/ioReadBlifMv.c index 3e09caf0..dc72c591 100644 --- a/src/base/io/ioReadBlifMv.c +++ b/src/base/io/ioReadBlifMv.c @@ -62,11 +62,13 @@ struct Io_MvMan_t_ { // general info about file int fBlifMv; // the file is BLIF-MV + int fUseReset; // the reset circuitry is added char * pFileName; // the name of the file char * pBuffer; // the contents of the file Vec_Ptr_t * vLines; // the line beginnings // the results of reading Abc_Lib_t * pDesign; // the design under construction + int nNDnodes; // the counter of ND nodes // intermediate storage for models Vec_Ptr_t * vModels; // vector of models Io_MvMod_t * pLatest; // the current model @@ -99,6 +101,7 @@ static int Io_MvParseLineMv( Io_MvMod_t * p, char * pLine ); static int Io_MvParseLineNamesMv( Io_MvMod_t * p, char * pLine, int fReset ); static int Io_MvParseLineNamesBlif( Io_MvMod_t * p, char * pLine ); static int Io_MvParseLineGateBlif( Io_MvMod_t * p, Vec_Ptr_t * vTokens ); +static Io_MvVar_t * Abc_NtkMvVarDup( Abc_Ntk_t * pNtk, Io_MvVar_t * pVar ); static int Io_MvCharIsSpace( char s ) { return s == ' ' || s == '\t' || s == '\r' || s == '\n'; } static int Io_MvCharIsMvSymb( char s ) { return s == '(' || s == ')' || s == '{' || s == '}' || s == '-' || s == ',' || s == '!'; } @@ -127,7 +130,7 @@ Abc_Ntk_t * Io_ReadBlifMv( char * pFileName, int fBlifMv, int fCheck ) Abc_Ntk_t * pNtk; Abc_Lib_t * pDesign; char * pDesignName; - int i; + int RetValue, i; // check that the file is available pFile = fopen( pFileName, "rb" ); @@ -141,6 +144,7 @@ Abc_Ntk_t * Io_ReadBlifMv( char * pFileName, int fBlifMv, int fCheck ) // start the file reader p = Io_MvAlloc(); p->fBlifMv = fBlifMv; + p->fUseReset = 0; p->pFileName = pFileName; p->pBuffer = Io_MvLoadFile( pFileName ); if ( p->pBuffer == NULL ) @@ -152,6 +156,9 @@ Abc_Ntk_t * Io_ReadBlifMv( char * pFileName, int fBlifMv, int fCheck ) pDesignName = Extra_FileNameGeneric( pFileName ); p->pDesign = Abc_LibCreate( pDesignName ); free( pDesignName ); + // free the HOP manager + Hop_ManStop( p->pDesign->pManFunc ); + p->pDesign->pManFunc = NULL; // prepare the file for parsing Io_MvReadPreparse( p ); // parse interfaces of each network @@ -163,6 +170,7 @@ Abc_Ntk_t * Io_ReadBlifMv( char * pFileName, int fBlifMv, int fCheck ) if ( pDesign == NULL ) return NULL; Io_MvFree( p ); +// pDesign should be linked to all models of the design // make sure that everything is okay with the network structure if ( fCheck ) @@ -177,11 +185,19 @@ Abc_Ntk_t * Io_ReadBlifMv( char * pFileName, int fBlifMv, int fCheck ) } } } -// pDesign should be linked to all models of the design + +//Abc_LibPrint( pDesign ); + + // detect top-level model + RetValue = Abc_LibFindTopLevelModels( pDesign ); + pNtk = Vec_PtrEntry( pDesign->vTops, 0 ); + if ( RetValue > 1 ) + printf( "Warning: The design has %d root-level modules. The first one (%s) will be used.\n", + Vec_PtrSize(pDesign->vTops), pNtk->pName ); // extract the master network - pNtk = Vec_PtrEntry( pDesign->vModules, 0 ); pNtk->pDesign = pDesign; + pDesign->pManFunc = NULL; // verify the design for cyclic dependence assert( Vec_PtrSize(pDesign->vModules) > 0 ); @@ -195,10 +211,7 @@ Abc_Ntk_t * Io_ReadBlifMv( char * pFileName, int fBlifMv, int fCheck ) else Abc_NtkIsAcyclicHierarchy( pNtk ); -//Io_WriteBlifMvDesign( pDesign, "_temp_.mv" ); -//Abc_LibPrint( pDesign ); -//Abc_LibFree( pDesign ); -//return NULL; +//Io_WriteBlifMv( pNtk, "_temp_.mv" ); return pNtk; } @@ -691,16 +704,18 @@ static Abc_Lib_t * Io_MvParse( Io_MvMan_t * p ) return NULL; } // create binary latch with 1-data and 0-init - pMod->pResetLatch = Io_ReadCreateResetLatch( pMod->pNtk, p->fBlifMv ); + if ( p->fUseReset ) + pMod->pResetLatch = Io_ReadCreateResetLatch( pMod->pNtk, p->fBlifMv ); } // parse the latches Vec_PtrForEachEntry( pMod->vLatches, pLine, k ) if ( !Io_MvParseLineLatch( pMod, pLine ) ) return NULL; // parse the reset lines - Vec_PtrForEachEntry( pMod->vResets, pLine, k ) - if ( !Io_MvParseLineNamesMv( pMod, pLine, 1 ) ) - return NULL; + if ( p->fUseReset ) + Vec_PtrForEachEntry( pMod->vResets, pLine, k ) + if ( !Io_MvParseLineNamesMv( pMod, pLine, 1 ) ) + return NULL; // parse the nodes if ( p->fBlifMv ) { @@ -721,6 +736,9 @@ static Abc_Lib_t * Io_MvParse( Io_MvMan_t * p ) // finalize the network Abc_NtkFinalizeRead( pMod->pNtk ); } + if ( p->nNDnodes ) +// printf( "Warning: The parser added %d PIs to replace non-deterministic nodes.\n", p->nNDnodes ); + printf( "Warning: The parser added %d constant 0 nodes to replace non-deterministic nodes.\n", p->nNDnodes ); // return the network pDesign = p->pDesign; p->pDesign = NULL; @@ -822,7 +840,7 @@ static int Io_MvParseLineOutputs( Io_MvMod_t * p, char * pLine ) static int Io_MvParseLineLatch( Io_MvMod_t * p, char * pLine ) { Vec_Ptr_t * vTokens = p->pMan->vTokens; - Abc_Obj_t * pObj, * pMux, * pNet; + Abc_Obj_t * pObj, * pNet; char * pToken; int Init; Io_MvSplitIntoTokens( vTokens, pLine, '\0' ); @@ -838,33 +856,35 @@ static int Io_MvParseLineLatch( Io_MvMod_t * p, char * pLine ) { pObj = Io_ReadCreateLatch( p->pNtk, Vec_PtrEntry(vTokens,1), Vec_PtrEntry(vTokens,2) ); // get initial value - if ( Vec_PtrSize(vTokens) > 3 ) - Init = atoi( Vec_PtrEntry(vTokens,3) ); + if ( p->pMan->fBlifMv ) + Abc_LatchSetInit0( pObj ); else - Init = 2; - if ( Init < 0 || Init > 2 ) { - sprintf( p->pMan->sError, "Line %d: Initial state of the latch is incorrect \"%s\".", Io_MvGetLine(p->pMan, pToken), Vec_PtrEntry(vTokens,3) ); - return 0; + if ( Vec_PtrSize(vTokens) > 3 ) + Init = atoi( Vec_PtrEntry(vTokens,3) ); + else + Init = 2; + if ( Init < 0 || Init > 2 ) + { + sprintf( p->pMan->sError, "Line %d: Initial state of the latch is incorrect \"%s\".", Io_MvGetLine(p->pMan, pToken), Vec_PtrEntry(vTokens,3) ); + return 0; + } + if ( Init == 0 ) + Abc_LatchSetInit0( pObj ); + else if ( Init == 1 ) + Abc_LatchSetInit1( pObj ); + else // if ( Init == 2 ) + Abc_LatchSetInitDc( pObj ); } - if ( Init == 0 ) - Abc_LatchSetInit0( pObj ); - else if ( Init == 1 ) - Abc_LatchSetInit1( pObj ); - else // if ( Init == 2 ) - Abc_LatchSetInitDc( pObj ); } else { - // get the net corresponding to output of reset latch - pNet = Abc_ObjFanout0(Abc_ObjFanout0(p->pResetLatch)); - assert( Abc_ObjIsNet(pNet) ); - // create mux - pMux = Io_ReadCreateResetMux( p->pNtk, Abc_ObjName(pNet), Vec_PtrEntry(vTokens,1), p->pMan->fBlifMv ); - // get the net of mux output - pNet = Abc_ObjFanout0(pMux); + // get the net corresponding to the output of the latch + pNet = Abc_NtkFindOrCreateNet( p->pNtk, Vec_PtrEntry(vTokens,2) ); + // get the net corresponding to the latch output (feeding into reset MUX) + pNet = Abc_NtkFindOrCreateNet( p->pNtk, Abc_ObjNameSuffix(pNet, "_out") ); // create latch - pObj = Io_ReadCreateLatch( p->pNtk, Abc_ObjName(pNet), Vec_PtrEntry(vTokens,2) ); + pObj = Io_ReadCreateLatch( p->pNtk, Vec_PtrEntry(vTokens,1), Abc_ObjName(pNet) ); Abc_LatchSetInit0( pObj ); } return 1; @@ -1180,7 +1200,7 @@ static char * Io_MvParseTableMv( Io_MvMod_t * p, Abc_Obj_t * pNode, Vec_Ptr_t * // prepare the place for the cover Vec_StrClear( vFunc ); // write the number of values - Io_MvWriteValues( pNode, vFunc ); +// Io_MvWriteValues( pNode, vFunc ); // get the first token pFirst = Vec_PtrEntry( vTokens2, 0 ); if ( pFirst[0] == '.' ) @@ -1217,6 +1237,60 @@ static char * Io_MvParseTableMv( Io_MvMod_t * p, Abc_Obj_t * pNode, Vec_Ptr_t * /**Function************************************************************* + Synopsis [Adds reset circuitry corresponding to latch with pName.] + + Description [Returns the reset node's net.] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ +static Abc_Obj_t * Io_MvParseAddResetCircuit( Io_MvMod_t * p, char * pName ) +{ + char Buffer[50]; + Abc_Obj_t * pNode, * pData0Net, * pData1Net, * pResetLONet, * pOutNet; + Io_MvVar_t * pVar; + // make sure the reset latch exists + assert( p->pResetLatch != NULL ); + // get the reset net + pResetLONet = Abc_ObjFanout0(Abc_ObjFanout0(p->pResetLatch)); + // get the output net + pOutNet = Abc_NtkFindOrCreateNet( p->pNtk, pName ); + // get the data nets + pData0Net = Abc_NtkFindOrCreateNet( p->pNtk, Abc_ObjNameSuffix(pOutNet, "_reset") ); + pData1Net = Abc_NtkFindOrCreateNet( p->pNtk, Abc_ObjNameSuffix(pOutNet, "_out") ); + // duplicate MV variables + if ( Abc_NtkMvVar(p->pNtk) ) + { + pVar = Abc_ObjMvVar( pOutNet ); + Abc_ObjSetMvVar( pData0Net, Abc_NtkMvVarDup(p->pNtk, pVar) ); + Abc_ObjSetMvVar( pData1Net, Abc_NtkMvVarDup(p->pNtk, pVar) ); + } + // create the node + pNode = Abc_NtkCreateNode( p->pNtk ); + // create the output net + Abc_ObjAddFanin( pOutNet, pNode ); + // create the function + if ( p->pMan->fBlifMv ) + { +// Vec_Att_t * p = Abc_NtkMvVar( pNtk ); + int nValues = Abc_ObjMvVarNum(pOutNet); +// sprintf( Buffer, "2 %d %d %d\n1 - - =1\n0 - - =2\n", nValues, nValues, nValues ); + sprintf( Buffer, "1 - - =1\n0 - - =2\n" ); + pNode->pData = Abc_SopRegister( p->pNtk->pManFunc, Buffer ); + } + else + pNode->pData = Abc_SopCreateMux( p->pNtk->pManFunc ); + // add nets + Abc_ObjAddFanin( pNode, pResetLONet ); + Abc_ObjAddFanin( pNode, pData1Net ); + Abc_ObjAddFanin( pNode, pData0Net ); + return pData0Net; +} + +/**Function************************************************************* + Synopsis [Parses the nodes line.] Description [] @@ -1241,19 +1315,15 @@ static int Io_MvParseLineNamesMvOne( Io_MvMod_t * p, Vec_Ptr_t * vTokens, Vec_Pt sprintf( p->pMan->sError, "Line %d: Latch with output signal \"%s\" does not exist.", Io_MvGetLine(p->pMan, pName), pName ); return 0; } +/* if ( !Abc_ObjIsBo(Abc_ObjFanin0(pNet)) ) { sprintf( p->pMan->sError, "Line %d: Reset line \"%s\" defines signal that is not a latch output.", Io_MvGetLine(p->pMan, pName), pName ); return 0; } - // get the latch input - pNode = Abc_ObjFanin0(Abc_ObjFanin0(Abc_ObjFanin0(pNet))); - assert( Abc_ObjIsBi(pNode) ); - // get the MUX feeding into the latch - pNode = Abc_ObjFanin0(Abc_ObjFanin0(pNode)); - assert( Abc_ObjFaninNum(pNode) == 3 ); - // get the corresponding fanin net - pNet = Abc_ObjFanin( pNode, 2 ); +*/ + // construct the reset circuit and get the reset net feeding into it + pNet = Io_MvParseAddResetCircuit( p, pName ); // create fanins pNode = Io_ReadCreateNode( p->pNtk, Abc_ObjName(pNet), (char **)(vTokens->pArray + 1), nInputs ); assert( nInputs == Vec_PtrSize(vTokens) - 2 ); @@ -1292,6 +1362,7 @@ static int Io_MvParseLineNamesMv( Io_MvMod_t * p, char * pLine, int fReset ) { Vec_Ptr_t * vTokens = p->pMan->vTokens; Vec_Ptr_t * vTokens2 = p->pMan->vTokens2; + Abc_Obj_t * pNet; char * pName, * pFirst, * pArrow; int nInputs, nOutputs, nLiterals, nLines, i; assert( p->pMan->fBlifMv ); @@ -1341,27 +1412,23 @@ static int Io_MvParseLineNamesMv( Io_MvMod_t * p, char * pLine, int fReset ) nLines = nLiterals / (nInputs + nOutputs); if ( nInputs == 0 && nLines > 1 ) { - Abc_Obj_t * pNode, * pNet; // add the outputs to the PIs for ( i = 0; i < nOutputs; i++ ) { pName = Vec_PtrEntry( vTokens, Vec_PtrSize(vTokens) - nOutputs + i ); - fprintf( stdout, "Io_ReadBlifMv(): Adding PI for internal non-deterministic node \"%s\".\n", pName ); // get the net corresponding to this node pNet = Abc_NtkFindOrCreateNet(p->pNtk, pName); if ( fReset ) { - // get the latch input - pNode = Abc_ObjFanin0(Abc_ObjFanin0(Abc_ObjFanin0(pNet))); - assert( Abc_ObjIsBi(pNode) ); - // get the MUX feeding into the latch - pNode = Abc_ObjFanin0(Abc_ObjFanin0(pNode)); - assert( Abc_ObjFaninNum(pNode) == 3 ); - // get the corresponding fanin net - pNet = Abc_ObjFanin( pNode, 2 ); + assert( p->pResetLatch != NULL ); + // construct the reset circuit and get the reset net feeding into it + pNet = Io_MvParseAddResetCircuit( p, pName ); } -// Io_ReadCreatePi( p->pNtk, pName ); - Abc_ObjAddFanin( pNet, Abc_NtkCreatePi(p->pNtk) ); + // add the new PI node +// Abc_ObjAddFanin( pNet, Abc_NtkCreatePi(p->pNtk) ); +// fprintf( stdout, "Io_ReadBlifMv(): Adding PI for internal non-deterministic node \"%s\".\n", pName ); + p->pMan->nNDnodes++; + Abc_ObjAddFanin( pNet, Abc_NtkCreateNodeConst0(p->pNtk) ); } return 1; } @@ -1437,7 +1504,7 @@ static char * Io_MvParseTableBlif( Io_MvMod_t * p, char * pTable, int nFanins ) sprintf( p->pMan->sError, "Line %d: Output value \"%s\" differs from the value in the first line of the table (%d).", Io_MvGetLine(p->pMan, pProduct), pOutput, Polarity ); return NULL; } - // parse one product product + // parse one product Vec_StrAppend( vFunc, pProduct ); Vec_StrPush( vFunc, ' ' ); Vec_StrPush( vFunc, pOutput[0] ); @@ -1487,6 +1554,40 @@ static int Io_MvParseLineNamesBlif( Io_MvMod_t * p, char * pLine ) return 1; } +/**Function************************************************************* + + Synopsis [Duplicate the MV variable.] + + Description [] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ +Io_MvVar_t * Abc_NtkMvVarDup( Abc_Ntk_t * pNtk, Io_MvVar_t * pVar ) +{ + Extra_MmFlex_t * pFlex; + Io_MvVar_t * pVarDup; + int i; + if ( pVar == NULL ) + return NULL; + pFlex = Abc_NtkMvVarMan( pNtk ); + assert( pFlex != NULL ); + pVarDup = (Io_MvVar_t *)Extra_MmFlexEntryFetch( pFlex, sizeof(Io_MvVar_t) ); + pVarDup->nValues = pVar->nValues; + pVarDup->pNames = NULL; + if ( pVar->pNames == NULL ) + return pVarDup; + pVarDup->pNames = (char **)Extra_MmFlexEntryFetch( pFlex, sizeof(char *) * pVar->nValues ); + for ( i = 0; i < pVar->nValues; i++ ) + { + pVarDup->pNames[i] = (char *)Extra_MmFlexEntryFetch( pFlex, strlen(pVar->pNames[i]) + 1 ); + strcpy( pVarDup->pNames[i], pVar->pNames[i] ); + } + return pVarDup; +} + #include "mio.h" #include "main.h" diff --git a/src/base/io/ioReadVerilog.c b/src/base/io/ioReadVerilog.c index 090cf254..c64e330c 100644 --- a/src/base/io/ioReadVerilog.c +++ b/src/base/io/ioReadVerilog.c @@ -45,14 +45,21 @@ Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck ) { Abc_Ntk_t * pNtk; Abc_Lib_t * pDesign; + int RetValue; // parse the verilog file pDesign = Ver_ParseFile( pFileName, NULL, fCheck, 1 ); if ( pDesign == NULL ) return NULL; -/* + + // detect top-level model + RetValue = Abc_LibFindTopLevelModels( pDesign ); + pNtk = Vec_PtrEntry( pDesign->vTops, 0 ); + if ( RetValue > 1 ) + printf( "Warning: The design has %d root-level modules. The first one (%s) will be used.\n", + Vec_PtrSize(pDesign->vTops), pNtk->pName ); + // extract the master network - pNtk = Vec_PtrEntryLast( pDesign->vModules ); pNtk->pDesign = pDesign; pDesign->pManFunc = NULL; @@ -67,35 +74,11 @@ Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck ) } else { - // bring the root model to the beginning - for ( i = Vec_PtrSize(pDesign->vModules) - 2; i >= 0; i-- ) - Vec_PtrWriteEntry(pDesign->vModules, i+1, Vec_PtrEntry(pDesign->vModules, i) ); - Vec_PtrWriteEntry(pDesign->vModules, 0, pNtk ); // check that there is no cyclic dependency Abc_NtkIsAcyclicHierarchy( pNtk ); } -*/ - // extract the master network - pNtk = Vec_PtrEntry( pDesign->vModules, 0 ); - pNtk->pDesign = pDesign; - pDesign->pManFunc = NULL; //Io_WriteVerilog( pNtk, "_temp.v" ); - - // verify the design for cyclic dependence - assert( Vec_PtrSize(pDesign->vModules) > 0 ); - if ( Vec_PtrSize(pDesign->vModules) == 1 ) - { -// printf( "Warning: The design is not hierarchical.\n" ); - Abc_LibFree( pDesign, pNtk ); - pNtk->pDesign = NULL; - pNtk->pSpec = Extra_UtilStrsav( pFileName ); - } - else - { - // check that there is no cyclic dependency - Abc_NtkIsAcyclicHierarchy( pNtk ); - } return pNtk; } diff --git a/src/base/io/ioUtil.c b/src/base/io/ioUtil.c index 0ac3181a..9845fbab 100644 --- a/src/base/io/ioUtil.c +++ b/src/base/io/ioUtil.c @@ -173,27 +173,6 @@ Abc_Ntk_t * Io_Read( char * pFileName, Io_FileType_t FileType, int fCheck ) return NULL; if ( !Abc_NtkIsNetlist(pNtk) ) return pNtk; - // consider the case of BLIF-MV - if ( Io_ReadFileType(pFileName) == IO_FILE_BLIFMV ) - { - extern Abc_Ntk_t * Abc_NtkConvertBlifMv( Abc_Ntk_t * pNtk ); -Abc_NtkPrintStats( stdout, pNtk, 0 ); -/* -{ - FILE * pFile = fopen( "_temp_.mv", "w" ); - Io_NtkWriteBlifMv( pFile, pNtk ); - fclose( pFile ); -} -*/ - pNtk = Abc_NtkConvertBlifMv( pTemp = pNtk ); - Abc_NtkDelete( pTemp ); - if ( pNtk == NULL ) - { - fprintf( stdout, "Converting BLIF-MV has failed.\n" ); - return NULL; - } - return pNtk; - } // flatten logic hierarchy assert( Abc_NtkIsNetlist(pNtk) ); if ( Abc_NtkWhiteboxNum(pNtk) > 0 ) @@ -218,69 +197,19 @@ Abc_NtkPrintStats( stdout, pNtk, 0 ); return NULL; } } - // convert the netlist into the logic network - pNtk = Abc_NtkToLogic( pTemp = pNtk ); - Abc_NtkDelete( pTemp ); - if ( pNtk == NULL ) - { - fprintf( stdout, "Converting netlist to logic network after reading has failed.\n" ); - return NULL; - } - return pNtk; -} - -/**Function************************************************************* - - Synopsis [Read the network from a file.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -Abc_Ntk_t * Io_ReadHie( char * pFileName, Io_FileType_t FileType, int fCheck ) -{ - Abc_Ntk_t * pNtk, * pTemp; - // detect the file type - if ( Io_ReadFileType(pFileName) == IO_FILE_BLIF ) - pNtk = Io_ReadBlifMv( pFileName, 0, fCheck ); -// else if ( Io_ReadFileType(pFileName) == IO_FILE_BLIFMV ) -// pNtk = Io_ReadBlifMv( pFileName, 1, fCheck ); - else if ( Io_ReadFileType(pFileName) == IO_FILE_VERILOG ) - pNtk = Io_ReadVerilog( pFileName, fCheck ); - else - { - printf( "Wrong file type.\n" ); - return NULL; - } - if ( pNtk == NULL ) - return NULL; -// printf( "\n" ); - // flatten logic hierarchy - assert( Abc_NtkIsNetlist(pNtk) ); - if ( Abc_NtkWhiteboxNum(pNtk) > 0 ) - { - pNtk = Abc_NtkFlattenLogicHierarchy( pTemp = pNtk ); - Abc_NtkDelete( pTemp ); - if ( pNtk == NULL ) - { - fprintf( stdout, "Flattening logic hierarchy has failed.\n" ); - return NULL; - } - } - // convert blackboxes - if ( Abc_NtkBlackboxNum(pNtk) > 0 ) + // consider the case of BLIF-MV + if ( Io_ReadFileType(pFileName) == IO_FILE_BLIFMV ) { - printf( "Hierarchy reader converted %d instances of blackboxes.\n", Abc_NtkBlackboxNum(pNtk) ); - pNtk = Abc_NtkConvertBlackboxes( pTemp = pNtk ); +//Abc_NtkPrintStats( stdout, pNtk, 0 ); +// Io_WriteBlifMv( pNtk, "_temp_.mv" ); + pNtk = Abc_NtkStrashBlifMv( pTemp = pNtk ); Abc_NtkDelete( pTemp ); if ( pNtk == NULL ) { - fprintf( stdout, "Converting blackboxes has failed.\n" ); + fprintf( stdout, "Converting BLIF-MV to AIG has failed.\n" ); return NULL; } + return pNtk; } // convert the netlist into the logic network pNtk = Abc_NtkToLogic( pTemp = pNtk ); @@ -349,7 +278,13 @@ void Io_Write( Abc_Ntk_t * pNtk, char * pFileName, Io_FileType_t FileType ) Io_WriteGml( pNtk, pFileName ); return; } - +/* + if ( FileType == IO_FILE_BLIFMV ) + { + Io_WriteBlifMv( pNtk, pFileName ); + return; + } +*/ // convert logic network into netlist if ( FileType == IO_FILE_PLA ) { @@ -359,15 +294,17 @@ void Io_Write( Abc_Ntk_t * pNtk, char * pFileName, Io_FileType_t FileType ) return; } if ( Abc_NtkIsComb(pNtk) ) - pNtkTemp = Abc_NtkToNetlist( pNtk, 1 ); + pNtkTemp = Abc_NtkToNetlist( pNtk ); else { fprintf( stdout, "Latches are writen into the PLA file at PI/PO pairs.\n" ); pNtkCopy = Abc_NtkDup( pNtk ); Abc_NtkMakeComb( pNtkCopy ); - pNtkTemp = Abc_NtkToNetlist( pNtk, 1 ); + pNtkTemp = Abc_NtkToNetlist( pNtk ); Abc_NtkDelete( pNtkCopy ); } + if ( !Abc_NtkToSop( pNtk, 1 ) ) + return; } else if ( FileType == IO_FILE_BENCH ) { @@ -379,7 +316,7 @@ void Io_Write( Abc_Ntk_t * pNtk, char * pFileName, Io_FileType_t FileType ) pNtkTemp = Abc_NtkToNetlistBench( pNtk ); } else - pNtkTemp = Abc_NtkToNetlist( pNtk, 0 ); + pNtkTemp = Abc_NtkToNetlist( pNtk ); if ( pNtkTemp == NULL ) { @@ -393,6 +330,12 @@ void Io_Write( Abc_Ntk_t * pNtk, char * pFileName, Io_FileType_t FileType ) Abc_NtkToSop( pNtkTemp, 0 ); Io_WriteBlif( pNtkTemp, pFileName, 1 ); } + else if ( FileType == IO_FILE_BLIFMV ) + { + if ( !Abc_NtkConvertToBlifMv( pNtkTemp ) ) + return; + Io_WriteBlifMv( pNtkTemp, pFileName ); + } else if ( FileType == IO_FILE_BENCH ) Io_WriteBench( pNtkTemp, pFileName ); else if ( FileType == IO_FILE_PLA ) @@ -439,6 +382,8 @@ void Io_WriteHie( Abc_Ntk_t * pNtk, char * pBaseName, char * pFileName ) assert( Abc_NtkIsStrash(pNtk) || Abc_NtkIsLogic(pNtk) ); if ( Io_ReadFileType(pBaseName) == IO_FILE_BLIF ) pNtkBase = Io_ReadBlifMv( pBaseName, 0, 1 ); + else if ( Io_ReadFileType(pBaseName) == IO_FILE_BLIFMV ) + pNtkBase = Io_ReadBlifMv( pBaseName, 1, 1 ); else if ( Io_ReadFileType(pBaseName) == IO_FILE_VERILOG ) pNtkBase = Io_ReadVerilog( pBaseName, 1 ); else @@ -446,6 +391,7 @@ void Io_WriteHie( Abc_Ntk_t * pNtk, char * pBaseName, char * pFileName ) if ( pNtkBase == NULL ) return; + // flatten logic hierarchy if present if ( Abc_NtkWhiteboxNum(pNtkBase) > 0 ) { pNtkBase = Abc_NtkFlattenLogicHierarchy( pNtkTemp = pNtkBase ); @@ -455,10 +401,27 @@ void Io_WriteHie( Abc_Ntk_t * pNtk, char * pBaseName, char * pFileName ) } // reintroduce the boxes into the netlist - if ( Abc_NtkBlackboxNum(pNtkBase) > 0 ) + if ( Io_ReadFileType(pBaseName) == IO_FILE_BLIFMV ) + { + if ( Abc_NtkBlackboxNum(pNtkBase) > 0 ) + { + printf( "Hierarchy writer does not support BLIF-MV with blackboxes.\n" ); + Abc_NtkDelete( pNtkBase ); + return; + } + // convert the current network to BLIF-MV + assert( !Abc_NtkIsNetlist(pNtk) ); + pNtkResult = Abc_NtkToNetlist( pNtk ); + if ( !Abc_NtkConvertToBlifMv( pNtkResult ) ) + return; + // reintroduce the network + pNtkResult = Abc_NtkInsertBlifMv( pNtkBase, pNtkTemp = pNtkResult ); + Abc_NtkDelete( pNtkTemp ); + } + else if ( Abc_NtkBlackboxNum(pNtkBase) > 0 ) { // derive the netlist - pNtkResult = Abc_NtkToNetlist( pNtk, 0 ); + pNtkResult = Abc_NtkToNetlist( pNtk ); pNtkResult = Abc_NtkInsertNewLogic( pNtkBase, pNtkTemp = pNtkResult ); Abc_NtkDelete( pNtkTemp ); if ( pNtkResult ) @@ -467,7 +430,7 @@ void Io_WriteHie( Abc_Ntk_t * pNtk, char * pBaseName, char * pFileName ) else { printf( "Warning: The output network does not contain blackboxes.\n" ); - pNtkResult = Abc_NtkToNetlist( pNtk, 0 ); + pNtkResult = Abc_NtkToNetlist( pNtk ); } Abc_NtkDelete( pNtkBase ); if ( pNtkResult == NULL ) @@ -486,6 +449,10 @@ void Io_WriteHie( Abc_Ntk_t * pNtk, char * pBaseName, char * pFileName ) Abc_NtkToAig( pNtkResult ); Io_WriteVerilog( pNtkResult, pFileName ); } + else if ( Io_ReadFileType(pFileName) == IO_FILE_BLIFMV ) + { + Io_WriteBlifMv( pNtkResult, pFileName ); + } else fprintf( stderr, "Unknown output file format.\n" ); @@ -614,61 +581,26 @@ Abc_Obj_t * Io_ReadCreateLatch( Abc_Ntk_t * pNtk, char * pNetLI, char * pNetLO ) Abc_Obj_t * Io_ReadCreateResetLatch( Abc_Ntk_t * pNtk, int fBlifMv ) { Abc_Obj_t * pLatch, * pNode; + Abc_Obj_t * pNetLI, * pNetLO; // create latch with 0 init value - pLatch = Io_ReadCreateLatch( pNtk, "_resetLI_", "_resetLO_" ); +// pLatch = Io_ReadCreateLatch( pNtk, "_resetLI_", "_resetLO_" ); + pNetLI = Abc_NtkCreateNet( pNtk ); + pNetLO = Abc_NtkCreateNet( pNtk ); + Abc_ObjAssignName( pNetLI, Abc_ObjName(pNetLI), NULL ); + Abc_ObjAssignName( pNetLO, Abc_ObjName(pNetLO), NULL ); + pLatch = Io_ReadCreateLatch( pNtk, Abc_ObjName(pNetLI), Abc_ObjName(pNetLO) ); + // set the initial value Abc_LatchSetInit0( pLatch ); // feed the latch with constant1- node - pNode = Abc_NtkCreateNode( pNtk ); - pNode->pData = Abc_SopRegister( pNtk->pManFunc, "2\n1\n" ); +// pNode = Abc_NtkCreateNode( pNtk ); +// pNode->pData = Abc_SopRegister( pNtk->pManFunc, "2\n1\n" ); + pNode = Abc_NtkCreateNodeConst1( pNtk ); Abc_ObjAddFanin( Abc_ObjFanin0(Abc_ObjFanin0(pLatch)), pNode ); return pLatch; } /**Function************************************************************* - Synopsis [Create a latch with the given input/output.] - - Description [By default, the latch value is unknown (ABC_INIT_NONE).] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -Abc_Obj_t * Io_ReadCreateResetMux( Abc_Ntk_t * pNtk, char * pResetLO, char * pDataLI, int fBlifMv ) -{ - char Buffer[50]; - Abc_Obj_t * pNode, * pData0Net, * pData1Net, * pResetLONet, * pLINet; - // get the reset output net - pResetLONet = Abc_NtkFindNet( pNtk, pResetLO ); - assert( pResetLONet ); - // get the latch input net - pData1Net = Abc_NtkFindOrCreateNet( pNtk, pDataLI ); - // create Data0 net (coming from reset node) - pData0Net = Abc_NtkFindOrCreateNet( pNtk, Abc_ObjNameSuffix(pData1Net, "_reset") ); - // create the node - pNode = Abc_NtkCreateNode( pNtk ); - if ( fBlifMv ) - { -// Vec_Att_t * p = Abc_NtkMvVar( pNtk ); - int nValues = Abc_ObjMvVarNum(pData1Net); - sprintf( Buffer, "2 %d %d %d\n1 - - =1\n0 - - =2\n", nValues, nValues, nValues ); - pNode->pData = Abc_SopRegister( pNtk->pManFunc, Buffer ); - } - else - pNode->pData = Abc_SopCreateMux( pNtk->pManFunc ); - // add nets - Abc_ObjAddFanin( pNode, pResetLONet ); - Abc_ObjAddFanin( pNode, pData1Net ); - Abc_ObjAddFanin( pNode, pData0Net ); - // create the output net - pLINet = Abc_NtkFindOrCreateNet( pNtk, Abc_ObjNameSuffix(pData1Net, "_mux") ); - Abc_ObjAddFanin( pLINet, pNode ); - return pNode; -} - -/**Function************************************************************* - Synopsis [Create node and the net driven by it.] Description [] diff --git a/src/base/io/ioWriteAiger.c b/src/base/io/ioWriteAiger.c index 3b7d78ca..00768356 100644 --- a/src/base/io/ioWriteAiger.c +++ b/src/base/io/ioWriteAiger.c @@ -225,7 +225,7 @@ void Io_WriteAiger( Abc_Ntk_t * pNtk, char * pFileName ) // write the buffer fwrite( pBuffer, 1, Pos, pFile ); free( pBuffer ); - +/* // write the symbol table // write PIs Abc_NtkForEachPi( pNtk, pObj, i ) @@ -236,7 +236,7 @@ void Io_WriteAiger( Abc_Ntk_t * pNtk, char * pFileName ) // write POs Abc_NtkForEachPo( pNtk, pObj, i ) fprintf( pFile, "o%d %s\n", i, Abc_ObjName(pObj) ); - +*/ // write the comment fprintf( pFile, "c\n" ); fprintf( pFile, "%s\n", pNtk->pName ); diff --git a/src/base/io/ioWriteBlif.c b/src/base/io/ioWriteBlif.c index 417fe2a3..c0c29d65 100644 --- a/src/base/io/ioWriteBlif.c +++ b/src/base/io/ioWriteBlif.c @@ -56,7 +56,7 @@ void Io_WriteBlifLogic( Abc_Ntk_t * pNtk, char * FileName, int fWriteLatches ) { Abc_Ntk_t * pNtkTemp; // derive the netlist - pNtkTemp = Abc_NtkToNetlist(pNtk,0); + pNtkTemp = Abc_NtkToNetlist(pNtk); if ( pNtkTemp == NULL ) { fprintf( stdout, "Writing BLIF has failed.\n" ); @@ -80,6 +80,8 @@ void Io_WriteBlifLogic( Abc_Ntk_t * pNtk, char * FileName, int fWriteLatches ) void Io_WriteBlif( Abc_Ntk_t * pNtk, char * FileName, int fWriteLatches ) { FILE * pFile; + Abc_Ntk_t * pNtkTemp; + int i; assert( Abc_NtkIsNetlist(pNtk) ); // start writing the file pFile = fopen( FileName, "w" ); @@ -96,18 +98,6 @@ void Io_WriteBlif( Abc_Ntk_t * pNtk, char * FileName, int fWriteLatches ) // write the hierarchy if present if ( Abc_NtkBlackboxNum(pNtk) > 0 ) { - Abc_Ntk_t * pNtkTemp; - int i; -/* - Abc_Obj_t * pObj; - Abc_NtkForEachBlackbox( pNtk, pObj, i ) - { - pNtkTemp = pObj->pData; - assert( pNtkTemp != NULL && Abc_NtkHasBlackbox(pNtkTemp) ); - fprintf( pFile, "\n\n" ); - Io_NtkWrite( pFile, pNtkTemp, fWriteLatches ); - } -*/ Vec_PtrForEachEntry( pNtk->pDesign->vModules, pNtkTemp, i ) { if ( pNtkTemp == pNtk ) diff --git a/src/base/io/ioWriteBlifMv.c b/src/base/io/ioWriteBlifMv.c index 597ca945..775a2e07 100644 --- a/src/base/io/ioWriteBlifMv.c +++ b/src/base/io/ioWriteBlifMv.c @@ -26,7 +26,7 @@ /// DECLARATIONS /// //////////////////////////////////////////////////////////////////////// -void Io_NtkWriteBlifMv( FILE * pFile, Abc_Ntk_t * pNtk ); +static void Io_NtkWriteBlifMv( FILE * pFile, Abc_Ntk_t * pNtk ); static void Io_NtkWriteBlifMvOne( FILE * pFile, Abc_Ntk_t * pNtk ); static void Io_NtkWriteBlifMvPis( FILE * pFile, Abc_Ntk_t * pNtk ); static void Io_NtkWriteBlifMvPos( FILE * pFile, Abc_Ntk_t * pNtk ); @@ -52,49 +52,34 @@ static void Io_NtkWriteBlifMvValues( FILE * pFile, Abc_Obj_t * pNode ); SeeAlso [] ***********************************************************************/ -void Io_WriteBlifMvDesign( Abc_Lib_t * pLib, char * FileName ) +void Io_WriteBlifMv( Abc_Ntk_t * pNtk, char * FileName ) { FILE * pFile; - Abc_Ntk_t * pNtk; + Abc_Ntk_t * pNtkTemp; int i; + assert( Abc_NtkIsNetlist(pNtk) ); + assert( Abc_NtkHasBlifMv(pNtk) ); // start writing the file pFile = fopen( FileName, "w" ); if ( pFile == NULL ) { - fprintf( stdout, "Io_WriteBlifMvDesign(): Cannot open the output file.\n" ); - return; - } - fprintf( pFile, "# Benchmark \"%s\" written by ABC on %s\n", pLib->pName, Extra_TimeStamp() ); - // write the master network - Vec_PtrForEachEntry( pLib->vModules, pNtk, i ) - Io_NtkWriteBlifMv( pFile, pNtk ); - fclose( pFile ); -} - -/**Function************************************************************* - - Synopsis [Write the network into a BLIF file with the given name.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -void Io_WriteBlifMvNetlist( Abc_Ntk_t * pNtk, char * FileName ) -{ - FILE * pFile; - // start writing the file - pFile = fopen( FileName, "w" ); - if ( pFile == NULL ) - { - fprintf( stdout, "Io_WriteMvNetlist(): Cannot open the output file.\n" ); + fprintf( stdout, "Io_WriteBlifMv(): Cannot open the output file.\n" ); return; } fprintf( pFile, "# Benchmark \"%s\" written by ABC on %s\n", pNtk->pName, Extra_TimeStamp() ); // write the master network Io_NtkWriteBlifMv( pFile, pNtk ); + // write the remaining networks + if ( pNtk->pDesign ) + { + Vec_PtrForEachEntry( pNtk->pDesign->vModules, pNtkTemp, i ) + { + if ( pNtkTemp == pNtk ) + continue; + fprintf( pFile, "\n\n" ); + Io_NtkWriteBlifMv( pFile, pNtkTemp ); + } + } fclose( pFile ); } @@ -185,7 +170,7 @@ void Io_NtkWriteBlifMvOne( FILE * pFile, Abc_Ntk_t * pNtk ) Io_NtkWriteBlifMvLatch( pFile, pLatch ); fprintf( pFile, "\n" ); } - +/* // write the subcircuits assert( Abc_NtkWhiteboxNum(pNtk) == 0 ); if ( Abc_NtkBlackboxNum(pNtk) > 0 ) @@ -195,6 +180,18 @@ void Io_NtkWriteBlifMvOne( FILE * pFile, Abc_Ntk_t * pNtk ) Io_NtkWriteBlifMvSubckt( pFile, pNode ); fprintf( pFile, "\n" ); } +*/ + if ( Abc_NtkBlackboxNum(pNtk) > 0 || Abc_NtkWhiteboxNum(pNtk) > 0 ) + { + fprintf( pFile, "\n" ); + Abc_NtkForEachBox( pNtk, pNode, i ) + { + if ( Abc_ObjIsLatch(pNode) ) + continue; + Io_NtkWriteBlifMvSubckt( pFile, pNode ); + } + fprintf( pFile, "\n" ); + } // write each internal node pProgress = Extra_ProgressBarStart( stdout, Abc_NtkObjNumMax(pNtk) ); @@ -414,26 +411,32 @@ void Io_NtkWriteBlifMvNode( FILE * pFile, Abc_Obj_t * pNode ) Abc_Obj_t * pFanin; char * pCur; int nValues, iFanin, i; - fprintf( pFile, "\n" ); + // write .mv directives for the fanins - pCur = Abc_ObjData(pNode); + fprintf( pFile, "\n" ); Abc_ObjForEachFanin( pNode, pFanin, i ) { - nValues = atoi(pCur); +// nValues = atoi(pCur); + nValues = Abc_ObjMvVarNum( pFanin ); if ( nValues > 2 ) fprintf( pFile, ".mv %s %d\n", Abc_ObjName(pFanin), nValues ); - while ( *pCur++ != ' ' ); +// while ( *pCur++ != ' ' ); } + // write .mv directives for the node - nValues = atoi(pCur); +// nValues = atoi(pCur); + nValues = Abc_ObjMvVarNum( Abc_ObjFanout0(pNode) ); if ( nValues > 2 ) fprintf( pFile, ".mv %s %d\n", Abc_ObjName(Abc_ObjFanout0(pNode)), nValues ); - while ( *pCur++ != '\n' ); +// while ( *pCur++ != '\n' ); + // write the .names line fprintf( pFile, ".table" ); Io_NtkWriteBlifMvNodeFanins( pFile, pNode ); fprintf( pFile, "\n" ); + // write the cubes + pCur = Abc_ObjData(pNode); if ( *pCur == 'd' ) { fprintf( pFile, ".default " ); diff --git a/src/base/io/ioWriteDot.c b/src/base/io/ioWriteDot.c index d8bb1855..8ae3cc42 100644 --- a/src/base/io/ioWriteDot.c +++ b/src/base/io/ioWriteDot.c @@ -277,6 +277,8 @@ void Io_WriteDotNtk( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho { if ( (int)pNode->Level != Level ) continue; + if ( Abc_ObjFaninNum(pNode) == 0 ) + continue; // fprintf( pFile, " Node%d [label = \"%d\"", pNode->Id, pNode->Id ); if ( Abc_NtkIsStrash(pNtk) ) pSopString = ""; @@ -313,7 +315,7 @@ void Io_WriteDotNtk( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho // check if the costant node is present if ( Abc_ObjFaninNum(pNode) == 0 && Abc_ObjFanoutNum(pNode) > 0 ) { - fprintf( pFile, " Node%d [label = \"Const1\"", pNode->Id ); + fprintf( pFile, " Node%d [label = \"Const%d\"", pNode->Id, Abc_NtkIsStrash(pNode->pNtk) || Abc_NodeIsConst1(pNode) ); fprintf( pFile, ", shape = ellipse" ); if ( pNode->fMarkB ) fprintf( pFile, ", style = filled" ); |