4 files changed, 24 insertions, 7 deletions

diff --git a/src/base/io/ioReadAiger.c b/src/base/io/ioReadAiger.c
index a54a00fe..fe519476 100644
--- a/src/base/io/ioReadAiger.c
+++ b/src/base/io/ioReadAiger.c
@@ -96,7 +96,7 @@ Abc_Ntk_t * Io_ReadAiger( char * pFileName, int fCheck )
 
     // prepare the array of nodes
     vNodes = Vec_PtrAlloc( 1 + nInputs + nLatches + nAnds );
-    Vec_PtrPush( vNodes, Abc_AigConst1(pNtkNew) );
+    Vec_PtrPush( vNodes, Abc_ObjNot( Abc_AigConst1(pNtkNew) ) );
 
     // create the PIs
     for ( i = 0; i < nInputs; i++ )
@@ -122,6 +122,8 @@ Abc_Ntk_t * Io_ReadAiger( char * pFileName, int fCheck )
         Vec_PtrPush( vNodes, pNode1 );
         // assign names to latch and its input
         Abc_ObjAssignName( pObj, Abc_ObjNameDummy("_L", i, nDigits), NULL );
+
+        printf( "Creating latch %s with input %d and output %d.\n", Abc_ObjName(pObj), pNode0->Id, pNode1->Id );
     } 
     
     // remember the beginning of latch/PO literals
@@ -156,14 +158,17 @@ Abc_Ntk_t * Io_ReadAiger( char * pFileName, int fCheck )
     Abc_NtkForEachLatchInput( pNtkNew, pObj, i )
     {
         uLit0 = atoi( pCur );  while ( *pCur++ != '\n' );
-        pNode0 = Abc_ObjNotCond( Vec_PtrEntry(vNodes, uLit0 >> 1), (uLit0 & 1) ^ (uLit0 < 2) );
+        pNode0 = Abc_ObjNotCond( Vec_PtrEntry(vNodes, uLit0 >> 1), (uLit0 & 1) );//^ (uLit0 < 2) );
         Abc_ObjAddFanin( pObj, pNode0 );
+
+        printf( "Adding input %d to latch input %d.\n", pNode0->Id, pObj->Id );
+
     }
     // read the PO driver literals
     Abc_NtkForEachPo( pNtkNew, pObj, i )
     {
         uLit0 = atoi( pCur );  while ( *pCur++ != '\n' );
-        pNode0 = Abc_ObjNotCond( Vec_PtrEntry(vNodes, uLit0 >> 1), (uLit0 & 1) ^ (uLit0 < 2) );
+        pNode0 = Abc_ObjNotCond( Vec_PtrEntry(vNodes, uLit0 >> 1), (uLit0 & 1) );//^ (uLit0 < 2) );
         Abc_ObjAddFanin( pObj, pNode0 );
     }
 
@@ -204,7 +209,7 @@ Abc_Ntk_t * Io_ReadAiger( char * pFileName, int fCheck )
             Abc_ObjAssignName( Abc_ObjFanin0(Abc_ObjFanin0(pObj)), Abc_ObjName(pObj), "L" );
         // mark the node as named
         pObj->pCopy = (Abc_Obj_t *)Abc_ObjName(pObj);
-    }
+    } 
     // skipping the comments
     free( pContents );
     Vec_PtrFree( vNodes );
diff --git a/src/base/io/ioReadBench.c b/src/base/io/ioReadBench.c
index 2730ba69..ba622e40 100644
--- a/src/base/io/ioReadBench.c
+++ b/src/base/io/ioReadBench.c
@@ -118,7 +118,13 @@ Abc_Ntk_t * Io_ReadBenchNetwork( Extra_FileReader_t * p )
             if ( strncmp(pType, "DFF", 3) == 0 ) // works for both DFF and DFFRSE
             {
                 pNode = Io_ReadCreateLatch( pNtk, vTokens->pArray[2], vTokens->pArray[0] );
-                Abc_LatchSetInit0( pNode );
+//                Abc_LatchSetInit0( pNode );
+                if ( pType[3] == '0' )
+                    Abc_LatchSetInit0( pNode );
+                else if ( pType[3] == '1' )
+                    Abc_LatchSetInit1( pNode );
+                else
+                    Abc_LatchSetInitDc( pNode );
             }
             else if ( strcmp(pType, "LUT") == 0 )
             {
diff --git a/src/base/io/ioWriteVerilog.c b/src/base/io/ioWriteVerilog.c
index a02d53fd..a4eeb78f 100644
--- a/src/base/io/ioWriteVerilog.c
+++ b/src/base/io/ioWriteVerilog.c
@@ -113,7 +113,12 @@ void Io_WriteVerilogInt( FILE * pFile, Abc_Ntk_t * pNtk )
 {
     // write inputs and outputs
 //    fprintf( pFile, "module %s ( gclk,\n   ", Abc_NtkName(pNtk) );
-    fprintf( pFile, "module %s ( \n   ", Abc_NtkName(pNtk) );
+    fprintf( pFile, "module %s ( ", Abc_NtkName(pNtk) );
+    // add the clock signal if it does not exist
+    if ( Abc_NtkLatchNum(pNtk) > 0 && Nm_ManFindIdByName(pNtk->pManName, "clock", ABC_OBJ_PI) == -1 )
+        fprintf( pFile, "clock, " );
+    // write other primary inputs
+    fprintf( pFile, "\n   " );
     if ( Abc_NtkPiNum(pNtk) > 0  )
     {
         Io_WriteVerilogPis( pFile, pNtk, 3 );
@@ -435,7 +440,8 @@ void Io_WriteVerilogLatches( FILE * pFile, Abc_Ntk_t * pNtk )
         return;
     // write the latches
 //    fprintf( pFile, "  always @(posedge %s) begin\n", Io_WriteVerilogGetName(Abc_ObjFanout0(Abc_NtkPi(pNtk,0))) );
-    fprintf( pFile, "  always begin\n" );
+//    fprintf( pFile, "  always begin\n" );
+    fprintf( pFile, "  always @ (posedge clock) begin\n" );
     Abc_NtkForEachLatch( pNtk, pLatch, i )
     {
         fprintf( pFile, "    %s", Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanout0(Abc_ObjFanout0(pLatch)))) );
diff --git a/src/base/io/ioWriteVerilog.zip b/src/base/io/ioWriteVerilog.zip
new file mode 100644
index 00000000..19e68a89
--- /dev/null
+++ b/src/base/io/ioWriteVerilog.zip