diff options
Diffstat (limited to 'src/map/fpga/fpgaCore.c')
-rw-r--r-- | src/map/fpga/fpgaCore.c | 121 |
1 files changed, 13 insertions, 108 deletions
diff --git a/src/map/fpga/fpgaCore.c b/src/map/fpga/fpgaCore.c index 457c2384..b181e997 100644 --- a/src/map/fpga/fpgaCore.c +++ b/src/map/fpga/fpgaCore.c @@ -17,18 +17,12 @@ ***********************************************************************/ #include "fpgaInt.h" -//#include "res.h" //////////////////////////////////////////////////////////////////////// /// DECLARATIONS /// //////////////////////////////////////////////////////////////////////// -static int Fpga_MappingPostProcess( Fpga_Man_t * p ); - -extern void Fpga_Experiment( Fpga_Man_t * p ); -extern void Fpga_MappingCutsSeq( Fpga_Man_t * p ); -extern void Fpga_MappingLValues( Fpga_Man_t * pMan, int fVerbose ); - +static int Fpga_MappingPostProcess( Fpga_Man_t * p ); //////////////////////////////////////////////////////////////////////// /// FUNCTION DEFITIONS /// @@ -51,35 +45,18 @@ extern void Fpga_MappingLValues( Fpga_Man_t * pMan, int fVerbose ); ***********************************************************************/ int Fpga_Mapping( Fpga_Man_t * p ) { - int clk; + int clk, clkTotal = clock(); // collect the nodes reachable from POs in the DFS order (including the choices) p->vAnds = Fpga_MappingDfs( p, 1 ); Fpga_ManReportChoices( p ); // recomputes levels Fpga_MappingSetChoiceLevels( p ); - if ( p->fSequential ) - { -// Fpga_MappingCutsSeq( p ); - Fpga_MappingCuts( p ); -//clk = clock(); -// Fpga_MappingLValues( p, p->fVerbose ); -//PRT( "Time", clock() - clk ); - return 0; - } - // compute the cuts of nodes in the DFS order clk = clock(); Fpga_MappingCuts( p ); p->timeCuts = clock() - clk; -// Fpga_MappingSortByLevel( p, p->vAnds, 1 ); - - // derive the truth tables - clk = clock(); -// Fpga_MappingTruths( p ); - p->timeTruth = clock() - clk; - // match the truth tables to the supergates clk = clock(); if ( !Fpga_MappingMatches( p, 1 ) ) @@ -94,10 +71,7 @@ int Fpga_Mapping( Fpga_Man_t * p ) return 0; p->timeRecover = clock() - clk; } - - // perform resynthesis -// if ( p->fResynthesis ) -// Res_Resynthesize( p, p->DelayLimit, p->AreaLimit, p->TimeLimit, 1 ); +PRT( "Total mapping time", clock() - clkTotal ); // print the AI-graph used for mapping //Fpga_ManShow( p, "test" ); @@ -124,128 +98,59 @@ int Fpga_Mapping( Fpga_Man_t * p ) int Fpga_MappingPostProcess( Fpga_Man_t * p ) { float aAreaTotalPrev, aAreaTotalCur, aAreaTotalCur2; - float aSwitchTotalPrev, aSwitchTotalCur; int Iter, clk; - + // compute area, set references, and collect nodes used in the mapping + aAreaTotalCur = Fpga_MappingSetRefsAndArea( p ); if ( p->fVerbose ) { -printf( "Iteration %dD : Area = %11.1f ", 0, Fpga_MappingArea( p ) ); +printf( "Iteration %dD : Area = %11.1f ", 0, aAreaTotalCur ); PRT( "Time", p->timeMatch ); } - -// Fpga_MappingExplore( p ); -// p->fAreaGlo = Fpga_MappingArea( p ); -// return; - - -// aAreaTotalCur = FPGA_FLOAT_LARGE; - aAreaTotalCur = Fpga_MappingSetRefsAndArea( p ); - Iter = 1; do { clk = clock(); // save the previous area flow aAreaTotalPrev = aAreaTotalCur; - // compute the required times and the fanouts Fpga_TimeComputeRequiredGlobal( p ); // remap topologically Fpga_MappingMatches( p, 0 ); // get the resulting area - aAreaTotalCur = Fpga_MappingArea( p ); +// aAreaTotalCur = Fpga_MappingSetRefsAndArea( p ); + aAreaTotalCur = Fpga_MappingAreaTrav( p ); + // note that here we do not update the reference counter + // for some reason, this works better on benchmarks if ( p->fVerbose ) { printf( "Iteration %dF : Area = %11.1f ", Iter++, aAreaTotalCur ); PRT( "Time", clock() - clk ); } - if ( p->fPower ) - aSwitchTotalCur = Fpga_MappingPrintSwitching( p ); // quit if this iteration reduced area flow by less than 1% } while ( aAreaTotalPrev > 1.02 * aAreaTotalCur ); - -// Fpga_MappingExplore( p ); -// p->fAreaGlo = Fpga_MappingArea( p ); -// return; - - -/* - // compute the area of each cut - aAreaTotalCur = Fpga_MappingSetRefsAndArea( p ); - // compute the required times and the fanouts - Fpga_TimeComputeRequiredGlobal( p ); - // perform experiment - Fpga_Experiment( p ); -*/ - - - // compute the area of each cut - aAreaTotalCur = Fpga_MappingSetRefsAndArea( p ); - aAreaTotalCur2 = Fpga_MappingComputeCutAreas( p ); + // update reference counters + aAreaTotalCur2 = Fpga_MappingSetRefsAndArea( p ); assert( aAreaTotalCur == aAreaTotalCur2 ); - -// aAreaTotalCur = FPGA_FLOAT_LARGE; -// Iter = 1; do { clk = clock(); // save the previous area flow aAreaTotalPrev = aAreaTotalCur; - // compute the required times and the fanouts Fpga_TimeComputeRequiredGlobal( p ); // remap topologically Fpga_MappingMatchesArea( p ); // get the resulting area - aAreaTotalCur = Fpga_MappingArea( p ); + aAreaTotalCur = Fpga_MappingSetRefsAndArea( p ); if ( p->fVerbose ) { printf( "Iteration %dA : Area = %11.1f ", Iter++, aAreaTotalCur ); PRT( "Time", clock() - clk ); } - if ( p->fPower ) - { - aSwitchTotalPrev = aSwitchTotalCur; - aSwitchTotalCur = Fpga_MappingPrintSwitching( p ); - } // quit if this iteration reduced area flow by less than 1% } while ( aAreaTotalPrev > 1.02 * aAreaTotalCur ); - - - if ( p->fPower ) - { - do { -clk = clock(); - // save the previous area flow - aAreaTotalPrev = aAreaTotalCur; - - // compute the required times and the fanouts - Fpga_TimeComputeRequiredGlobal( p ); - // remap topologically - Fpga_MappingMatchesSwitch( p ); - // get the resulting area - aAreaTotalCur = Fpga_MappingArea( p ); -if ( p->fVerbose ) -{ -printf( "Iteration %dS : Area = %11.1f ", Iter++, aAreaTotalCur ); -PRT( "Time", clock() - clk ); -} - aSwitchTotalPrev = aSwitchTotalCur; - aSwitchTotalCur = Fpga_MappingPrintSwitching( p ); - // quit if this iteration reduced area flow by less than 1% - } while ( aSwitchTotalPrev > 1.01 * aSwitchTotalCur ); - } - -/* - // compute the area of each cut - aAreaTotalCur = Fpga_MappingSetRefsAndArea( p ); - // compute the required times and the fanouts - Fpga_TimeComputeRequiredGlobal( p ); - // perform experiment - Fpga_Experiment( p ); -*/ p->fAreaGlo = aAreaTotalCur; return 1; } |