diff options
Diffstat (limited to 'src')
-rw-r--r-- | src/base/abci/abcDar.c | 21 | ||||
-rw-r--r-- | src/base/cba/cbaBlast.c | 29 | ||||
-rw-r--r-- | src/base/cba/cbaSimple.c | 17 | ||||
-rw-r--r-- | src/base/cba/cbaWriteBlif.c | 2 |
4 files changed, 52 insertions, 17 deletions
diff --git a/src/base/abci/abcDar.c b/src/base/abci/abcDar.c index f450fc47..8f01c9c1 100644 --- a/src/base/abci/abcDar.c +++ b/src/base/abci/abcDar.c @@ -871,13 +871,14 @@ static inline Abc_Obj_t * Abc_NtkFromCellRead( Abc_Ntk_t * p, Vec_Int_t * vCopyL } Abc_Ntk_t * Abc_NtkFromCellMappedGia( Gia_Man_t * p ) { - int fVerbose = 1; + int fFixDrivers = 0; int fDuplicate = 1; + int fVerbose = 1; Abc_Ntk_t * pNtkNew; Vec_Int_t * vCopyLits; Abc_Obj_t * pObjNew, * pObjNewLi, * pObjNewLo; Gia_Obj_t * pObj, * pObjLi, * pObjLo; - int i, k, iLit, iFanLit, nDupGates, nCells, fNeedConst[2] = {0}; + int i, k, iLit, iFanLit, nCells, fNeedConst[2] = {0}; Mio_Cell_t * pCells = Mio_CollectRootsNewDefault( 6, &nCells, 0 ); assert( Gia_ManHasCellMapping(p) ); // start network @@ -985,14 +986,18 @@ Abc_Ntk_t * Abc_NtkFromCellMappedGia( Gia_Man_t * p ) Abc_NtkAddDummyBoxNames( pNtkNew ); // decouple the PO driver nodes to reduce the number of levels - nDupGates = Abc_NtkLogicMakeSimpleCos( pNtkNew, fDuplicate ); - if ( fVerbose && nDupGates && !Abc_FrameReadFlag("silentmode") ) + if ( fFixDrivers ) { - if ( !fDuplicate ) - printf( "Added %d buffers/inverters to decouple the CO drivers.\n", nDupGates ); - else - printf( "Duplicated %d gates to decouple the CO drivers.\n", nDupGates ); + int nDupGates = Abc_NtkLogicMakeSimpleCos( pNtkNew, fDuplicate ); + if ( fVerbose && nDupGates && !Abc_FrameReadFlag("silentmode") ) + { + if ( !fDuplicate ) + printf( "Added %d buffers/inverters to decouple the CO drivers.\n", nDupGates ); + else + printf( "Duplicated %d gates to decouple the CO drivers.\n", nDupGates ); + } } + assert( Gia_ManPiNum(p) == Abc_NtkPiNum(pNtkNew) ); assert( Gia_ManPoNum(p) == Abc_NtkPoNum(pNtkNew) ); assert( Gia_ManRegNum(p) == Abc_NtkLatchNum(pNtkNew) ); diff --git a/src/base/cba/cbaBlast.c b/src/base/cba/cbaBlast.c index bd120044..e4365d83 100644 --- a/src/base/cba/cbaBlast.c +++ b/src/base/cba/cbaBlast.c @@ -59,7 +59,7 @@ void Cba_ManPrepareGates( Cba_Man_t * p ) ppGraphs[i] = Dec_Factor( pSop ); } assert( p->ppGraphs == NULL ); - p->ppGraphs = ppGraphs; + p->ppGraphs = (void **)ppGraphs; } void Cba_ManUndoGates( Cba_Man_t * p ) { @@ -432,7 +432,7 @@ Cba_Man_t * Cba_ManBlastTest( Cba_Man_t * p ) ***********************************************************************/ static inline int Abc_NodeIsSeriousGate( Abc_Obj_t * p ) { - return Abc_ObjIsNode(p) && (Abc_ObjFaninNum(p) > 0); + return (Abc_ObjIsNode(p) && (Abc_ObjFaninNum(p) > 0) && !Abc_ObjIsBarBuf(p));// || Abc_ObjIsPi(p); } Vec_Int_t * Cba_ManCountAbc( Cba_Man_t * p, Abc_Ntk_t * pNtk, int fAlwaysAdd ) { @@ -464,10 +464,11 @@ Vec_Int_t * Cba_ManCountAbc( Cba_Man_t * p, Abc_Ntk_t * pNtk, int fAlwaysAdd ) assert( Count == pNtk->nBarBufs2 ); Abc_NtkForEachPo( pNtk, pObj, i ) { + if ( !Abc_NodeIsSeriousGate(Abc_ObjFanin0(pObj)) ) + continue; assert( Abc_ObjFanin0(pObj)->iTemp == 1 ); pObj->iTemp = Abc_ObjFanin0(pObj)->iTemp; - if ( Abc_NodeIsSeriousGate(Abc_ObjFanin0(pObj)) ) - Vec_IntAddToEntry( vDrivenCos, pObj->iTemp, 1 ); + Vec_IntAddToEntry( vDrivenCos, pObj->iTemp, 1 ); } // for each network, count the total number of COs Cba_ManForEachNtk( p, pCbaNtk, i ) @@ -487,6 +488,14 @@ void Cba_NtkCreateOrConnectFanin( Abc_Ntk_t * pNtk, Abc_Obj_t * pFanin, Cba_Ntk_ Vec_IntWriteEntry( &p->vNameIds, pFanin->iTemp, Cba_ObjNameId(p, iTerm) ); Vec_IntWriteEntry( &p->vFanins, iTerm, pFanin->iTemp ); } + else if ( pNtk && (Abc_ObjIsPi(pFanin) || Abc_ObjIsBarBuf(pFanin)) ) + { + Vec_IntWriteEntry( &p->vTypes, p->nObjs, CBA_OBJ_NODE ); + Vec_IntWriteEntry( &p->vFuncs, p->nObjs, 3 ); // assuming elem gates are added first + Vec_IntWriteEntry( &p->vFanins, p->nObjs, Cba_ManHandleBuffer(p->pDesign, pFanin->iTemp) ); + Vec_IntWriteEntry( &p->vNameIds, p->nObjs, Cba_ObjNameId(p, iTerm) ); + Vec_IntWriteEntry( &p->vFanins, iTerm, p->nObjs++ ); + } else { assert( !pFanin || Abc_NodeIsConst0(pFanin) || Abc_NodeIsConst1(pFanin) ); @@ -502,12 +511,19 @@ void Cba_NtkPrepareLibrary( Cba_Man_t * p, Mio_Library_t * pLib ) Mio_Gate_t * pGate; Mio_Gate_t * pGate0 = Mio_LibraryReadConst0( pLib ); Mio_Gate_t * pGate1 = Mio_LibraryReadConst1( pLib ); + Mio_Gate_t * pGate2 = Mio_LibraryReadBuf( pLib ); + if ( !pGate0 || !pGate1 || !pGate2 ) + { + printf( "The library does not have one of the elementary gates.\n" ); + return; + } assert( Abc_NamObjNumMax(p->pFuncs) == 1 ); Abc_NamStrFindOrAdd( p->pFuncs, Mio_GateReadName(pGate0), NULL ); Abc_NamStrFindOrAdd( p->pFuncs, Mio_GateReadName(pGate1), NULL ); - assert( Abc_NamObjNumMax(p->pFuncs) == 3 ); + Abc_NamStrFindOrAdd( p->pFuncs, Mio_GateReadName(pGate2), NULL ); + assert( Abc_NamObjNumMax(p->pFuncs) == 4 ); Mio_LibraryForEachGate( pLib, pGate ) - if ( pGate != pGate0 && pGate != pGate1 ) + if ( pGate != pGate0 && pGate != pGate1 && pGate != pGate2 ) Abc_NamStrFindOrAdd( p->pFuncs, Mio_GateReadName(pGate), NULL ); assert( Abc_NamObjNumMax(p->pFuncs) > 1 ); } @@ -519,6 +535,7 @@ void Cba_NtkInsertNtk( Cba_Man_t * p, Abc_Ntk_t * pNtk ) Abc_Obj_t * pObj, * pFanin; assert( Abc_NtkHasMapping(pNtk) ); Cba_NtkPrepareLibrary( p, (Mio_Library_t *)pNtk->pManFunc ); + p->pMioLib = pNtk->pManFunc; Abc_NtkForEachPi( pNtk, pObj, i ) pObj->iTemp = Cba_NtkPi( pRoot, i ); diff --git a/src/base/cba/cbaSimple.c b/src/base/cba/cbaSimple.c index 1370a0be..bebb9464 100644 --- a/src/base/cba/cbaSimple.c +++ b/src/base/cba/cbaSimple.c @@ -30,10 +30,23 @@ ABC_NAMESPACE_IMPL_START /* design = array containing design name (as the first entry in the array) followed by pointers to modules -module = array containing module name (as the first entry in the array) followed by pointers to four arrays: - {array of input names; array of output names; array of nodes; array of boxes} +module = array containing module name (as the first entry in the array) followed by pointers to 6 arrays: + {array of input names; array of output names; array of nodes; array of boxes, + array of floating-point input-arrival times; array of floating-point output-required times} node = array containing output name, followed by node type, followed by input names box = array containing model name, instance name, followed by pairs of formal/actual names for each port + + Comments: + - in describing boxes + - input formal/actual name pairs should be listed before output name pairs + - the order of formal names should be the same as the order of inputs/outputs in the module description + - all formal names present in the module description should be listed + - if an input pin is not driven or an output pin has no fanout, the actual pin name is NULL + - word-level formal name "a" is written as bit-level names (a[0]. a[1], etc) ordered LSB to MSB + - primitive names should be given as char*-strings in description of nodes and boxes + - primitive modules should not be written, but the list of primitives and formal names should be provided + - constant 0/1 nets can be specified as char*-strings "NetConst0" and "NetConst1". + - arrays of input-arrival/output-required times in the module description are optional */ //////////////////////////////////////////////////////////////////////// diff --git a/src/base/cba/cbaWriteBlif.c b/src/base/cba/cbaWriteBlif.c index 4a59b69d..e8fd8ae1 100644 --- a/src/base/cba/cbaWriteBlif.c +++ b/src/base/cba/cbaWriteBlif.c @@ -171,7 +171,7 @@ void Cba_ManWriteBlifLines( FILE * pFile, Cba_Ntk_t * p ) { char * pGateName = Abc_NamStr( p->pDesign->pFuncs, Cba_ObjFuncId(p, i) ); Mio_Gate_t * pGate = Mio_LibraryReadGateByName( (Mio_Library_t *)p->pDesign->pMioLib, pGateName, NULL ); - fprintf( pFile, ".gate" ); + fprintf( pFile, ".gate %s", pGateName ); Cba_ManWriteBlifGate( pFile, p, pGate, Cba_ObjFaninVec(p, i), i ); } else if ( Abc_NamObjNumMax(p->pDesign->pFuncs) > 1 ) // SOP functions |