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-rw-r--r--src/base/abc/abcHieGia.c145
1 files changed, 124 insertions, 21 deletions
diff --git a/src/base/abc/abcHieGia.c b/src/base/abc/abcHieGia.c
index 24166c8f..cfdf2e49 100644
--- a/src/base/abc/abcHieGia.c
+++ b/src/base/abc/abcHieGia.c
@@ -211,7 +211,7 @@ Gia_Man_t * Gia_ManFlattenLogicHierarchy2( Abc_Ntk_t * pNtk )
SeeAlso []
***********************************************************************/
-void Gia_ManFlattenLogicPrepare( Abc_Ntk_t * pNtk )
+int Gia_ManFlattenLogicPrepare( Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pTerm, * pBox;
int i, k;
@@ -228,8 +228,9 @@ void Gia_ManFlattenLogicPrepare( Abc_Ntk_t * pNtk )
Abc_ObjForEachFanout( pBox, pTerm, k )
pTerm->iData = k;
}
+ return Abc_NtkPiNum(pNtk) + Abc_NtkPoNum(pNtk);
}
-int Gia_ManFlattenLogicHierarchy_rec( Gia_Man_t * pNew, Vec_Ptr_t * vSupers, Abc_Obj_t * pObj, Vec_Int_t * vBufs )
+int Gia_ManFlattenLogicHierarchy_rec( Gia_Man_t * pNew, Vec_Ptr_t * vSupers, Abc_Obj_t * pObj, Vec_Ptr_t * vBuffers )
{
Abc_Ntk_t * pModel;
Abc_Obj_t * pBox, * pFanin;
@@ -237,62 +238,66 @@ int Gia_ManFlattenLogicHierarchy_rec( Gia_Man_t * pNew, Vec_Ptr_t * vSupers, Abc
if ( pObj->iTemp != -1 )
return pObj->iTemp;
if ( Abc_ObjIsNet(pObj) || Abc_ObjIsPo(pObj) || Abc_ObjIsBi(pObj) )
- return (pObj->iTemp = Gia_ManFlattenLogicHierarchy_rec(pNew, vSupers, Abc_ObjFanin0(pObj), vBufs));
+ return (pObj->iTemp = Gia_ManFlattenLogicHierarchy_rec(pNew, vSupers, Abc_ObjFanin0(pObj), vBuffers));
if ( Abc_ObjIsPi(pObj) )
{
pBox = (Abc_Obj_t *)Vec_PtrPop( vSupers );
- pModel = (Abc_Ntk_t *)pBox->pData;
+ pModel = Abc_ObjModel(pBox);
//printf( " Exiting %s\n", Abc_NtkName(pModel) );
assert( Abc_ObjFaninNum(pBox) == Abc_NtkPiNum(pModel) );
assert( pObj->iData >= 0 && pObj->iData < Abc_NtkPiNum(pModel) );
pFanin = Abc_ObjFanin( pBox, pObj->iData );
- iLit = Gia_ManFlattenLogicHierarchy_rec( pNew, vSupers, pFanin, vBufs );
+ iLit = Gia_ManFlattenLogicHierarchy_rec( pNew, vSupers, pFanin, vBuffers );
Vec_PtrPush( vSupers, pBox );
- return (pObj->iTemp = (vBufs ? Gia_ManAppendBuf(pNew, iLit) : iLit));
+ //if ( vBuffers ) Vec_PtrPush( vBuffers, pFanin ); // save BI
+ if ( vBuffers ) Vec_PtrPush( vBuffers, pObj ); // save PI
+ return (pObj->iTemp = (vBuffers ? Gia_ManAppendBuf(pNew, iLit) : iLit));
}
if ( Abc_ObjIsBo(pObj) )
{
pBox = Abc_ObjFanin0(pObj);
assert( Abc_ObjIsBox(pBox) );
Vec_PtrPush( vSupers, pBox );
- pModel = (Abc_Ntk_t *)pBox->pData;
+ pModel = Abc_ObjModel(pBox);
//printf( "Entering %s\n", Abc_NtkName(pModel) );
assert( Abc_ObjFanoutNum(pBox) == Abc_NtkPoNum(pModel) );
assert( pObj->iData >= 0 && pObj->iData < Abc_NtkPoNum(pModel) );
pFanin = Abc_NtkPo( pModel, pObj->iData );
- iLit = Gia_ManFlattenLogicHierarchy_rec( pNew, vSupers, pFanin, vBufs );
+ iLit = Gia_ManFlattenLogicHierarchy_rec( pNew, vSupers, pFanin, vBuffers );
Vec_PtrPop( vSupers );
- return (pObj->iTemp = (vBufs ? Gia_ManAppendBuf(pNew, iLit) : iLit));
+ //if ( vBuffers ) Vec_PtrPush( vBuffers, pObj ); // save BO
+ if ( vBuffers ) Vec_PtrPush( vBuffers, pFanin ); // save PO
+ return (pObj->iTemp = (vBuffers ? Gia_ManAppendBuf(pNew, iLit) : iLit));
}
assert( Abc_ObjIsNode(pObj) );
Abc_ObjForEachFanin( pObj, pFanin, i )
- Gia_ManFlattenLogicHierarchy_rec( pNew, vSupers, pFanin, vBufs );
+ Gia_ManFlattenLogicHierarchy_rec( pNew, vSupers, pFanin, vBuffers );
return (pObj->iTemp = Abc_NodeStrashToGia( pNew, pObj ));
}
-Gia_Man_t * Gia_ManFlattenLogicHierarchy( Abc_Ntk_t * pNtk )
+Gia_Man_t * Gia_ManFlattenLogicHierarchy( Abc_Ntk_t * pNtk, Vec_Ptr_t ** pvBuffers )
{
int fUseBufs = 1;
Gia_Man_t * pNew, * pTemp;
Abc_Ntk_t * pModel;
Abc_Obj_t * pTerm;
Vec_Ptr_t * vSupers;
- int i;//, Counter = -1;
+ Vec_Ptr_t * vBuffers = fUseBufs ? Vec_PtrAlloc(1000) : NULL;
+ int i, Counter = 0;
assert( Abc_NtkIsNetlist(pNtk) );
// Abc_NtkPrintBoxInfo( pNtk );
- // create DFS order of nets
+ // set the PI/PO numbers
+ Counter -= Abc_NtkPiNum(pNtk) + Abc_NtkPoNum(pNtk);
if ( !pNtk->pDesign )
- Gia_ManFlattenLogicPrepare( pNtk );
+ Counter += Gia_ManFlattenLogicPrepare( pNtk );
else
Vec_PtrForEachEntry( Abc_Ntk_t *, pNtk->pDesign->vModules, pModel, i )
- Gia_ManFlattenLogicPrepare( pModel );
+ Counter += Gia_ManFlattenLogicPrepare( pModel );
// start the manager
pNew = Gia_ManStart( Abc_NtkObjNumMax(pNtk) );
pNew->pName = Abc_UtilStrsav(pNtk->pName);
pNew->pSpec = Abc_UtilStrsav(pNtk->pSpec);
- if ( fUseBufs )
- pNew->vBarBufs = Vec_IntAlloc( 1000 );
// create PIs and buffers
Abc_NtkForEachPi( pNtk, pTerm, i )
@@ -302,16 +307,20 @@ Gia_Man_t * Gia_ManFlattenLogicHierarchy( Abc_Ntk_t * pNtk )
vSupers = Vec_PtrAlloc( 100 );
Gia_ManHashAlloc( pNew );
Abc_NtkForEachPo( pNtk, pTerm, i )
- Gia_ManFlattenLogicHierarchy_rec( pNew, vSupers, pTerm, pNew->vBarBufs );
+ Gia_ManFlattenLogicHierarchy_rec( pNew, vSupers, pTerm, vBuffers );
Gia_ManHashStop( pNew );
Vec_PtrFree( vSupers );
- printf( "Hierarchy reader flattened %d instances of boxes.\n", pNtk->pDesign ? Vec_PtrSize(pNtk->pDesign->vModules)-1 : 0 );
+ printf( "Hierarchy reader flattened %d instances of boxes and added %d barbufs (out of %d).\n",
+ pNtk->pDesign ? Vec_PtrSize(pNtk->pDesign->vModules)-1 : 0, Vec_PtrSize(vBuffers), &Counter );
// create buffers and POs
Abc_NtkForEachPo( pNtk, pTerm, i )
Gia_ManAppendCo( pNew, pTerm->iTemp );
- // save buffers
-// Vec_IntPrint( pNew->vBarBufs );
+
+ if ( pvBuffers )
+ *pvBuffers = vBuffers;
+ else
+ Vec_PtrFreeP( &vBuffers );
// cleanup
pNew = Gia_ManCleanup( pTemp = pNew );
@@ -319,6 +328,100 @@ Gia_Man_t * Gia_ManFlattenLogicHierarchy( Abc_Ntk_t * pNtk )
return pNew;
}
+/**Function*************************************************************
+
+ Synopsis [Inserts the result of mapping into logic hierarchy.]
+
+ Description [When this procedure is called PIs/POs of pNtk
+ point to the corresponding nodes in network with barbufs.]
+
+ SideEffects []
+
+ SeeAlso []
+
+***********************************************************************/
+Abc_Obj_t * Gia_ManInsertOne_rec( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNew, Abc_Obj_t * pObj )
+{
+ Abc_Obj_t * pFanin; int i;
+ if ( pObj == NULL )
+ return Abc_NtkCreateNodeConst0( pNtk );
+ assert( Abc_ObjNtk(pObj) == pNew );
+ if ( pObj->pCopy )
+ return pObj->pCopy;
+ Abc_ObjForEachFanin( pObj, pFanin, i )
+ Gia_ManInsertOne_rec( pNtk, pNew, pFanin );
+ pObj->pCopy = Abc_NtkDupObj( pNtk, pObj, 0 );
+ Abc_ObjForEachFanin( pObj, pFanin, i )
+ Abc_ObjAddFanin( pObj, pFanin );
+ return pObj->pCopy;
+}
+void Gia_ManInsertOne( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNew )
+{
+ Abc_Obj_t * pObj, * pBox; int i, k;
+ // check that PIs point to barbufs
+ Abc_NtkForEachPi( pNtk, pObj, i )
+ assert( !pObj->pCopy || Abc_ObjNtk(pObj->pCopy) == pNew );
+ // make barbufs point to box outputs
+ Abc_NtkForEachBox( pNtk, pBox, i )
+ Abc_ObjForEachFanout( pBox, pObj, k )
+ {
+ pObj->pCopy = Abc_NtkPo(Abc_ObjModel(pBox), k)->pCopy;
+ assert( !pObj->pCopy || Abc_ObjNtk(pObj->pCopy) == pNew );
+ }
+ // remove internal nodes
+ Abc_NtkForEachNode( pNtk, pObj, i )
+ Abc_NtkDeleteObj( pObj );
+ // start traversal from box inputs
+ Abc_NtkForEachBox( pNtk, pBox, i )
+ Abc_ObjForEachFanin( pBox, pObj, k )
+ if ( Abc_ObjFaninNum(pObj) == 0 )
+ Abc_ObjAddFanin( pObj, Gia_ManInsertOne_rec(pNtk, pNew, Abc_NtkPi(Abc_ObjModel(pBox), k)->pCopy) );
+ // start traversal from primary outputs
+ Abc_NtkForEachPo( pNtk, pObj, i )
+ if ( Abc_ObjFaninNum(pObj) == 0 )
+ Abc_ObjAddFanin( pObj, Gia_ManInsertOne_rec(pNtk, pNew, pObj->pCopy) );
+}
+void Gia_ManInsertLogicHierarchy( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNew )
+{
+ Vec_Ptr_t * vBuffers;
+ Gia_Man_t * pGia = Gia_ManFlattenLogicHierarchy( pNtk, &vBuffers );
+ Abc_Ntk_t * pModel;
+ Abc_Obj_t * pObj;
+ int i;
+
+ assert( Gia_ManPiNum(pGia) == Abc_NtkPiNum(pNtk) );
+ assert( Gia_ManPiNum(pGia) == Abc_NtkPiNum(pNew) );
+ assert( Gia_ManPoNum(pGia) == Abc_NtkPoNum(pNtk) );
+ assert( Gia_ManPoNum(pGia) == Abc_NtkPoNum(pNew) );
+ assert( Gia_ManBufNum(pGia) == Vec_PtrSize(vBuffers) );
+ assert( Gia_ManBufNum(pGia) == pNew->nBarBufs2 );
+ Gia_ManStop( pGia );
+
+ // clean the networks
+ if ( !pNtk->pDesign )
+ Abc_NtkCleanCopy( pNtk );
+ else
+ Vec_PtrForEachEntry( Abc_Ntk_t *, pNtk->pDesign->vModules, pModel, i )
+ Abc_NtkCleanCopy( pModel );
+
+ // annotate PIs and POs of each network with barbufs
+ Abc_NtkForEachPi( pNew, pObj, i )
+ Abc_NtkPi(pNtk, i)->pCopy = pObj;
+ Abc_NtkForEachPo( pNew, pObj, i )
+ Abc_NtkPo(pNtk, i)->pCopy = pObj;
+ Abc_NtkForEachBarBuf( pNew, pObj, i )
+ ((Abc_Obj_t *)Vec_PtrEntry(vBuffers, i))->pCopy = pObj;
+ Vec_PtrFree( vBuffers );
+
+ // connect each model
+ Abc_NtkCleanCopy( pNew );
+ Gia_ManInsertOne( pNtk, pNew );
+ if ( pNtk->pDesign )
+ Vec_PtrForEachEntry( Abc_Ntk_t *, pNtk->pDesign->vModules, pModel, i )
+ if ( pModel != pNtk )
+ Gia_ManInsertOne( pModel, pNew );
+}
+
////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-05 00:46:06 +0000