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* Correcting incorrect handling of timing in several &-commands.Alan Mishchenko2014-08-257-44/+172
* Improving print-out of 'dsd -p'.Alan Mishchenko2014-08-224-1/+154
* Propagating timing support to the new synthesis/mapping commands.Alan Mishchenko2014-08-209-41/+34
* Extended command &cone to extract timing critical cones.Alan Mishchenko2014-08-193-39/+141
* Added command 'sparsify' to derive ISF from CSF.Alan Mishchenko2014-08-182-0/+212
* Changing default CNF generation in &bmc.Alan Mishchenko2014-08-183-1/+9
* Added DSD-based collapsing &dsd.Alan Mishchenko2014-08-162-2/+2
* Added DSD-based collapsing &dsd.Alan Mishchenko2014-08-161-2/+3
* Adding specialized matching to 'if'.Alan Mishchenko2014-08-161-1/+1
* Added DSD-based collapsing &dsd.Alan Mishchenko2014-08-161-0/+1
* Adding specialized matching to 'if'.Alan Mishchenko2014-08-166-0/+140
* Added DSD-based collapsing &dsd.Alan Mishchenko2014-08-165-5/+440
* Suggested fix to allow .constr files to have empty lines.Alan Mishchenko2014-08-131-0/+2
* Enabling circuit solver in &fraig.Alan Mishchenko2014-08-126-13/+100
* Bug fix in &fraig -L <num>.Alan Mishchenko2014-08-123-86/+5
* Bug fix in &fraig -L <num>.Alan Mishchenko2014-08-125-8/+107
* Increasing the size of pre-allocated memory in &syn2.Alan Mishchenko2014-08-111-1/+1
* Adding delay optimization to synthesis script &syn2.Alan Mishchenko2014-08-088-22/+123
* Enabling cofactoring in the mapper.Alan Mishchenko2014-08-062-2/+23
* Profiling code for SOP/DSD/LMS balancing.Alan Mishchenko2014-08-041-0/+69
* Compiler warnings.Alan Mishchenko2014-08-045-11/+67
* Enabling ISOP-based minimization in 'collapse' if EXDC is available.Alan Mishchenko2014-08-042-2/+35
* Compiler warnings.Alan Mishchenko2014-08-022-1/+2
* Profiling code for SOP/DSD/LMS balancing.Alan Mishchenko2014-08-025-0/+465
* Changes to the hopelessly limited Verilog parser to skip one-bit bit-ranges, ...Alan Mishchenko2014-08-021-4/+26
* Small changes.Alan Mishchenko2014-07-292-3/+4
* Adding support for standard-cell mapping.Alan Mishchenko2014-07-285-10/+147
* Generating abstraction of standard cell library.Alan Mishchenko2014-07-261-1/+1
* Generating abstraction of standard cell library.Alan Mishchenko2014-07-265-0/+397
* Generating abstraction of standard cell library.Alan Mishchenko2014-07-258-19/+181
* Fixing option 'if -G <num>' after changes.Alan Mishchenko2014-07-253-10/+10
* Adding message prefix.Alan Mishchenko2014-07-241-8/+9
* Bug fix in 'print_gates' due to the mix-up of the inverter.Alan Mishchenko2014-07-221-1/+1
* Undoing previous change to SOP balancing.Alan Mishchenko2014-07-221-6/+6
* Small improvement to SOP balancing.Alan Mishchenko2014-07-221-4/+16
* Small changes.Alan Mishchenko2014-07-212-36/+43
* Adding new command &sopb for resource-aware SOP balancing.Alan Mishchenko2014-07-218-35/+408
* Updates and changes to several packages.Alan Mishchenko2014-07-2012-40/+162
* Small changes in several packages.Alan Mishchenko2014-07-182-2/+3
* Small changes in several packages.Alan Mishchenko2014-07-172-2/+11
* Small changes in several packages.Alan Mishchenko2014-07-174-4/+55
* Improvements to profiling and printing statistics.Alan Mishchenko2014-07-093-23/+114
* Improvements to false path detection.Alan Mishchenko2014-07-091-25/+21
* Improvements to false path detection.Alan Mishchenko2014-07-084-28/+352
* Experiment with SOP balancing.Alan Mishchenko2014-07-021-1/+20
* Compiler warning.Alan Mishchenko2014-07-011-1/+1
* Improvements to representation of choices.Alan Mishchenko2014-07-011-144/+0
* Improvements to representation of choices.Alan Mishchenko2014-07-0115-66/+259
* Changes to align node IDs in Abc_Ntk_t representing a logic network with Abc_...Alan Mishchenko2014-06-301-14/+12
* Changes to align node IDs in Abc_Ntk_t representing a logic network with Abc_...Alan Mishchenko2014-06-301-10/+14
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