iCE40/abc - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Printing node type statistics.	Alan Mishchenko	2014-09-24	2	-2/+106
*	Bug fix in handling MUXes in Verilog parser, induced by recent changes.	Alan Mishchenko	2014-09-24	1	-0/+2
*	Added switch -t to &flow2.	Alan Mishchenko	2014-09-24	2	-9/+14
*	Added support of word-level MUXes represented as 'always'-statements.	Alan Mishchenko	2014-09-24	1	-2/+2
*	Added support of word-level MUXes represented as 'always'-statements.	Alan Mishchenko	2014-09-24	3	-18/+167
*	Enables dumping stats into a file.	Alan Mishchenko	2014-09-23	2	-1/+15
*	Extending &cec to take a single-output miter (usage of switch -d has changed!).	Alan Mishchenko	2014-09-23	3	-10/+50
*	Debugging the bit-blaster.	Alan Mishchenko	2014-09-23	1	-1/+15
*	Debugging the bit-blaster.	Alan Mishchenko	2014-09-23	2	-8/+28
*	Adding switch to enable SOP balancing in '&flow2'.	Alan Mishchenko	2014-09-21	2	-14/+30
*	Tuning the flow scripts.	Alan Mishchenko	2014-09-20	1	-1/+1
*	Extending resource limit.	Alan Mishchenko	2014-09-20	1	-2/+2
*	Tuning the flow scripts.	Alan Mishchenko	2014-09-20	2	-5/+70
*	Synchronizing packages.	Alan Mishchenko	2014-09-20	3	-6/+6
*	Synchronizing packages.	Alan Mishchenko	2014-09-20	1	-0/+2
*	Synchronizing packages.	Alan Mishchenko	2014-09-20	2	-3/+3
*	Synchronizing packages.	Alan Mishchenko	2014-09-20	2	-1/+3
*	Updating command 'dsd_clean'.	Alan Mishchenko	2014-09-20	4	-10/+45
*	Tuning the flow scripts.	Alan Mishchenko	2014-09-20	2	-141/+248
*	Updating DSD balance to handle XOR gate as having the same delay as AND gate.	Alan Mishchenko	2014-09-19	4	-10/+11
*	Improvements to Boolean matching.	Alan Mishchenko	2014-09-19	2	-33/+98
*	Improvements to Boolean matching.	Alan Mishchenko	2014-09-19	8	-88/+563
*	Improvements to Boolean matching.	Alan Mishchenko	2014-09-18	5	-14/+30
*	Improvements to Boolean matching.	Alan Mishchenko	2014-09-18	5	-19/+57
*	Improvements to Boolean matching.	Alan Mishchenko	2014-09-18	1	-14/+29
*	Improving DSD manager.	Alan Mishchenko	2014-09-18	3	-6/+89
*	Concurrency for Boolean matching.	Alan Mishchenko	2014-09-18	10	-65/+331
*	Improvements to Boolean matching.	Alan Mishchenko	2014-09-17	4	-64/+220
*	Improvements to word-level Verilog parser.	Alan Mishchenko	2014-09-17	2	-3/+4
*	Improvements to word-level Verilog parser.	Alan Mishchenko	2014-09-17	5	-230/+488
*	Spurious assertion.	Alan Mishchenko	2014-09-17	1	-1/+1
*	Improvements to word-level Verilog parser.	Alan Mishchenko	2014-09-16	5	-78/+277
*	Support for leakage power in Liberty parser and sizer.	Alan Mishchenko	2014-09-16	5	-5/+122
*	New choice computation.	Alan Mishchenko	2014-09-16	3	-22/+197
*	Code restructuring.	Alan Mishchenko	2014-09-16	7	-322/+432
*	Improvements to Boolean matching.	Alan Mishchenko	2014-09-16	2	-201/+568
*	Compiler error (duplicate typedef).	Alan Mishchenko	2014-09-15	1	-1/+0
*	Compiler warnings.	Alan Mishchenko	2014-09-12	4	-47/+47
*	Replacing tabs with spaces.	Alan Mishchenko	2014-09-12	1	-1/+1
*	New word-level representation package.	Alan Mishchenko	2014-09-12	15	-66/+2276
*	Resetting the random seed in 'sparsify'.	Alan Mishchenko	2014-09-11	1	-0/+1
*	Updating timing info during normalization.	Alan Mishchenko	2014-09-10	1	-1/+1
*	Updating timing info during normalization.	Alan Mishchenko	2014-09-10	1	-1/+3
*	Bug fix in transferring timing info.	Alan Mishchenko	2014-09-09	4	-6/+67
*	Corner-case bug fix in balancing.	Alan Mishchenko	2014-09-08	1	-0/+2
*	Added command 'move_names'.	Alan Mishchenko	2014-08-28	1	-1/+1
*	Added command 'move_names'.	Alan Mishchenko	2014-08-28	2	-0/+106
*	Tuning LUT mapping flow.	Alan Mishchenko	2014-08-28	2	-1/+5
*	Tuning LUT mapping flow.	Alan Mishchenko	2014-08-27	2	-4/+6
*	Compiler warning.	Alan Mishchenko	2014-08-27	1	-2/+2