Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Integrating SAT-based CEX minimization. | Alan Mishchenko | 2018-03-25 | 4 | -10/+145 |
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* | Adding new NPN code (compiler fix). | Alan Mishchenko | 2018-03-25 | 1 | -9/+9 |
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* | Adding new NPN code (compiler fix). | Alan Mishchenko | 2018-03-25 | 1 | -1/+1 |
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* | Adding new NPN code developed by XueGong Zhou at Fudan University. | Alan Mishchenko | 2018-03-25 | 4 | -144/+1098 |
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* | Updating &mfs to support hard objects. | Alan Mishchenko | 2018-03-23 | 2 | -2/+55 |
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* | Adding switch 'scorr -f' to dump inductive invariant as an AIG. | Alan Mishchenko | 2018-03-22 | 7 | -20/+36 |
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* | Temporary bug fix for signal names in WLC (correction). | Alan Mishchenko | 2018-03-21 | 1 | -2/+5 |
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* | Temporary bug fix for signal names in WLC. | Alan Mishchenko | 2018-03-21 | 1 | -0/+2 |
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* | Continuos integration support of both Travis CI (Linux and macOS) and ↵ | Baruch Sterin | 2018-03-11 | 3 | -1/+69 |
| | | | | Appveyor (Windows) | ||||
* | Bug fix in blasting with boxes. | Alan Mishchenko | 2018-03-06 | 1 | -1/+1 |
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* | Extending primitives supported by WLC. | Alan Mishchenko | 2018-03-03 | 3 | -5/+85 |
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* | Adding parameters and improvements to %blast. | Alan Mishchenko | 2018-02-28 | 6 | -1/+20 |
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* | Adding parameters and improvements to %blast. | Alan Mishchenko | 2018-02-28 | 13 | -101/+319 |
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* | Adding support for adders with carry-in in WLC and NDR. | Alan Mishchenko | 2018-02-24 | 5 | -5/+113 |
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* | Bug fix in NDR handling. | Alan Mishchenko | 2018-02-20 | 1 | -6/+38 |
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* | Merge two branches. | Alan Mishchenko | 2018-02-20 | 1 | -33/+81 |
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| * | Improvements to circuit based solver. | Alan Mishchenko | 2018-02-20 | 1 | -33/+81 |
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* | | Small fix in satoko. | Bruno Schmitt | 2018-02-20 | 2 | -3/+1 |
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* | Compilation problem with pow(). | Alan Mishchenko | 2018-02-19 | 4 | -7/+7 |
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* | Improvements to circuit based solver. | Alan Mishchenko | 2018-02-17 | 1 | -193/+490 |
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* | Extending MiniLUT to return attributes. | Alan Mishchenko | 2018-02-11 | 2 | -0/+20 |
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* | Experiments with LUT mapping. | Alan Mishchenko | 2018-02-10 | 3 | -14/+65 |
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* | Fixing input swapping issue in MUXes derived from NDR. | Alan Mishchenko | 2018-02-07 | 2 | -0/+4 |
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* | Suggested fix to compile on FreeBSD. | Alan Mishchenko | 2018-02-05 | 1 | -2/+11 |
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* | Improvements to NDR to represent hierarchical designs. | Alan Mishchenko | 2018-02-05 | 1 | -2/+2 |
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* | Improvements to NDR to represent hierarchical designs. | Alan Mishchenko | 2018-02-05 | 2 | -3/+2 |
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* | Improvements to NDR to represent hierarchical designs. | Alan Mishchenko | 2018-02-05 | 4 | -66/+219 |
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* | Suggested fix to compile on FreeBSD. | Alan Mishchenko | 2018-02-04 | 1 | -1/+3 |
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* | Adding support of reading and writing designs using a new internal format ↵ | Alan Mishchenko | 2018-01-29 | 1 | -18/+76 |
| | | | | (bug fix). | ||||
* | Adding support of reading and writing designs using a new internal format. | Alan Mishchenko | 2018-01-28 | 6 | -5/+368 |
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* | Experiments with circuit-based SAT. | Alan Mishchenko | 2018-01-27 | 1 | -26/+225 |
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* | Experiments with circuit-based SAT. | Alan Mishchenko | 2018-01-27 | 1 | -132/+94 |
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* | Experiments with circuit-based SAT. | Alan Mishchenko | 2018-01-27 | 1 | -31/+38 |
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* | Experiments with circuit-based SAT. | Alan Mishchenko | 2018-01-27 | 2 | -130/+165 |
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* | Experiments with circuit-based SAT. | Alan Mishchenko | 2018-01-27 | 6 | -5/+1309 |
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* | Experiments with SAT-based simulation. | Alan Mishchenko | 2018-01-25 | 8 | -18/+59 |
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* | Experiments with SAT-based simulation. | Alan Mishchenko | 2018-01-23 | 5 | -6/+146 |
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* | Updates to exact synthesis commands. | Alan Mishchenko | 2018-01-22 | 1 | -1/+0 |
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* | Updates to exact synthesis commands. | Alan Mishchenko | 2018-01-19 | 4 | -38/+226 |
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* | Backing up node's truth-table to make sure it is not destroyed while ↵ | Alan Mishchenko | 2018-01-19 | 1 | -2/+4 |
| | | | | deriving AIG. | ||||
* | Fixed crash in &nf when there is no buffer gate. | Alan Mishchenko | 2018-01-12 | 1 | -0/+5 |
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* | Merged in Fatsie/abc/liberty_value_expression (pull request #87) | Alan Mishchenko | 2018-01-05 | 1 | -0/+12 |
|\ | | | | | | | Allow expression in value in liberty file | ||||
| * | Created new branch liberty_value_expression | Staf Verhaegen | 2018-01-04 | 0 | -0/+0 |
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| * | Value of properties can be expression. | Staf Verhaegen | 2018-01-03 | 1 | -0/+12 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Example found in the 2007.03 Liberty Reference Manual that was also found in the wild: input_voltage(CMOS) { vil : 0.3 * VDD ; vih : 0.7 * VDD ; vimin : -0.5 ; vimax : VDD + 0.5 ; } Current implementation just parses the expression but no interpretation is done. | ||||
* | | New command 'testexact'. | Alan Mishchenko | 2018-01-04 | 1 | -2/+2 |
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* | | New command 'testexact'. | Alan Mishchenko | 2018-01-04 | 2 | -7/+348 |
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* | New exact synthesis command 'allexact'. | Alan Mishchenko | 2017-12-30 | 3 | -33/+97 |
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* | New exact synthesis command 'allexact'. | Alan Mishchenko | 2017-12-28 | 1 | -0/+2 |
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* | New exact synthesis command 'allexact'. | Alan Mishchenko | 2017-12-28 | 8 | -15/+1340 |
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* | Corner-case bug fixed in CNF generation. | Alan Mishchenko | 2017-12-28 | 1 | -0/+1 |
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