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* False path detection.Alan Mishchenko2013-10-311-0/+4
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* Specialized induction check.Alan Mishchenko2013-10-311-0/+4
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* Multi-output property solver.Alan Mishchenko2013-10-231-0/+4
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* Resubstitution code.Alan Mishchenko2013-10-061-0/+4
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* Towards better Boolean matching.Alan Mishchenko2013-10-051-144/+4
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* Experiment with the AIG package.Alan Mishchenko2013-10-031-0/+144
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* New logic sharing extraction.Alan Mishchenko2013-09-291-0/+4
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* New logic sharing extraction.Alan Mishchenko2013-09-281-0/+4
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* Performance balancing command &b.Alan Mishchenko2013-09-271-0/+4
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* Generation of plain AIG after mapping.Alan Mishchenko2013-09-271-0/+4
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* New logic sharing extraction.Alan Mishchenko2013-09-261-5/+1
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* Improving DAG-aware unmapping.Alan Mishchenko2013-09-251-0/+4
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* Infrastructure to support full Liberty format and unitification of library ↵Alan Mishchenko2013-09-151-2/+10
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* Updates for the new BMC engine.Alan Mishchenko2013-09-101-0/+4
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* Improvements to the new technology mapper.Alan Mishchenko2013-09-091-0/+4
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* Improvements to the new technology mapper.Alan Mishchenko2013-09-071-0/+4
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* Updates for the new BMC engine.Alan Mishchenko2013-09-051-0/+4
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* Adding interpolant computation sat_solver2.Alan Mishchenko2013-09-051-0/+4
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* Enabling additional matching feature in the LUT mapper.Alan Mishchenko2013-08-121-0/+4
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* Integrated buffering and sizing.Alan Mishchenko2013-08-081-0/+4
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* SAT solver with dynamic CNF loading.Alan Mishchenko2013-08-011-0/+4
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* Improved buffering.Alan Mishchenko2013-07-291-4/+0
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* Improved gate-sizing.Alan Mishchenko2013-07-291-0/+4
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* Restructuring gate-sizing code trying to separate timing analysis.Alan Mishchenko2013-07-211-4/+8
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* Added command 'dnsize' to complement command 'upsize'.Alan Mishchenko2013-07-201-0/+4
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* New technology mapper.Alan Mishchenko2013-07-171-0/+4
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* New technology mapper.Alan Mishchenko2013-07-131-0/+8
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* New technology mapper.Alan Mishchenko2013-07-121-8/+52
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* Adding commands 'bm2' and 'saucy3' developed by Hadi Katebi, Igor Markov, ↵Alan Mishchenko2013-07-011-0/+4
| | | | and Karem Sakallah at U Michigan.
* Unifying representation of mapping in GIA.Alan Mishchenko2013-06-251-4/+0
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* New features to debug an test tech-mapping with choices.Alan Mishchenko2013-06-241-0/+20
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* Limiting runtime limit checks in 'pdr'.Alan Mishchenko2013-06-221-0/+4
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* Integrating new MFS package with GIA manager.Alan Mishchenko2013-06-041-0/+4
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* New DSD detection code.Alan Mishchenko2013-05-301-0/+4
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* Multiplexer profiling.Alan Mishchenko2013-05-271-0/+4
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* Counter-example depth minimization.Alan Mishchenko2013-05-221-0/+4
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* New MFS package.Alan Mishchenko2013-05-121-3/+7
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* Procedures for sorting fanins of the nodes.Alan Mishchenko2013-05-061-0/+28
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* Reading/writing MiniAIG and several minor changes.Alan Mishchenko2013-05-031-0/+4
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* Faster isomorphism detection (command &iso).Alan Mishchenko2013-05-011-0/+4
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* New fast extract.Alan Mishchenko2013-04-271-0/+12
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* SAT sweeping under constraints.Alan Mishchenko2013-04-251-0/+32
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* New MFS package.Alan Mishchenko2013-04-021-0/+32
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* Shrink for 6-LUTs.Alan Mishchenko2013-03-311-0/+24
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* User-controlable SAT sweeper.Alan Mishchenko2013-02-251-0/+4
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* Started PO partitioning command.Alan Mishchenko2013-02-241-0/+4
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* Adding STG generation (&era -d) and STG encoding (&read_stg <file>).Alan Mishchenko2013-02-191-0/+4
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* Integrating sweeping information.Alan Mishchenko2013-02-181-0/+4
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* Integration of timing manager.Alan Mishchenko2013-02-031-0/+4
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* Technology mapper.Alan Mishchenko2013-01-081-0/+8
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