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yosys-experimental
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Author
Age
Files
Lines
*
Experiments with recent ideas.
Alan Mishchenko
2014-03-18
1
-0
/
+4
*
Adding barrier buffers.
Alan Mishchenko
2014-03-16
1
-0
/
+4
*
Experiments with simulation.
Alan Mishchenko
2014-03-14
1
-0
/
+4
*
Changes to LUT mappers.
Alan Mishchenko
2014-03-08
1
-0
/
+4
*
Experiments with delay fault testing.
Alan Mishchenko
2014-03-04
1
-0
/
+4
*
Changes to LUT mappers.
Alan Mishchenko
2014-02-27
1
-0
/
+4
*
Changes to LUT mappers.
Alan Mishchenko
2014-02-17
1
-0
/
+4
*
Removing unused LMS code.
Alan Mishchenko
2014-02-16
1
-8
/
+0
*
Initial new interpolation code.
Alan Mishchenko
2014-01-28
1
-0
/
+4
*
Structural mapper into structures.
Alan Mishchenko
2013-11-12
1
-0
/
+4
*
False path detection.
Alan Mishchenko
2013-10-31
1
-0
/
+4
*
Specialized induction check.
Alan Mishchenko
2013-10-31
1
-0
/
+4
*
Multi-output property solver.
Alan Mishchenko
2013-10-23
1
-0
/
+4
*
Resubstitution code.
Alan Mishchenko
2013-10-06
1
-0
/
+4
*
Towards better Boolean matching.
Alan Mishchenko
2013-10-05
1
-144
/
+4
*
Experiment with the AIG package.
Alan Mishchenko
2013-10-03
1
-0
/
+144
*
New logic sharing extraction.
Alan Mishchenko
2013-09-29
1
-0
/
+4
*
New logic sharing extraction.
Alan Mishchenko
2013-09-28
1
-0
/
+4
*
Performance balancing command &b.
Alan Mishchenko
2013-09-27
1
-0
/
+4
*
Generation of plain AIG after mapping.
Alan Mishchenko
2013-09-27
1
-0
/
+4
*
New logic sharing extraction.
Alan Mishchenko
2013-09-26
1
-5
/
+1
*
Improving DAG-aware unmapping.
Alan Mishchenko
2013-09-25
1
-0
/
+4
*
Infrastructure to support full Liberty format and unitification of library re...
Alan Mishchenko
2013-09-15
1
-2
/
+10
*
Updates for the new BMC engine.
Alan Mishchenko
2013-09-10
1
-0
/
+4
*
Improvements to the new technology mapper.
Alan Mishchenko
2013-09-09
1
-0
/
+4
*
Improvements to the new technology mapper.
Alan Mishchenko
2013-09-07
1
-0
/
+4
*
Updates for the new BMC engine.
Alan Mishchenko
2013-09-05
1
-0
/
+4
*
Adding interpolant computation sat_solver2.
Alan Mishchenko
2013-09-05
1
-0
/
+4
*
Enabling additional matching feature in the LUT mapper.
Alan Mishchenko
2013-08-12
1
-0
/
+4
*
Integrated buffering and sizing.
Alan Mishchenko
2013-08-08
1
-0
/
+4
*
SAT solver with dynamic CNF loading.
Alan Mishchenko
2013-08-01
1
-0
/
+4
*
Improved buffering.
Alan Mishchenko
2013-07-29
1
-4
/
+0
*
Improved gate-sizing.
Alan Mishchenko
2013-07-29
1
-0
/
+4
*
Restructuring gate-sizing code trying to separate timing analysis.
Alan Mishchenko
2013-07-21
1
-4
/
+8
*
Added command 'dnsize' to complement command 'upsize'.
Alan Mishchenko
2013-07-20
1
-0
/
+4
*
New technology mapper.
Alan Mishchenko
2013-07-17
1
-0
/
+4
*
New technology mapper.
Alan Mishchenko
2013-07-13
1
-0
/
+8
*
New technology mapper.
Alan Mishchenko
2013-07-12
1
-8
/
+52
*
Adding commands 'bm2' and 'saucy3' developed by Hadi Katebi, Igor Markov, and...
Alan Mishchenko
2013-07-01
1
-0
/
+4
*
Unifying representation of mapping in GIA.
Alan Mishchenko
2013-06-25
1
-4
/
+0
*
New features to debug an test tech-mapping with choices.
Alan Mishchenko
2013-06-24
1
-0
/
+20
*
Limiting runtime limit checks in 'pdr'.
Alan Mishchenko
2013-06-22
1
-0
/
+4
*
Integrating new MFS package with GIA manager.
Alan Mishchenko
2013-06-04
1
-0
/
+4
*
New DSD detection code.
Alan Mishchenko
2013-05-30
1
-0
/
+4
*
Multiplexer profiling.
Alan Mishchenko
2013-05-27
1
-0
/
+4
*
Counter-example depth minimization.
Alan Mishchenko
2013-05-22
1
-0
/
+4
*
New MFS package.
Alan Mishchenko
2013-05-12
1
-3
/
+7
*
Procedures for sorting fanins of the nodes.
Alan Mishchenko
2013-05-06
1
-0
/
+28
*
Reading/writing MiniAIG and several minor changes.
Alan Mishchenko
2013-05-03
1
-0
/
+4
*
Faster isomorphism detection (command &iso).
Alan Mishchenko
2013-05-01
1
-0
/
+4
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