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path: root/src/aig/gia/gia.h
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* Adding one API of GIA manager.Alan Mishchenko2019-01-121-0/+18
* Adding switch &w -n to modify the comment section of the AIGER file written.Alan Mishchenko2018-11-211-1/+1
* Adding switch &w -p to dump AIG in a Verilog file.Alan Mishchenko2018-04-251-0/+1
* Experiments with LUT mapping.Alan Mishchenko2018-02-101-0/+1
* Experiments with SAT-based simulation.Alan Mishchenko2018-01-251-1/+2
* Experiments with SAT-based simulation.Alan Mishchenko2018-01-231-0/+10
* Experiments with AIG-based simulation.Alan Mishchenko2017-12-051-2/+14
* Portability changes for gcc-6 suggested by Clifford.Alan Mishchenko2017-12-021-6/+4
* Improvements to AIG-based quantification.Alan Mishchenko2017-11-261-1/+8
* Extracting CSAT interface and several cleanups.Alan Mishchenko2017-11-131-0/+5
* Changes to make GIA structural hashing use a dedicated array instead of pObj-...Alan Mishchenko2017-11-131-3/+4
* Improvements to quantification.Alan Mishchenko2017-11-131-0/+11
* Profiling quantification and other changes.Alan Mishchenko2017-11-061-0/+5
* Profiling quantification and other changes.Alan Mishchenko2017-11-061-0/+11
* Improvements to quantification.Alan Mishchenko2017-10-291-0/+3
* Improvements to SAT based SOP computation.Alan Mishchenko2017-10-061-0/+1
* Adding printout of slack distribution for mapped networks.Alan Mishchenko2017-10-021-0/+1
* Several small changes.Alan Mishchenko2017-09-051-0/+3
* Supporting CO attributes in GIA.Alan Mishchenko2017-07-121-0/+1
* Adding new command line options for &verify and &synch2.Alan Mishchenko2017-07-061-1/+1
* Synchronizing various data-structures.Alan Mishchenko2017-07-041-0/+5
* Experiments with support minimization.Alan Mishchenko2017-04-291-0/+4
* Experiments with support minimization.Alan Mishchenko2017-04-271-0/+6
* Removing unused procedure.Alan Mishchenko2017-02-221-1/+0
* Experiments with SAT sweeping.Alan Mishchenko2017-02-181-5/+9
* Word-level abstraction engine.Alan Mishchenko2017-02-151-0/+1
* Standardizing the use of new CNF generator. Adding CNF variable connectivity ...Alan Mishchenko2017-02-101-0/+2
* Updates to arithmetic verification.Alan Mishchenko2017-01-151-0/+2
* Updates to arithmetic verification.Alan Mishchenko2017-01-141-0/+1
* Adding print-out of critical path for mapped AIGs to &show.Alan Mishchenko2017-01-131-1/+1
* Updates to arithmetic verification.Alan Mishchenko2017-01-121-0/+1
* Updates to delay optimization project.Alan Mishchenko2016-12-311-15/+38
* Several changes in arithmetic circuit manipulation.Alan Mishchenko2016-12-221-1/+1
* Adding support for minimalistic representation of LUT mapping.Alan Mishchenko2016-12-051-0/+2
* Adding new command 'dump_equiv'.Alan Mishchenko2016-07-211-0/+6
* Enabling AIGs without structural hashing (&get -c to import logic network).Alan Mishchenko2016-05-201-9/+12
* Enabling AIGs without structural hashing.Alan Mishchenko2016-05-201-1/+1
* Switch &miter -y to convert a two-word miter into a dual-output miter.Alan Mishchenko2016-05-201-0/+1
* Enabling AIGs without structural hashing.Alan Mishchenko2016-05-201-3/+4
* Experiments with CEC for arithmetic circuits.Alan Mishchenko2016-05-111-0/+1
* Experiments with CEC for arithmetic circuits.Alan Mishchenko2016-05-081-1/+1
* Experiments with CEC for arithmetic circuits.Alan Mishchenko2016-05-071-0/+6
* Adding option to rehash AIG after mapping.Alan Mishchenko2016-04-271-1/+1
* Using seed assignment of edges in &edge.Alan Mishchenko2016-04-271-0/+1
* Improved algo for edge computation.Alan Mishchenko2016-04-221-1/+1
* Experimental algorithm for edge optimization.Alan Mishchenko2016-04-131-0/+6
* Supporting edge information during mapping.Alan Mishchenko2016-04-111-2/+2
* Adding AIG rehashing after LUT mapping in Gia.Alan Mishchenko2016-04-071-0/+1
* Supporting edges in delay-optimization in &satlut.Alan Mishchenko2016-04-071-0/+1
* Supporting edges in delay-optimization in &satlut.Alan Mishchenko2016-04-071-0/+8
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