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path: root/src/aig/gia/gia.h
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* Experimental algorithm for edge optimization.Alan Mishchenko2016-04-131-0/+6
* Supporting edge information during mapping.Alan Mishchenko2016-04-111-2/+2
* Adding AIG rehashing after LUT mapping in Gia.Alan Mishchenko2016-04-071-0/+1
* Supporting edges in delay-optimization in &satlut.Alan Mishchenko2016-04-071-0/+1
* Supporting edges in delay-optimization in &satlut.Alan Mishchenko2016-04-071-0/+8
* Supporting edge information during mapping.Alan Mishchenko2016-04-061-0/+9
* Improvements to delay-optimization in &satlut.Alan Mishchenko2016-04-041-1/+1
* Improvements to delay-optimization in &satlut.Alan Mishchenko2016-04-041-0/+1
* Enabling native Gia visualization in &show.Alan Mishchenko2016-04-031-2/+6
* Windowing for technology mapping.Alan Mishchenko2016-03-301-1/+22
* Windowing for technology mapping.Alan Mishchenko2016-03-291-12/+21
* New command to dump LUT network.Alan Mishchenko2016-01-161-0/+1
* Adding switch &miter -x for XORs outputs of two word-level POs.Alan Mishchenko2016-01-061-0/+1
* Migrating back to using 'float' in area-flow computation in &nf.Alan Mishchenko2016-01-051-0/+1
* Improvements to 'satclp' (unfinished).Alan Mishchenko2015-11-061-0/+2
* Improvements to 'satclp'.Alan Mishchenko2015-10-281-0/+1
* Added several knobs to control QoR in &nf.Alan Mishchenko2015-10-201-0/+2
* Adding support for black boxes in extended AIG.Alan Mishchenko2015-10-041-0/+1
* Adding support for flop init-states in extended AIG.Alan Mishchenko2015-10-041-0/+1
* Experiments with LUT structure mapping.Alan Mishchenko2015-09-271-0/+3
* Improvements to &b -das.Alan Mishchenko2015-09-181-0/+1
* Adding switch to &b to prevent dumplicated area when used in delay-mode (&b -...Alan Mishchenko2015-09-181-1/+1
* Performance tuning of the Nf.Alan Mishchenko2015-08-311-0/+3
* Adding switch to control area-recovery and more tuning in &nf.Alan Mishchenko2015-08-281-0/+1
* Adding new GIA duplication API.Alan Mishchenko2015-07-211-0/+1
* New TFI/TFO profiling code.Alan Mishchenko2015-07-091-1/+3
* Small changes to enable collecting results using &ps -D file.Alan Mishchenko2015-07-091-0/+2
* Sequential word-level simulator for Wlc_Ntk_t.Alan Mishchenko2015-06-041-0/+3
* Properly copying and saving the timing info in &get and &put.Alan Mishchenko2015-04-041-0/+2
* Print-out of sequential equivalences in &scorr.Alan Mishchenko2015-03-311-1/+1
* Support for representing programmable cell configuration data.Alan Mishchenko2015-03-081-0/+2
* Adding switch '-p' to control pin-permutation in &nf.Alan Mishchenko2015-02-081-0/+1
* Integrating barrier buffers.Alan Mishchenko2014-12-111-4/+7
* Integrating barrier buffers.Alan Mishchenko2014-12-081-1/+7
* Improvements to handling boxes and flops.Alan Mishchenko2014-11-251-0/+1
* Adding integrity check for boxes and flops.Alan Mishchenko2014-11-251-0/+4
* Improvements to handling boxes and flops.Alan Mishchenko2014-11-241-1/+1
* Improvements to handling boxes and flops.Alan Mishchenko2014-11-241-3/+5
* Fix in reading flop classes.Alan Mishchenko2014-11-211-0/+1
* Integrating mfs2 package to work with boxes.Alan Mishchenko2014-11-161-0/+5
* Enabling AIGs with boxes for word-level and sequential designs.Alan Mishchenko2014-11-141-0/+2
* Enabling AIGs with boxes for word-level and sequential designs.Alan Mishchenko2014-11-131-3/+3
* Added switch -i to &filter to use FIs instead of FOs.Alan Mishchenko2014-11-111-1/+1
* Generation of barrier-buffers for hierarchical design.Alan Mishchenko2014-11-101-0/+1
* Detecting full-adder chains and putting them into white boxes.Alan Mishchenko2014-11-091-0/+7
* Making public some APIs.Alan Mishchenko2014-11-031-1/+20
* Adding MAJ gate to GIA package.Alan Mishchenko2014-10-261-0/+1
* MUX decomposition during mapping.Alan Mishchenko2014-10-121-1/+2
* Deriving cell mapping with &if -kz.Alan Mishchenko2014-10-041-5/+9
* Extending &cec to take a single-output miter (usage of switch -d has changed!).Alan Mishchenko2014-09-231-0/+1
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