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path: root/src/aig/gia/gia.h
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* Synchronizing various data-structures.Alan Mishchenko2017-07-041-0/+5
* Experiments with support minimization.Alan Mishchenko2017-04-291-0/+4
* Experiments with support minimization.Alan Mishchenko2017-04-271-0/+6
* Removing unused procedure.Alan Mishchenko2017-02-221-1/+0
* Experiments with SAT sweeping.Alan Mishchenko2017-02-181-5/+9
* Word-level abstraction engine.Alan Mishchenko2017-02-151-0/+1
* Standardizing the use of new CNF generator. Adding CNF variable connectivity ...Alan Mishchenko2017-02-101-0/+2
* Updates to arithmetic verification.Alan Mishchenko2017-01-151-0/+2
* Updates to arithmetic verification.Alan Mishchenko2017-01-141-0/+1
* Adding print-out of critical path for mapped AIGs to &show.Alan Mishchenko2017-01-131-1/+1
* Updates to arithmetic verification.Alan Mishchenko2017-01-121-0/+1
* Updates to delay optimization project.Alan Mishchenko2016-12-311-15/+38
* Several changes in arithmetic circuit manipulation.Alan Mishchenko2016-12-221-1/+1
* Adding support for minimalistic representation of LUT mapping.Alan Mishchenko2016-12-051-0/+2
* Adding new command 'dump_equiv'.Alan Mishchenko2016-07-211-0/+6
* Enabling AIGs without structural hashing (&get -c to import logic network).Alan Mishchenko2016-05-201-9/+12
* Enabling AIGs without structural hashing.Alan Mishchenko2016-05-201-1/+1
* Switch &miter -y to convert a two-word miter into a dual-output miter.Alan Mishchenko2016-05-201-0/+1
* Enabling AIGs without structural hashing.Alan Mishchenko2016-05-201-3/+4
* Experiments with CEC for arithmetic circuits.Alan Mishchenko2016-05-111-0/+1
* Experiments with CEC for arithmetic circuits.Alan Mishchenko2016-05-081-1/+1
* Experiments with CEC for arithmetic circuits.Alan Mishchenko2016-05-071-0/+6
* Adding option to rehash AIG after mapping.Alan Mishchenko2016-04-271-1/+1
* Using seed assignment of edges in &edge.Alan Mishchenko2016-04-271-0/+1
* Improved algo for edge computation.Alan Mishchenko2016-04-221-1/+1
* Experimental algorithm for edge optimization.Alan Mishchenko2016-04-131-0/+6
* Supporting edge information during mapping.Alan Mishchenko2016-04-111-2/+2
* Adding AIG rehashing after LUT mapping in Gia.Alan Mishchenko2016-04-071-0/+1
* Supporting edges in delay-optimization in &satlut.Alan Mishchenko2016-04-071-0/+1
* Supporting edges in delay-optimization in &satlut.Alan Mishchenko2016-04-071-0/+8
* Supporting edge information during mapping.Alan Mishchenko2016-04-061-0/+9
* Improvements to delay-optimization in &satlut.Alan Mishchenko2016-04-041-1/+1
* Improvements to delay-optimization in &satlut.Alan Mishchenko2016-04-041-0/+1
* Enabling native Gia visualization in &show.Alan Mishchenko2016-04-031-2/+6
* Windowing for technology mapping.Alan Mishchenko2016-03-301-1/+22
* Windowing for technology mapping.Alan Mishchenko2016-03-291-12/+21
* New command to dump LUT network.Alan Mishchenko2016-01-161-0/+1
* Adding switch &miter -x for XORs outputs of two word-level POs.Alan Mishchenko2016-01-061-0/+1
* Migrating back to using 'float' in area-flow computation in &nf.Alan Mishchenko2016-01-051-0/+1
* Improvements to 'satclp' (unfinished).Alan Mishchenko2015-11-061-0/+2
* Improvements to 'satclp'.Alan Mishchenko2015-10-281-0/+1
* Added several knobs to control QoR in &nf.Alan Mishchenko2015-10-201-0/+2
* Adding support for black boxes in extended AIG.Alan Mishchenko2015-10-041-0/+1
* Adding support for flop init-states in extended AIG.Alan Mishchenko2015-10-041-0/+1
* Experiments with LUT structure mapping.Alan Mishchenko2015-09-271-0/+3
* Improvements to &b -das.Alan Mishchenko2015-09-181-0/+1
* Adding switch to &b to prevent dumplicated area when used in delay-mode (&b -...Alan Mishchenko2015-09-181-1/+1
* Performance tuning of the Nf.Alan Mishchenko2015-08-311-0/+3
* Adding switch to control area-recovery and more tuning in &nf.Alan Mishchenko2015-08-281-0/+1
* Adding new GIA duplication API.Alan Mishchenko2015-07-211-0/+1
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