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path: root/src/aig/gia/gia.h
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* Sequential word-level simulator for Wlc_Ntk_t.Alan Mishchenko2015-06-041-0/+3
* Properly copying and saving the timing info in &get and &put.Alan Mishchenko2015-04-041-0/+2
* Print-out of sequential equivalences in &scorr.Alan Mishchenko2015-03-311-1/+1
* Support for representing programmable cell configuration data.Alan Mishchenko2015-03-081-0/+2
* Adding switch '-p' to control pin-permutation in &nf.Alan Mishchenko2015-02-081-0/+1
* Integrating barrier buffers.Alan Mishchenko2014-12-111-4/+7
* Integrating barrier buffers.Alan Mishchenko2014-12-081-1/+7
* Improvements to handling boxes and flops.Alan Mishchenko2014-11-251-0/+1
* Adding integrity check for boxes and flops.Alan Mishchenko2014-11-251-0/+4
* Improvements to handling boxes and flops.Alan Mishchenko2014-11-241-1/+1
* Improvements to handling boxes and flops.Alan Mishchenko2014-11-241-3/+5
* Fix in reading flop classes.Alan Mishchenko2014-11-211-0/+1
* Integrating mfs2 package to work with boxes.Alan Mishchenko2014-11-161-0/+5
* Enabling AIGs with boxes for word-level and sequential designs.Alan Mishchenko2014-11-141-0/+2
* Enabling AIGs with boxes for word-level and sequential designs.Alan Mishchenko2014-11-131-3/+3
* Added switch -i to &filter to use FIs instead of FOs.Alan Mishchenko2014-11-111-1/+1
* Generation of barrier-buffers for hierarchical design.Alan Mishchenko2014-11-101-0/+1
* Detecting full-adder chains and putting them into white boxes.Alan Mishchenko2014-11-091-0/+7
* Making public some APIs.Alan Mishchenko2014-11-031-1/+20
* Adding MAJ gate to GIA package.Alan Mishchenko2014-10-261-0/+1
* MUX decomposition during mapping.Alan Mishchenko2014-10-121-1/+2
* Deriving cell mapping with &if -kz.Alan Mishchenko2014-10-041-5/+9
* Extending &cec to take a single-output miter (usage of switch -d has changed!).Alan Mishchenko2014-09-231-0/+1
* Adding commands to save/load best network.Alan Mishchenko2014-08-261-0/+3
* Improving GIA interfaces for some procedures.Alan Mishchenko2014-08-251-4/+4
* Correcting incorrect handling of timing in several &-commands.Alan Mishchenko2014-08-251-2/+3
* Propagating timing support to the new synthesis/mapping commands.Alan Mishchenko2014-08-201-0/+2
* Extended command &cone to extract timing critical cones.Alan Mishchenko2014-08-191-1/+2
* Adding delay optimization to synthesis script &syn2.Alan Mishchenko2014-08-081-1/+2
* Enabling cofactoring in the mapper.Alan Mishchenko2014-08-061-0/+1
* Adding support for standard-cell mapping.Alan Mishchenko2014-07-281-10/+27
* Adding new command &sopb for resource-aware SOP balancing.Alan Mishchenko2014-07-211-1/+6
* Updates and changes to several packages.Alan Mishchenko2014-07-201-3/+6
* Small changes in several packages.Alan Mishchenko2014-07-171-0/+1
* Improvements to false path detection.Alan Mishchenko2014-07-081-0/+1
* Improvements to representation of choices.Alan Mishchenko2014-07-011-1/+7
* Changes and improvements to different packages.Alan Mishchenko2014-06-261-14/+35
* Improvements to power-aware mapping.Alan Mishchenko2014-06-231-0/+1
* Experiments with cofactoring variables.Alan Mishchenko2014-06-201-1/+2
* New tools for profiling verification miters.Alan Mishchenko2014-06-201-0/+3
* Various changes to enable better CNF generation.Alan Mishchenko2014-06-171-0/+3
* Bug fix in CEC generation after rarity simulation and few small changes.Alan Mishchenko2014-06-161-0/+1
* Updates and bug fixes.Alan Mishchenko2014-06-151-0/+1
* Adding more features to the synthesis script &syn2.Alan Mishchenko2014-06-141-1/+1
* Specializing some truth-table functions to 6 inputs.Alan Mishchenko2014-06-141-0/+1
* Various modifications.Alan Mishchenko2014-06-121-2/+7
* Enabling switching activity.Alan Mishchenko2014-06-121-0/+1
* Integrating recent changes.Alan Mishchenko2014-06-121-0/+4
* Various modifications.Alan Mishchenko2014-06-101-0/+9
* Adding CEC command &splitprove.Alan Mishchenko2014-06-041-0/+1
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