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* Various changes.Alan Mishchenko2021-10-221-0/+7
* Experiments with pattern generation.Alan Mishchenko2021-10-101-0/+2
* Various changes.Alan Mishchenko2021-10-061-0/+1
* Various changes.Alan Mishchenko2021-09-301-0/+6
* Improving MiniAIG and name manager.Alan Mishchenko2021-09-161-1/+1
* Various changes.Alan Mishchenko2021-09-141-1/+9
* Various changes.Alan Mishchenko2021-09-021-0/+8
* Improving AIG to Verilog converter.Alan Mishchenko2021-08-171-1/+1
* Adding node ordering options to command &dfs.Alan Mishchenko2021-08-051-1/+1
* Experiments with simulation.Alan Mishchenko2020-12-301-0/+1
* Adding switch to replace proved outputs by const0.Alan Mishchenko2020-12-161-1/+1
* Experiments with MFFC computation.Alan Mishchenko2020-11-151-0/+2
* Improvements to the SAT sweeper.Alan Mishchenko2020-11-141-0/+1
* Experiments with SAT sweeping.Alan Mishchenko2020-11-091-1/+3
* Experimental cost function in technology mapping.Alan Mishchenko2020-11-011-0/+1
* Experiment with structural similarity.Alan Mishchenko2020-07-161-0/+3
* Experimental resubstitution.Alan Mishchenko2020-05-151-2/+2
* Compiler warnings and errors.Alan Mishchenko2020-05-031-0/+3
* Experimental resubstitution.Alan Mishchenko2020-05-031-0/+1
* Experiments with simulation-based engines.Alan Mishchenko2020-03-221-0/+2
* Various changes.Alan Mishchenko2020-03-211-1/+2
* Various changes.Alan Mishchenko2020-03-181-1/+1
* Ongoing changes to the simulator.Alan Mishchenko2020-03-091-8/+2
* Updating and extending simulation data structures.Alan Mishchenko2020-03-051-5/+4
* Adding commands to generate data for experiments.Alan Mishchenko2020-02-231-0/+8
* Making &gla iterate over property outputs.Alan Mishchenko2019-12-111-0/+1
* Changes to several APIs.Alan Mishchenko2019-11-031-0/+2
* Experiments with simulation.Alan Mishchenko2019-10-271-1/+3
* Adding miter construction with one bit-level output for each pair of word-lev...Alan Mishchenko2019-04-141-0/+1
* Fixing several other type conversion warnings.Alan Mishchenko2019-03-051-24/+24
* Fixing some warnings with -Wconversion.Alan Mishchenko2019-03-051-1/+1
* Adding switch -x to &ps to disable color printout.Alan Mishchenko2019-02-121-0/+1
* Exploring other ways of CEX writing.Alan Mishchenko2019-01-211-1/+1
* Adding one API of GIA manager.Alan Mishchenko2019-01-121-0/+18
* Adding switch &w -n to modify the comment section of the AIGER file written.Alan Mishchenko2018-11-211-1/+1
* Adding switch &w -p to dump AIG in a Verilog file.Alan Mishchenko2018-04-251-0/+1
* Experiments with LUT mapping.Alan Mishchenko2018-02-101-0/+1
* Experiments with SAT-based simulation.Alan Mishchenko2018-01-251-1/+2
* Experiments with SAT-based simulation.Alan Mishchenko2018-01-231-0/+10
* Experiments with AIG-based simulation.Alan Mishchenko2017-12-051-2/+14
* Portability changes for gcc-6 suggested by Clifford.Alan Mishchenko2017-12-021-6/+4
* Improvements to AIG-based quantification.Alan Mishchenko2017-11-261-1/+8
* Extracting CSAT interface and several cleanups.Alan Mishchenko2017-11-131-0/+5
* Changes to make GIA structural hashing use a dedicated array instead of pObj-...Alan Mishchenko2017-11-131-3/+4
* Improvements to quantification.Alan Mishchenko2017-11-131-0/+11
* Profiling quantification and other changes.Alan Mishchenko2017-11-061-0/+5
* Profiling quantification and other changes.Alan Mishchenko2017-11-061-0/+11
* Improvements to quantification.Alan Mishchenko2017-10-291-0/+3
* Improvements to SAT based SOP computation.Alan Mishchenko2017-10-061-0/+1
* Adding printout of slack distribution for mapped networks.Alan Mishchenko2017-10-021-0/+1
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