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iCE40/abc
yosys-experimental
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aig
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gia
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gia.h
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Author
Age
Files
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*
Standardizing the use of new CNF generator. Adding CNF variable connectivity ...
Alan Mishchenko
2017-02-10
1
-0
/
+2
*
Updates to arithmetic verification.
Alan Mishchenko
2017-01-15
1
-0
/
+2
*
Updates to arithmetic verification.
Alan Mishchenko
2017-01-14
1
-0
/
+1
*
Adding print-out of critical path for mapped AIGs to &show.
Alan Mishchenko
2017-01-13
1
-1
/
+1
*
Updates to arithmetic verification.
Alan Mishchenko
2017-01-12
1
-0
/
+1
*
Updates to delay optimization project.
Alan Mishchenko
2016-12-31
1
-15
/
+38
*
Several changes in arithmetic circuit manipulation.
Alan Mishchenko
2016-12-22
1
-1
/
+1
*
Adding support for minimalistic representation of LUT mapping.
Alan Mishchenko
2016-12-05
1
-0
/
+2
*
Adding new command 'dump_equiv'.
Alan Mishchenko
2016-07-21
1
-0
/
+6
*
Enabling AIGs without structural hashing (&get -c to import logic network).
Alan Mishchenko
2016-05-20
1
-9
/
+12
*
Enabling AIGs without structural hashing.
Alan Mishchenko
2016-05-20
1
-1
/
+1
*
Switch &miter -y to convert a two-word miter into a dual-output miter.
Alan Mishchenko
2016-05-20
1
-0
/
+1
*
Enabling AIGs without structural hashing.
Alan Mishchenko
2016-05-20
1
-3
/
+4
*
Experiments with CEC for arithmetic circuits.
Alan Mishchenko
2016-05-11
1
-0
/
+1
*
Experiments with CEC for arithmetic circuits.
Alan Mishchenko
2016-05-08
1
-1
/
+1
*
Experiments with CEC for arithmetic circuits.
Alan Mishchenko
2016-05-07
1
-0
/
+6
*
Adding option to rehash AIG after mapping.
Alan Mishchenko
2016-04-27
1
-1
/
+1
*
Using seed assignment of edges in &edge.
Alan Mishchenko
2016-04-27
1
-0
/
+1
*
Improved algo for edge computation.
Alan Mishchenko
2016-04-22
1
-1
/
+1
*
Experimental algorithm for edge optimization.
Alan Mishchenko
2016-04-13
1
-0
/
+6
*
Supporting edge information during mapping.
Alan Mishchenko
2016-04-11
1
-2
/
+2
*
Adding AIG rehashing after LUT mapping in Gia.
Alan Mishchenko
2016-04-07
1
-0
/
+1
*
Supporting edges in delay-optimization in &satlut.
Alan Mishchenko
2016-04-07
1
-0
/
+1
*
Supporting edges in delay-optimization in &satlut.
Alan Mishchenko
2016-04-07
1
-0
/
+8
*
Supporting edge information during mapping.
Alan Mishchenko
2016-04-06
1
-0
/
+9
*
Improvements to delay-optimization in &satlut.
Alan Mishchenko
2016-04-04
1
-1
/
+1
*
Improvements to delay-optimization in &satlut.
Alan Mishchenko
2016-04-04
1
-0
/
+1
*
Enabling native Gia visualization in &show.
Alan Mishchenko
2016-04-03
1
-2
/
+6
*
Windowing for technology mapping.
Alan Mishchenko
2016-03-30
1
-1
/
+22
*
Windowing for technology mapping.
Alan Mishchenko
2016-03-29
1
-12
/
+21
*
New command to dump LUT network.
Alan Mishchenko
2016-01-16
1
-0
/
+1
*
Adding switch &miter -x for XORs outputs of two word-level POs.
Alan Mishchenko
2016-01-06
1
-0
/
+1
*
Migrating back to using 'float' in area-flow computation in &nf.
Alan Mishchenko
2016-01-05
1
-0
/
+1
*
Improvements to 'satclp' (unfinished).
Alan Mishchenko
2015-11-06
1
-0
/
+2
*
Improvements to 'satclp'.
Alan Mishchenko
2015-10-28
1
-0
/
+1
*
Added several knobs to control QoR in &nf.
Alan Mishchenko
2015-10-20
1
-0
/
+2
*
Adding support for black boxes in extended AIG.
Alan Mishchenko
2015-10-04
1
-0
/
+1
*
Adding support for flop init-states in extended AIG.
Alan Mishchenko
2015-10-04
1
-0
/
+1
*
Experiments with LUT structure mapping.
Alan Mishchenko
2015-09-27
1
-0
/
+3
*
Improvements to &b -das.
Alan Mishchenko
2015-09-18
1
-0
/
+1
*
Adding switch to &b to prevent dumplicated area when used in delay-mode (&b -...
Alan Mishchenko
2015-09-18
1
-1
/
+1
*
Performance tuning of the Nf.
Alan Mishchenko
2015-08-31
1
-0
/
+3
*
Adding switch to control area-recovery and more tuning in &nf.
Alan Mishchenko
2015-08-28
1
-0
/
+1
*
Adding new GIA duplication API.
Alan Mishchenko
2015-07-21
1
-0
/
+1
*
New TFI/TFO profiling code.
Alan Mishchenko
2015-07-09
1
-1
/
+3
*
Small changes to enable collecting results using &ps -D file.
Alan Mishchenko
2015-07-09
1
-0
/
+2
*
Sequential word-level simulator for Wlc_Ntk_t.
Alan Mishchenko
2015-06-04
1
-0
/
+3
*
Properly copying and saving the timing info in &get and &put.
Alan Mishchenko
2015-04-04
1
-0
/
+2
*
Print-out of sequential equivalences in &scorr.
Alan Mishchenko
2015-03-31
1
-1
/
+1
*
Support for representing programmable cell configuration data.
Alan Mishchenko
2015-03-08
1
-0
/
+2
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