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path: root/src/aig/gia/giaIf.c
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* Small changes to enable collecting results using &ps -D file.Alan Mishchenko2015-07-091-7/+14
* Temp change in the AIG reader and minor tuning.Alan Mishchenko2015-07-081-0/+2
* C++ compiler typecast problem.Alan Mishchenko2015-07-081-1/+1
* Copying prog cell data.Alan Mishchenko2015-05-211-0/+5
* Making sure the names are transfered when &get -n is used.Alan Mishchenko2015-04-041-0/+5
* Properly copying and saving the timing info in &get and &put.Alan Mishchenko2015-04-041-0/+2
* Enable arrival/required times in &nf.Alan Mishchenko2015-03-151-0/+5
* Compiler warnings.Alan Mishchenko2015-03-081-3/+3
* Support for representing programmable cell configuration data.Alan Mishchenko2015-03-081-29/+78
* Exprimental features in tech-mapping.Alan Mishchenko2014-12-211-110/+142
* Exprimental features in tech-mapping.Alan Mishchenko2014-12-211-1/+40
* Adding new mapping feature.Alan Mishchenko2014-12-111-1/+7
* Integrating barrier buffers.Alan Mishchenko2014-12-111-2/+15
* Changes to history recording and other small things.Alan Mishchenko2014-11-301-3/+13
* Improvements to handling boxes and flops.Alan Mishchenko2014-11-241-3/+4
* MUX decomposition during mapping.Alan Mishchenko2014-10-131-5/+19
* MUX decomposition during mapping.Alan Mishchenko2014-10-121-8/+15
* MUX decomposition during mapping.Alan Mishchenko2014-10-121-7/+10
* MUX decomposition during mapping.Alan Mishchenko2014-10-111-25/+121
* Deriving network in terms of programmable cells.Alan Mishchenko2014-10-111-5/+12
* Compiler warnings.Alan Mishchenko2014-10-081-1/+1
* Detection of threshold functions.Alan Mishchenko2014-10-081-9/+11
* Deriving cell mapping with &if -kz.Alan Mishchenko2014-10-041-8/+60
* Deriving AIG after cell mapping.Alan Mishchenko2014-10-031-0/+29
* Bug fix in transferring timing info.Alan Mishchenko2014-09-091-1/+1
* Improvements to DSD balancing.Alan Mishchenko2014-08-271-5/+5
* Adding commands to save/load best network.Alan Mishchenko2014-08-261-2/+56
* Improvements to the timing manager.Alan Mishchenko2014-08-251-5/+1
* Improving GIA interfaces for some procedures.Alan Mishchenko2014-08-251-42/+58
* Correcting incorrect handling of timing in several &-commands.Alan Mishchenko2014-08-251-3/+6
* Propagating timing support to the new synthesis/mapping commands.Alan Mishchenko2014-08-201-19/+9
* Adding delay optimization to synthesis script &syn2.Alan Mishchenko2014-08-081-0/+32
* Adding new command &sopb for resource-aware SOP balancing.Alan Mishchenko2014-07-211-0/+26
* Updates and changes to several packages.Alan Mishchenko2014-07-201-9/+12
* Small changes in several packages.Alan Mishchenko2014-07-181-1/+1
* Small changes in several packages.Alan Mishchenko2014-07-171-2/+3
* Small changes in several packages.Alan Mishchenko2014-07-171-1/+52
* Experiment with SOP balancing.Alan Mishchenko2014-07-021-1/+20
* Improvements to representation of choices.Alan Mishchenko2014-07-011-4/+4
* Adding a feature to collapse hierarhical AIGs.Alan Mishchenko2014-06-051-1/+6
* Correcting switching activity computation.Alan Mishchenko2014-06-051-9/+1
* Added optimization for average rather than maximum delay.Alan Mishchenko2014-04-191-4/+0
* Added structural hashing by default after if -g and &if -g.Alan Mishchenko2014-04-191-2/+3
* Adding color to mapping stats.Alan Mishchenko2014-04-191-3/+3
* Adding color to mapping stats.Alan Mishchenko2014-04-191-3/+27
* Improvements to DSD balancing.Alan Mishchenko2014-04-191-0/+2
* Adding print-out of average level.Alan Mishchenko2014-04-191-2/+6
* New feature to optimize delay during mapping.Alan Mishchenko2014-04-111-1/+2
* Improvements to DSD in technology mapping.Alan Mishchenko2014-04-111-1/+2
* New feature to optimize delay during mapping.Alan Mishchenko2014-04-111-4/+6
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