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path: root/src/aig/gia/giaIf.c
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* Rare bug fix in mapping with choices.Alan Mishchenko2020-10-291-0/+38
* Memory leaks.Alan Mishchenko2020-09-281-0/+1
* Memory leaks.Alan Mishchenko2020-09-251-0/+1
* Adding a new feature to decompose special 6-input cuts.Alan Mishchenko2019-10-261-0/+28
* Making &mfs work with boxes larger than 6 inputs. Adding option &if -w to pri...Alan Mishchenko2019-09-191-0/+7
* Undoing some of the previous changes.Alan Mishchenko2018-11-151-1/+5
* Several recent bug fixes.Alan Mishchenko2018-11-041-3/+2
* Fix timing info communication in GIA APIs.Alan Mishchenko2018-10-231-0/+1
* Fix timing info communication in GIA APIs.Alan Mishchenko2018-10-231-0/+1
* Fix timing info communication in GIA APIs.Alan Mishchenko2018-10-221-1/+15
* Maintenance and updates.Alan Mishchenko2017-09-241-4/+4
* Maintenance and updates.Alan Mishchenko2017-09-201-0/+4
* Compiler warnings.Alan Mishchenko2017-07-221-3/+3
* Supporting CO attributes in GIA.Alan Mishchenko2017-07-121-1/+8
* Merged in boschmitt/abc (pull request #77)Alan Mishchenko2017-07-041-1/+1
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| * Small fixes for C++ compilersBruno Schmitt2017-07-041-1/+1
* | Synchronizing various data-structures.Alan Mishchenko2017-07-041-1/+94
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* Outputting cell configurations.Alan Mishchenko2017-06-021-3/+51
* Small fixes and a change to &cec to allow two files names given as command-li...Alan Mishchenko2017-01-211-8/+8
* Updates to delay optimization project.Alan Mishchenko2017-01-021-16/+16
* Infrastructure for using the results of exact SAT-based synthesis during mapp...Alan Mishchenko2016-07-291-6/+6
* Adding option to rehash AIG after mapping.Alan Mishchenko2016-04-271-3/+2
* Improved algo for edge computation.Alan Mishchenko2016-04-241-2/+5
* Improved algo for edge computation.Alan Mishchenko2016-04-221-2/+5
* Supporting edge information during mapping.Alan Mishchenko2016-04-111-1/+2
* Adding AIG rehashing after LUT mapping in Gia.Alan Mishchenko2016-04-071-1/+56
* Windowing for technology mapping.Alan Mishchenko2016-03-301-5/+5
* Windowing for technology mapping.Alan Mishchenko2016-03-291-0/+24
* Adding support for flop init-states in extended AIG.Alan Mishchenko2015-10-041-0/+1
* Experiments with LUT structure mapping.Alan Mishchenko2015-09-301-2/+6
* Small changes to enable collecting results using &ps -D file.Alan Mishchenko2015-07-091-7/+14
* Temp change in the AIG reader and minor tuning.Alan Mishchenko2015-07-081-0/+2
* C++ compiler typecast problem.Alan Mishchenko2015-07-081-1/+1
* Copying prog cell data.Alan Mishchenko2015-05-211-0/+5
* Making sure the names are transfered when &get -n is used.Alan Mishchenko2015-04-041-0/+5
* Properly copying and saving the timing info in &get and &put.Alan Mishchenko2015-04-041-0/+2
* Enable arrival/required times in &nf.Alan Mishchenko2015-03-151-0/+5
* Compiler warnings.Alan Mishchenko2015-03-081-3/+3
* Support for representing programmable cell configuration data.Alan Mishchenko2015-03-081-29/+78
* Exprimental features in tech-mapping.Alan Mishchenko2014-12-211-110/+142
* Exprimental features in tech-mapping.Alan Mishchenko2014-12-211-1/+40
* Adding new mapping feature.Alan Mishchenko2014-12-111-1/+7
* Integrating barrier buffers.Alan Mishchenko2014-12-111-2/+15
* Changes to history recording and other small things.Alan Mishchenko2014-11-301-3/+13
* Improvements to handling boxes and flops.Alan Mishchenko2014-11-241-3/+4
* MUX decomposition during mapping.Alan Mishchenko2014-10-131-5/+19
* MUX decomposition during mapping.Alan Mishchenko2014-10-121-8/+15
* MUX decomposition during mapping.Alan Mishchenko2014-10-121-7/+10
* MUX decomposition during mapping.Alan Mishchenko2014-10-111-25/+121
* Deriving network in terms of programmable cells.Alan Mishchenko2014-10-111-5/+12
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