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path: root/src/aig/gia/giaMan.c
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* Adding switch &w -n to modify the comment section of the AIGER file written.Alan Mishchenko2018-11-211-2/+2
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* Adding switch &w -p to dump AIG in a Verilog file.Alan Mishchenko2018-04-251-0/+185
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* Adding parameters and improvements to %blast.Alan Mishchenko2018-02-281-3/+3
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* Experiments with SAT-based simulation.Alan Mishchenko2018-01-231-0/+2
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* Improvements to AIG-based quantification.Alan Mishchenko2017-11-261-0/+1
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* Extracting CSAT interface and several cleanups.Alan Mishchenko2017-11-131-1/+1
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* Changes to make GIA structural hashing use a dedicated array instead of ↵Alan Mishchenko2017-11-131-2/+4
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* Improvements to quantification.Alan Mishchenko2017-11-131-0/+2
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* Profiling quantification and other changes.Alan Mishchenko2017-11-061-0/+1
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* Small fix. Garanteeing pPars is not NULL before checking pPars->fSlacksBruno Schmitt2017-10-241-1/+1
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* Adding printout of slack distribution for mapped networks.Alan Mishchenko2017-10-021-0/+320
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* Supporting CO attributes in GIA.Alan Mishchenko2017-07-121-0/+1
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* Synchronizing various data-structures.Alan Mishchenko2017-07-041-0/+3
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* Adding new command 'dump_equiv'.Alan Mishchenko2016-07-211-0/+2
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* Experiments with CEC for arithmetic circuits.Alan Mishchenko2016-05-111-0/+1
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* Experimental algorithm for edge optimization.Alan Mishchenko2016-04-131-0/+2
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* Supporting edge information during mapping.Alan Mishchenko2016-04-111-1/+1
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* Supporting edge information during mapping.Alan Mishchenko2016-04-061-0/+26
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* Windowing for technology mapping.Alan Mishchenko2016-03-301-0/+1
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* Windowing for technology mapping.Alan Mishchenko2016-03-291-1/+1
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* Adding support for black boxes in extended AIG.Alan Mishchenko2015-10-041-0/+2
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* Adding support for flop init-states in extended AIG.Alan Mishchenko2015-10-041-0/+1
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* New constraint manager and memory reporting 'ps'.Alan Mishchenko2015-09-081-0/+7
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* Support for representing programmable cell configuration data.Alan Mishchenko2015-03-081-0/+2
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* Diabling pin-permutation in &nf mapper.Alan Mishchenko2015-02-081-0/+1
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* Integrating barrier buffers.Alan Mishchenko2014-12-081-0/+2
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* Improvements to handling boxes and flops.Alan Mishchenko2014-11-251-1/+1
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* Adding integrity check for boxes and flops.Alan Mishchenko2014-11-251-4/+17
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* Improvements to handling boxes and flops.Alan Mishchenko2014-11-251-1/+1
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* Improvements to handling boxes and flops.Alan Mishchenko2014-11-241-5/+7
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* Fix in reading flop classes.Alan Mishchenko2014-11-211-8/+7
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* Fix in reading flop classes.Alan Mishchenko2014-11-211-1/+7
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* Integrating mfs2 package to work with boxes.Alan Mishchenko2014-11-161-0/+1
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* Generation of barrier-buffers for hierarchical design.Alan Mishchenko2014-11-101-0/+1
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* Improvements to DSD balancing.Alan Mishchenko2014-08-271-1/+1
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* Improvements to the timing manager.Alan Mishchenko2014-08-251-2/+4
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* Adding support for standard-cell mapping.Alan Mishchenko2014-07-281-0/+1
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* Improvements to representation of choices.Alan Mishchenko2014-07-011-4/+2
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* Improvements to power-aware mapping.Alan Mishchenko2014-06-231-5/+9
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* Experiments with balancing.Alan Mishchenko2014-06-221-1/+1
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* New tools for profiling verification miters.Alan Mishchenko2014-06-201-0/+39
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* Various modifications.Alan Mishchenko2014-06-121-24/+5
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* Various modifications.Alan Mishchenko2014-06-101-3/+18
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* Adding CEC command &splitprove.Alan Mishchenko2014-06-041-0/+1
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* Adding color to sizing stats.Alan Mishchenko2014-04-191-0/+7
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* Adding color to mapping stats.Alan Mishchenko2014-04-191-0/+17
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* Adding print-out of average level.Alan Mishchenko2014-04-191-1/+4
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* Experiments with recent ideas.Alan Mishchenko2014-03-201-6/+14
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* Experiments with recent ideas.Alan Mishchenko2014-03-191-0/+39
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* Experiments with recent ideas.Alan Mishchenko2014-03-191-0/+1
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