iCE40/abc - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Adding switch &w -n to modify the comment section of the AIGER file written.	Alan Mishchenko	2018-11-21	1	-3/+3
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*	Procedures to verify equivalence classes.	Alan Mishchenko	2018-11-11	1	-1/+139
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*	Procedure to return seq equivalences.	Alan Mishchenko	2018-07-22	1	-0/+68
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*	Making sure duplicated inverters are not created.	Alan Mishchenko	2018-04-11	1	-3/+9
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*	Extending MiniLUT to return attributes.	Alan Mishchenko	2018-02-11	1	-0/+19
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*	Adding API to dump MiniAIG into a Verilog file and other small changes.	Alan Mishchenko	2017-10-22	1	-0/+1
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*	Compiler warnings.	Alan Mishchenko	2017-07-22	1	-1/+1
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*	Bug fix in MiniLUT APIs.	Alan Mishchenko	2017-07-12	1	-1/+31
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*	Making MiniLUT work for more than 6 inputs.	Alan Mishchenko	2017-07-08	1	-17/+38
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*	Synchronizing various data-structures.	Alan Mishchenko	2017-07-04	1	-10/+124
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*	Corner-case bug in MiniLUT.	Alan Mishchenko	2017-01-25	1	-0/+1
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*	Dealing wit COs driven by inverters in MiniLUT.	Alan Mishchenko	2017-01-06	1	-2/+38
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*	Adding support for minimalistic representation of LUT mapping.	Alan Mishchenko	2016-12-05	1	-1/+1
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*	Adding support for minimalistic representation of LUT mapping.	Alan Mishchenko	2016-12-05	1	-0/+182
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*	Reading/writing MiniAIG and several minor changes.	Alan Mishchenko	2013-05-03	1	-0/+2
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*	Reading/writing MiniAIG and several minor changes.	Alan Mishchenko	2013-05-03	1	-0/+187