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iCE40/abc
yosys-experimental
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path:
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src
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aig
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gia
/
giaMini.c
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Author
Age
Files
Lines
*
Making sure duplicated inverters are not created.
Alan Mishchenko
2018-04-11
1
-3
/
+9
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*
Extending MiniLUT to return attributes.
Alan Mishchenko
2018-02-11
1
-0
/
+19
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*
Adding API to dump MiniAIG into a Verilog file and other small changes.
Alan Mishchenko
2017-10-22
1
-0
/
+1
|
*
Compiler warnings.
Alan Mishchenko
2017-07-22
1
-1
/
+1
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*
Bug fix in MiniLUT APIs.
Alan Mishchenko
2017-07-12
1
-1
/
+31
|
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Making MiniLUT work for more than 6 inputs.
Alan Mishchenko
2017-07-08
1
-17
/
+38
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*
Synchronizing various data-structures.
Alan Mishchenko
2017-07-04
1
-10
/
+124
|
*
Corner-case bug in MiniLUT.
Alan Mishchenko
2017-01-25
1
-0
/
+1
|
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Dealing wit COs driven by inverters in MiniLUT.
Alan Mishchenko
2017-01-06
1
-2
/
+38
|
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Adding support for minimalistic representation of LUT mapping.
Alan Mishchenko
2016-12-05
1
-1
/
+1
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Adding support for minimalistic representation of LUT mapping.
Alan Mishchenko
2016-12-05
1
-0
/
+182
|
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Reading/writing MiniAIG and several minor changes.
Alan Mishchenko
2013-05-03
1
-0
/
+2
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Reading/writing MiniAIG and several minor changes.
Alan Mishchenko
2013-05-03
1
-0
/
+187