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path: root/src/aig/gia
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* Experiments with simulation.Alan Mishchenko2019-10-275-7/+152
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* Adding a new feature to decompose special 6-input cuts.Alan Mishchenko2019-10-261-0/+28
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* Making &mfs work with boxes larger than 6 inputs. Adding option &if -w to ↵Alan Mishchenko2019-09-192-2/+9
| | | | print delay profile.
* Bug fix in &trace.Alan Mishchenko2019-09-181-0/+1
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* Upgrading reparametrization to perform (non-range-equivalent) removal of logic.Alan Mishchenko2019-09-041-0/+56
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* Adding new switch to &genqfb to use output as an enable in the miter.Alan Mishchenko2019-07-301-3/+14
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* Preserving boxes after &write.Alan Mishchenko2019-07-251-6/+2
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* Bug fix in &mfs.Alan Mishchenko2019-07-251-0/+2
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* Fixing some update gcc.Alan Mishchenko2019-07-242-2/+2
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* Adding command &permute.Alan Mishchenko2019-07-021-0/+45
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* Adding command &print_truth to print truth tables for primary outputs.Alan Mishchenko2019-05-251-0/+34
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* Corner case bug fix in reducing equivalences.Alan Mishchenko2019-05-241-1/+2
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* Fixing recent change to 'print_stats'.Alan Mishchenko2019-05-111-2/+2
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* Experiment with frontier cut computation.Alan Mishchenko2019-05-011-0/+15
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* Adding switch &st -s for MUX restructring.Alan Mishchenko2019-04-211-0/+74
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* Adding miter construction with one bit-level output for each pair of ↵Alan Mishchenko2019-04-141-1/+1
| | | | word-level outputs (small fix).
* Adding miter construction with one bit-level output for each pair of ↵Alan Mishchenko2019-04-142-0/+8
| | | | word-level outputs.
* Converting dch-style equivalences into scorr-style ones.Alan Mishchenko2019-04-051-0/+12
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* Updating canonical form computation procedures (compiler warnings).Alan Mishchenko2019-03-051-1/+1
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* Fixing several other type conversion warnings.Alan Mishchenko2019-03-051-24/+24
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* Fixing some warnings by adding cast from 'int' to 'size_t' in memset, ↵Alan Mishchenko2019-03-055-16/+16
| | | | memcpy, etc.
* Fixing some warnings with -Wconversion.Alan Mishchenko2019-03-051-1/+1
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* Adding switch -x to &ps to disable color printout.Alan Mishchenko2019-02-122-1/+18
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* Exploring other ways of CEX writing.Alan Mishchenko2019-01-215-6/+9
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* Experiment with partitioned &scorr.Alan Mishchenko2019-01-151-0/+185
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* Adding one API of GIA manager.Alan Mishchenko2019-01-121-0/+18
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* Bug fix in deriving names for the miter output.Alan Mishchenko2019-01-101-4/+9
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* Fixing float overflow during area-flow computation in &lf.Alan Mishchenko2018-12-131-0/+8
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* Adding switch &w -n to modify the comment section of the AIGER file written.Alan Mishchenko2018-11-2110-17/+16
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* Adding an option to write new-line after the comment symbol when dumping an ↵Alan Mishchenko2018-11-201-2/+7
| | | | AIGER file.
* Undoing some of the previous changes.Alan Mishchenko2018-11-151-1/+5
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* Procedures to verify equivalence classes.Alan Mishchenko2018-11-111-1/+139
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* Several recent bug fixes.Alan Mishchenko2018-11-041-3/+2
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* Fix timing info communication in GIA APIs.Alan Mishchenko2018-10-231-0/+1
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* Fix timing info communication in GIA APIs.Alan Mishchenko2018-10-231-0/+1
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* Fix timing info communication in GIA APIs.Alan Mishchenko2018-10-222-1/+27
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* Preserving output names while deriving a miter.Alan Mishchenko2018-09-201-0/+26
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* Preserving names while deriving a miter.Alan Mishchenko2018-09-201-0/+2
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* Procedure to return seq equivalences.Alan Mishchenko2018-07-221-0/+68
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* Compiler warnings.Alan Mishchenko2018-06-081-1/+2
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* Supporting the decoder primitive in NDR and bit-blasting.Alan Mishchenko2018-06-051-1/+1
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* Disabling unused feature in &nf.Alan Mishchenko2018-06-041-0/+2
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* Adding switch &w -p to dump AIG in a Verilog file.Alan Mishchenko2018-04-252-0/+186
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* Making sure duplicated inverters are not created.Alan Mishchenko2018-04-111-3/+9
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* Integrating SAT-based CEX minimization (bug fix).Alan Mishchenko2018-03-251-4/+8
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* Integrating SAT-based CEX minimization.Alan Mishchenko2018-03-251-2/+106
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* Updating &mfs to support hard objects.Alan Mishchenko2018-03-231-2/+25
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* Adding parameters and improvements to %blast.Alan Mishchenko2018-02-281-3/+3
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* Improvements to circuit based solver.Alan Mishchenko2018-02-201-33/+81
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* Improvements to circuit based solver.Alan Mishchenko2018-02-171-193/+490
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